CN100377198C - Single time pulse driving shift temporary storage and display driving circuit using it - Google Patents
Single time pulse driving shift temporary storage and display driving circuit using it Download PDFInfo
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- CN100377198C CN100377198C CNB2004100704881A CN200410070488A CN100377198C CN 100377198 C CN100377198 C CN 100377198C CN B2004100704881 A CNB2004100704881 A CN B2004100704881A CN 200410070488 A CN200410070488 A CN 200410070488A CN 100377198 C CN100377198 C CN 100377198C
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Abstract
The present invention relates to a single clock pulse driving shifting temporary memory. The single clock pulse driving shifting temporary memory has a multistage architecture, wherein the M stage architecture comprises a latch unit, a logic unit and a non-overlap signal buffer, wherein the latch unit refers to a clock pulse signal, and latches are from input signals of the M-1 stage architecture; the logic unit is connected with the output end of the latch unit so as to carry out NAND logical operation to output signals of the latch unit and the clock pulse signal. Besides, the non-overlap signal buffer is connected with the output end of the logic unit and comprises two reversers which are mutually connected in series, wherein output signals of the first reverser which is coupled with the output end of the logic unit are fed into the latch unit of the M+1 stage architecture; meanwhile, output signals of the non-overlap signal buffer of the M-1 stage architecture are fed into the non-overlap signal buffer of the M stage architecture or the logic unit of the M stage architecture so as to delay the output signals of the non-overlap signal buffer.
Description
Technical field
The present invention is about a kind of single time pulse driving shift temporary storage (Single Clock Driven Shift Register) that is used for circuit of display driving, especially a kind of single time pulse driving shift temporary storage that improves the output signal overlapping phenomenon.
Background technology
Advantages such as LCD (LCD) is frivolous owing to having possessed, power saving, no width of cloth ray, and replace traditional iconoscope (CRT) display gradually, be widely used in the electronic products such as desktop PC, personal digital aid (PDA), mobile computer, digital camera and mobile phone.
(Active Matrix Liquid Crystal Display AMLCD) is the light transmittance that utilizes the electric field controls liquid crystal, to reach the purpose of display frame to active-matrix formula LCD.Please refer to shown in Figure 1A, a typical active-matrix formula LCD 10 comprises a display panels 20 and a drive system 30.Wherein, has a picture element matrix (pixelarray) 22 on the display panels 20.Drive system 30 comprises a control circuit 32, one source pole driving circuit (sourcedriver) 34 and scan driving circuit (scan driver) 36.Each pixel components 122 is to be electrically connected to a thin film transistor (TFT) 124 in the picture element matrix 22, and the source electrode of this thin film transistor (TFT) 124 is electrically connected to source electrode drive circuit 34, grid is electrically connected to scan drive circuit 36, to use the running of switch control pixel components 122 as.
The extraneous shows signal DS that provides of control circuit 32 conversions, producing video data D, horizontal clock signal HCK and horizontal activation signal HST provides to source electrode drive circuit 34, simultaneously, also producing vertical clock signal VCK provides to scan drive circuit 36 with vertical activation signal VST.Please refer to shown in Figure 1B, source electrode drive circuit 34 comprises a shift registor (Shift Register) 342 and a plurality of sampling locks (Sampling Gate) 344.Wherein, each sampling lock 344 corresponds in the picture element matrix 22 pixel components 122 with delegation.Import in regular turn in each sampling lock 344 to produce sampled signal (sampling signal) Sa in horizontal clock signal HCK and the horizontal activation signal HST input shift registor 342.Feeding has the sampling lock 344 of sampled signal Sa to open, so that video data D is passed through in these sampling lock 344 input picture element matrixes 22.
Please refer to shown in Figure 2ly, is the circuit diagram of a typical shift registor 40.While also please refer to shown in Figure 3, shows the mode chart of the electric signal of diverse locations in this shift registor 40.Single clock pulse that this shift registor 40 1 has multistage (Stage) framework drives true single-phase dynamic (True Single PhaseDynamic Circuit, TSPC) shift registor.Wherein, the M level framework comprises a bolt-lock (latch) unit 42, a NAND logical block 44 and a reverser 46.Bolt-lock unit 42 is subjected to a horizontal clock signal HCK and controls, and, in this bolt-lock unit 42 of output signal S (m-1) feed-in from the M-1 level framework.It should be noted that with regard to the first order framework signal of feed-in bolt-lock unit 42 is aforementioned levels activation signal HST.
NAND logical block 44 is connected in the output terminal of bolt-lock unit 42, carries out the logical operation of NAND with output signal A and horizontal clock signal HCK with bolt-lock unit 42.Reverser 46 is connected in the output terminal of NAND logical block 44, with the polarity of the output signal B that changes NAND logical block 44.Please be simultaneously with reference to shown in Figure 1, the output signal S of this reverser 46 (m) is aforesaid sampled signal Sa, and its feed-in sampling lock 344 is to take a sample to video data D, simultaneously, the also bolt-lock unit 42 of feed-in M+1 level framework is as the input signal of M+1 level framework.
Please refer to shown in Fig. 4 A, drive the emulation output waveform figure of true single-phase dynamic level Four framework shift registor for the single clock pulse of typical case.V among the figure (STX) promptly corresponds to horizontal start signal HST, and V (CLK) promptly corresponds to horizontal clock signal HCK, and V (OUT_A1) represents the output signal of the first order to fourth stage framework respectively to V (OUT_A4), promptly corresponds to S (1) to S (4).
Please be simultaneously with reference to shown in Fig. 4 B, the enlarged drawing of the emulation output waveform of adjacent two level frameworks of shift registor for this reason.As shown in FIG., the emulation output signal V (OUT_A1) of adjacent two level frameworks has obvious overlapping generation with the boundary of the waveform of V (OUT_A2).In other words, shift registor sample signal of importing each sampling lock will overlap phenomenon thus, and to the accuracy of sampling, and even the correctness that shows of picture causes and seriously influences.
More than be to be described at the shift registor 342 in the source class driving circuit 34.Yet, a shift registor is also arranged in the scan drive circuit 36, produce sweep signal by in the row input picture element matrix 22 according to vertical clock signal VCK and vertical activation signal VST.This shift registor that is positioned at scan drive circuit 36 also may produce the situation shown in Fig. 4 B, the phenomenon that the sweep signal of just adjacent two level frameworks output overlaps.This overlapping phenomenon is connected to the correctness of the opening and closing time of each thin film transistor (TFT) 124 with influence, seriously influences and the correctness that video data D writes picture element matrix 22 caused.
The present invention adopts a zero lap technology, improves the overlapping problem of traditional shift registor output signal, so that the sampling of display data is more accurate with the action that data writes.
Summary of the invention
Fundamental purpose of the present invention is at traditional single time pulse driving shift temporary storage, and its output signal is overlapping and influence the problem of display picture correctness, proposes a kind of method of solution.
The invention provides a kind of flat display driving circuit, it has a kind of single time pulse driving shift temporary storage, according to a clock pulse signal and an initial signal, to produce sampled signal or sweep signal.This single time pulse driving shift temporary storage has multistage (Stage) framework, and wherein, the M level framework comprises a bolt-lock (latch) unit, a logical block and a zero lap signal buffer (Non-overlapbuffer).The bolt-lock unit is according to a clock pulse signal, and bolt-lock is from the input signal of M-1 level framework.Logical block is connected in the output terminal of bolt-lock unit, carries out logical operation with output signal and clock signal to the bolt-lock unit.The zero lap signal buffer is connected in the output terminal of logical block, comprises at least three reversers of serial connection mutually.And, be coupled to the output signal of the odd number reverser of logical block output terminal, be in the bolt-lock unit of feed-in M+1 level framework.Simultaneously, from the output signal of the zero lap signal buffer of M-1 level framework, be the zero lap signal buffer or the logical block of this M level framework of feed-in, to postpone the output signal of zero lap signal buffer.
A kind of single time pulse driving shift temporary storage has multistage architecture, and the M level framework comprises:
One bolt-lock unit is according to a clock pulse signal, with the input signal of bolt-lock from the M-1 level framework;
One logical block is connected in the output terminal of this bolt-lock unit, and output signal and this clock signal of this bolt-lock unit carried out logical operation; And
One zero lap signal buffer is connected in the output terminal of this logical block, comprises at least three reversers of serial connection mutually;
Wherein, in this zero lap signal buffer, be coupled to the output signal of this odd number reverser of this logical block output terminal, it is the bolt-lock unit of feed-in M+1 level framework, and, the output signal of the zero lap signal buffer of M-1 level framework, this zero lap signal buffer of feed-in or this logical block, to postpone the output signal of this zero lap signal buffer, in the bolt-lock unit of this M level framework, be subjected to the transistor that this clock signal is controlled, in the bolt-lock unit of M+1 level framework, be subjected to the transistor that this clock signal is controlled, be respectively a N type and the staggered transistor of a P type, and, in the bolt-lock unit of this M level framework, being subjected to the transistor that this clock signal controls is the N type, and this clock signal is imported this logical block again after counter-rotating.
Description of drawings
Fig. 1 is the block schematic diagram of a typical active-matrix formula LCD.
Fig. 2 is the circuit diagram of a typical shift registor.
Fig. 3 is in the displayed map 2 typical shift registors, the mode chart of the electric signal of diverse location.
Fig. 4 A is the emulation output waveform figure that typical single clock pulse drives level Four framework shift registor.
Fig. 4 B is among Fig. 4 A, the enlarged drawing of the emulation output waveform of adjacent two level frameworks.
Fig. 5 is the block schematic diagram of drive system one preferred embodiment of the present invention.
Fig. 6 is the circuit diagram of single time pulse driving shift temporary storage one preferred embodiment of the present invention.
Fig. 7 is the circuit diagram of another embodiment of single time pulse driving shift temporary storage of the present invention.
Fig. 8 A drives the emulation output waveform figure of level Four framework shift registor for the single clock pulse of the present invention.
Fig. 8 B is among Fig. 8 A, the enlarged drawing of the emulation output waveform of adjacent two level frameworks.
Symbol description:
Thin film transistor (TFT) 124 drive systems 30,50
Logical block 44,724 reversers 46,728
Single time pulse driving shift temporary storage 72 zero lap signal buffers 726
Embodiment
Please refer to shown in Figure 5ly, be the block schematic diagram of drive system 50 1 preferred embodiments of the present invention.As shown in FIG., this drive system 50 comprises a control circuit 60, one source pole driving circuit (sourcedriver) 70 and scan driving circuit (scan driver) 80.Wherein, control circuit 60 provides video data D, horizontal clock signal HCK and horizontal activation signal HST to source electrode drive circuit 70, simultaneously, also provides vertical clock signal VCK and vertical activation signal VST to scan drive circuit 80.Source electrode drive circuit 70 comprises a single time pulse driving shift temporary storage 72 and a plurality of sampling locks 74, wherein, each sampling lock 74 in the picture element matrix (not icon) that corresponds to display panel with the picture element of delegation.Horizontal clock signal HCK and horizontal activation signal HST from control circuit 60 are in the input single time pulse driving shift temporary storage 72, import each sampling lock 74 in regular turn to produce sampled signal (sampling signal) Sa.Feeding has the sampling lock 74 of sampled signal Sa to open, and is imported line by line in the picture element matrix so that video data D passes through this sampling lock 74.
Please refer to shown in Figure 6ly, be the circuit diagram of single time pulse driving shift temporary storage 72 1 preferred embodiments of Fig. 5.For simplicity, among the figure only the framework (Stage) with regard to M level to the M+1 level of this single time pulse driving shift temporary storage 72 describe.As shown in FIG., each level framework of this single time pulse driving shift temporary storage 72 all has a bolt-lock (latch) unit 722, a logical block 724 and a zero lap signal buffer (Non-overlap buffer) 726.
With regard to the framework of M level, bolt-lock unit 722 wherein is subjected to a horizontal clock signal HCK and controls, and according to this horizontal clock signal HCK, bolt-lock is from the input signal INP (M) of M-1 level framework (previous stage framework).The action of this bolt-lock will prolong input signal INP (M), and the time point of the change in voltage of the decline time point of its voltage and horizontal clock signal HCK is matched.It should be noted that the first order framework for single time pulse driving shift temporary storage 72 of the present invention, the input signal of previous stage framework is that INP (1) is aforementioned horizontal activation signal HST from control circuit 60.
Zero lap signal buffer 726 is connected in the output terminal of logical block 724, and this zero lap signal buffer 726 is made of three reversers (inverter) that are connected in series mutually.Wherein, be coupled to the output signal of first reverser of logical block 724 output terminals, in the bolt-lock unit 722 as input signal INP (M+1) feed-in M+1 level framework (next stage framework).
Secondly, the output signal D of this zero lap signal buffer 726 (M) is except importing the sampling lock 74, also in the zero lap signal buffer 726 of feed-in M+1 level framework (next stage framework) as sampled signal Sa.Same, from the output signal D (M-1) of the zero lap signal buffer 726 of M-1 level framework (previous stage framework), in this M level zero lap signal buffer 726 of feed-in.With regard to a preferred embodiment, this output signal D (M-1) is coupled to second reverser of logical block 724 output terminals for feed-in, so that the voltage rising time point of the output signal of this reverser postpones backward.And then the voltage rising time point of zero lap signal buffer 726 output signal D (M) is postponed backward, to alleviate the overlapping phenomenon of output signal D (M-1) and D (M).
As above-mentioned, as seen, zero lap signal buffer 726 of the present invention is not limited in by three reversers and is constituted, but can be connected in series more reverser according to demand.And in the case, in this zero lap signal buffer 726, be coupled to the output signal of the odd number reverser of logical block 724 output terminals, all can be used as in the bolt-lock unit 722 of input signal INP (M+1) feed-in M+1 level framework (next stage framework).In addition, output signal D (M-1) from the zero lap signal buffer 726 of M-1 level framework (previous stage framework), in can this zero lap signal buffer 726 of feed-in, be coupled to the even number reverser of logical block 724 output terminals, and can reach the purpose of the voltage rising time point of delaying output signal D (M) equally.
As described above, because the output signal D (M) of zero lap signal buffer 726, i.e. sampled signal Sa described in Fig. 5.And see through the voltage rising time point of the running of zero lap signal buffer 726 with delay output signal D (M), can alleviate the overlapping phenomenon of sampled signal Sa, and then improve the accuracy of sampling.
It should be noted that, for the hydrous water positive-negative polarity variation of arteries and veins signal HCK at ordinary times, in the bolt-lock unit 722 of M level framework, being subjected to the transistor that horizontal clock signal HCK controlled is a N transistor npn npn, and in the bolt-lock unit 722 of M+1 level framework, being subjected to the transistor that horizontal clock signal HCK controlled is a P shape transistor.That is to say that in the bolt-lock unit 722 of adjacent two level frameworks, it is opposite to be subjected to the transistorized polarity that horizontal clock signal HCK controlled.Same, for the hydrous water positive-negative polarity variation of arteries and veins signal HCK at ordinary times, and make logical block 724 normal operations, if the transistor that horizontal clock signal HCK is controlled is the N type, after then horizontal clock signal HCK must reverse through a reverser 728, and then in the input logic unit 724.
Please refer to shown in Figure 7ly, be the circuit diagram of single time pulse driving shift temporary storage 72 another embodiment of Fig. 5.For simplicity, among the figure only the framework with regard to M level to the M+1 level of this single time pulse driving shift temporary storage 72 describe.Compared to the single time pulse driving shift temporary storage 72 of Fig. 6, the output signal D (M) of the zero lap signal buffer 726 of present embodiment, the logical block 724 of feed-in M+i level framework (next stage framework).Same, from the output signal D (M-1) of the zero lap signal buffer 726 of M-1 level framework (previous stage framework), be in the logical block 724 of this M level of feed-in, so that the voltage rising time point of the output signal of this logical block 724 postpones backward.And then the rising time point of the voltage of zero lap signal buffer 726 output signal D (M) is postponed backward, to alleviate the overlapping phenomenon of output signal D (M-1) and D (M), improve the accuracy of sampling.
Please refer to shown in Fig. 8 A, be the emulation output waveform figure of the single time pulse driving shift temporary storage 72 of Fig. 6.This simulation result is that the shift registor with the level Four framework carries out emulation.V among the figure (STX) promptly corresponds to horizontal start signal HST, and V (CLK) promptly corresponds to horizontal clock signal HCK, and V (OUT_A1) represents the output signal of the first order to fourth stage framework respectively to V (OUT_A4), promptly corresponds to D (1) to D (4).
Please be simultaneously with reference to shown in Fig. 8 B, the enlarged drawing of the emulation output signal V (OUT_A1) of adjacent two level frameworks and the waveform of V (OUT_A2) among Fig. 8 A for this reason.Compared to the output result of Fig. 4 B tradition shift registor, the running of single time pulse driving shift temporary storage of the present invention obviously can relax the overlapping phenomenon of adjacent two level framework output signal V (OUT_A1) and V (OUT_A2).Therefore, shift registor of the present invention can be avoided the overlapping phenomenon of sampled signal, to improve the accuracy of sampling, guarantees the correctness that picture shows simultaneously.
Above embodiment is to be described at the shift registor 72 in the source class driving circuit 70.Yet, a shift registor (not icon) is also arranged in the scan drive circuit 80, vertical clock signal VCK and vertical activation signal VST according to control circuit 60 is produced import in the picture element matrix by row and produce sweep signal.This scan drive circuit 80 also can improve the overlapping phenomenon of the sweep signal of its output by the design of shift registor of the present invention.So that the opening and closing time of each thin film transistor (TFT) is correct in the picture element matrix, and then guarantee that video data correctly writes in the picture element matrix.
Claims (8)
1. a single time pulse driving shift temporary storage has multistage architecture, it is characterized in that the M level framework comprises:
One bolt-lock unit is according to a clock pulse signal, with the input signal of bolt-lock from the M-1 level framework;
One logical block is connected in the output terminal of this bolt-lock unit, and output signal and this clock signal of this bolt-lock unit carried out the NAND logical operation; And
One zero lap signal buffer is connected in the output terminal of this logical block, comprises at least three reversers of serial connection mutually;
Wherein, in this zero lap signal buffer, be coupled to the output signal of the odd number reverser of this logical block output terminal, it is the bolt-lock unit of feed-in M+1 level framework, and, the output signal of the zero lap signal buffer of M-1 level framework, this zero lap signal buffer of feed-in or this logical block, to postpone the output signal of this zero lap signal buffer, in the bolt-lock unit of this M level framework, be subjected to the transistor that this clock signal is controlled, in the bolt-lock unit of M+1 level framework, be subjected to the transistor that this clock signal is controlled, be respectively a N type and the staggered transistor of a P type, and, in the bolt-lock unit of this M level framework, being subjected to the transistor that this clock signal controls is the N type, and this clock signal is imported this logical block again after counter-rotating.
2. single time pulse driving shift temporary storage as claimed in claim 1 is characterized in that, is coupled to the output signal of first reverser of this logical block output terminal, the bolt-lock unit of feed-in M+1 level framework.
3. single time pulse driving shift temporary storage as claimed in claim 1 is characterized in that, the bolt-lock unit of the 1st level framework is according to this clock signal bolt-lock one initial signal, to activate this single time pulse driving shift temporary storage.
4. single time pulse driving shift temporary storage as claimed in claim 1 is characterized in that, this zero lap signal buffer is made of the reverser that odd number is connected in series mutually.
5. single time pulse driving shift temporary storage as claimed in claim 1 is characterized in that, the output signal of the zero lap signal buffer of this M-1 level framework is this zero lap signal buffer of feed-in, is coupled to the even number reverser of this logical block output terminal.
6. a flat-panel screens driving circuit is characterized in that, has a kind of single time pulse driving shift temporary storage, according to a clock pulse signal and an initial signal, produce sampled signal or sweep signal, this single time pulse driving shift temporary storage has multistage architecture, wherein, the M level framework comprises:
One bolt-lock unit is subjected to this clock signal and controls, and, in this bolt-lock unit of the output signal feed-in of M-1 level framework;
One logical block is connected in the output terminal of this bolt-lock unit, carries out the NAND logical operation with output signal and this clock signal with this bolt-lock unit; And
One zero lap signal buffer is connected in the output terminal of this logical block, and the reverser that is connected in series mutually by odd number is constituted;
Wherein, in this zero lap signal buffer, be coupled to the output signal of the odd number reverser of this logical block output terminal, the bolt-lock unit of feed-in M+1 level framework, and, the output signal of the zero lap signal buffer of M-1 level framework, this zero lap signal buffer of feed-in or this logical block, to postpone the output signal of this zero lap signal buffer, in the bolt-lock unit of this M level framework, be subjected to the transistor that this clock signal is controlled, in the bolt-lock unit of M+1 level framework, be subjected to the transistor that this clock signal is controlled, be respectively a N type and the staggered transistor of a P type, and, in the bolt-lock unit of this M level framework, being subjected to the transistor that this clock signal controls is the N type, and this clock signal is imported this logical block again after counter-rotating.
7. flat-panel screens driving circuit as claimed in claim 6 is characterized in that, is coupled to the output signal of first reverser of this logical block output terminal, the bolt-lock unit of feed-in M+1 level framework.
8. flat-panel screens driving circuit as claimed in claim 6 is characterized in that, the output signal of the zero lap signal buffer of this M-1 level framework, and feed-in is coupled to the even number reverser of this logical block output terminal.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100704881A CN100377198C (en) | 2004-08-03 | 2004-08-03 | Single time pulse driving shift temporary storage and display driving circuit using it |
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| CNB2004100704881A CN100377198C (en) | 2004-08-03 | 2004-08-03 | Single time pulse driving shift temporary storage and display driving circuit using it |
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| CN100377198C true CN100377198C (en) | 2008-03-26 |
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| TWI741759B (en) * | 2020-06-16 | 2021-10-01 | 聯詠科技股份有限公司 | Source driver and driving circuit thereof |
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| EP1096467A2 (en) * | 1999-11-01 | 2001-05-02 | Sharp Kabushiki Kaisha | Shift register and image display device |
| CN1404300A (en) * | 2002-09-17 | 2003-03-19 | 统宝光电股份有限公司 | No-overlapping sample pulse signal generator and pulse signal producing method |
| WO2003034393A1 (en) * | 2001-10-17 | 2003-04-24 | Sony Corporation | Display apparatus |
| CN1460883A (en) * | 2002-05-21 | 2003-12-10 | 索尼公司 | Display device |
| JP2004152482A (en) * | 2003-11-20 | 2004-05-27 | Sharp Corp | Shift register and image display device |
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- 2004-08-03 CN CNB2004100704881A patent/CN100377198C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1096467A2 (en) * | 1999-11-01 | 2001-05-02 | Sharp Kabushiki Kaisha | Shift register and image display device |
| WO2003034393A1 (en) * | 2001-10-17 | 2003-04-24 | Sony Corporation | Display apparatus |
| CN1460883A (en) * | 2002-05-21 | 2003-12-10 | 索尼公司 | Display device |
| CN1404300A (en) * | 2002-09-17 | 2003-03-19 | 统宝光电股份有限公司 | No-overlapping sample pulse signal generator and pulse signal producing method |
| JP2004152482A (en) * | 2003-11-20 | 2004-05-27 | Sharp Corp | Shift register and image display device |
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