CN1404300A - No-overlapping sample pulse signal generator and pulse signal producing method - Google Patents
No-overlapping sample pulse signal generator and pulse signal producing method Download PDFInfo
- Publication number
- CN1404300A CN1404300A CN 02142690 CN02142690A CN1404300A CN 1404300 A CN1404300 A CN 1404300A CN 02142690 CN02142690 CN 02142690 CN 02142690 A CN02142690 A CN 02142690A CN 1404300 A CN1404300 A CN 1404300A
- Authority
- CN
- China
- Prior art keywords
- signal
- pulse
- defence
- signal generator
- pulse signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention relates to to a signal generator of free overlap sampling impulse can be used on the active matrix display, which includes an impulse scatterer, a defense, signal generator and a logical operation circuit. The method to generate the signal includes the following steps, the impulse scatterer to respond to a trigger of a starting impulse to generate several impulse signals in different phase and then to export them separately, the defense signal generated to provide a defence signal which switches between the first electric potential and the second electric potential, the logic operation circuit to receive these impulse signals to carry out an operation with the defense signal for exporting several numbers of sampling signal in sequence, the adjacent two sampling sections of sampling signals having a time interval for avoiding the overlap according to the time of the defense signal at the second electric potential.
Description
Technical field
The present invention relates to a kind of zero lap sample-pulse signal generator and production method, finger is applied to zero lap sample-pulse signal generator and the production method on the active matrix display device especially.
Background technology
See also Fig. 1, it is the circuit box schematic diagram of a Thin Film Transistor-LCD of using always at present, horizontal scanning circuit (horizontal scanning circuit) the 10th wherein, in order to produce in regular turn several sampling pulses (sampling pulse) Φ 1, Φ 2 ..., Φ n (not shown) come control switch circuit S1, S2 ... the conducting of Sn (not shown) or close, with image data signal SIG select to be sent to data wire Y1, Y2 ..., one of in the Yn (not shown), and then reach the purpose of upgrading image data.
See also Fig. 2 again, it is the waveform schematic diagram of above-mentioned sampling pulse (sampling pulse) Φ 1, Φ 2, in ideal, the rising edge of Φ 2 just produces after should finishing in the trailing edge variation of Φ 1, but because of the congenital problem on the manufacturing process, the trailing edge of the horizontal scanning circuit 10 normal Φ 1 of generation commonly used does not change as yet and finishes, and the rising edge of Φ 2 just produces.Thus, 2 of Φ 1, Φ will have one section overlapping region 20 to produce, and then cause image data signal SIG to be input to simultaneously on two data wire Y1, the Y2, cause data entry error and cause image distortion, and how to improve above-mentioned defective, for developing main purpose of the present invention.
Summary of the invention
The object of the present invention is to provide a kind of zero lap sample-pulse signal generator, solve in the typical thin films transistor liquid crystal display (TFT-LCD) image distortion because of signal overlap caused.
The present invention seeks to realize like this:
The invention discloses a kind of zero lap sample-pulse signal generator, be applied on the active matrix display device, this signal generator comprises: a pulse disperser, it responds the triggering of a starting impulse and produces several pulse signals in regular turn also respectively with corresponding output output, and has phase difference between the pulse signal of these outputs outputs; One defence signal generator produces a defence signal, and this defence signal switches between one first current potential and one second current potential; An and logical operation circuit, be electrically connected on this pulse disperser and this defence signal generator, this logical operation circuit carries out computing to these received pulse signals and this defence signal, and then export several sampled signals in regular turn, and be in time of this second current potential according to this defence signal, have a time interval between the sampling range of adjacent two sampled signals to avoid overlapping.
According to above-mentioned conception, zero lap sample-pulse signal generator of the present invention, wherein this pulse disperser is to be formed by connecting by several offset buffers.
According to above-mentioned conception, zero lap sample-pulse signal generator of the present invention, wherein these offset buffers clock signal of responding a pair of complementation is operated, and the time that this defence signal that this defence signal generator is produced is in this second current potential is to contain this variation that complementary clock signal is switched along the zone.
According to above-mentioned conception, zero lap sample-pulse signal generator of the present invention, wherein this logical operation circuit includes several NAND gates, and each NAND gate receives several pulse signals respectively and this defence signal carries out logical operation, and then exports corresponding sampled signal.
According to above-mentioned conception, zero lap sample-pulse signal generator of the present invention, its applied this active matrix display device is a Thin Film Transistor-LCD.
The present invention also discloses a kind of zero lap sample-pulse signal production method, be applied on the active matrix display device, this signal generating method comprise the following steps: to respond the triggering of a starting impulse and produce in regular turn the phase place inequality several pulse signals and respectively output; One defence signal is provided, and this defence signal switches between one first current potential and one second current potential; And receive these pulse signals and this defence signal and carry out a computing exporting several sampled signals in regular turn, and be in time of this second current potential according to this defence signal, have a time interval between the sampling range of adjacent two sampled signals to avoid overlapping.
According to above-mentioned conception, zero lap sample-pulse signal production method of the present invention, the clock signal that wherein more responds a pair of complementation produces these pulse signals, and the time that this defence signal is in this second current potential is contained this variation that complementary clock signal is switched along the zone.
According to above-mentioned conception, zero lap sample-pulse signal production method of the present invention, wherein this computing is a NAND gate computing.
According to above-mentioned conception, zero lap sample-pulse signal production method of the present invention, its applied this active matrix display device is a Thin Film Transistor-LCD.
Description of drawings
The present invention is able to more deep understanding by following accompanying drawing and detailed description:
Fig. 1 is the circuit box schematic diagram of a Thin Film Transistor-LCD of using always at present;
Fig. 2 is the waveform schematic diagram of above-mentioned sampling pulse Φ 1, Φ 2;
Fig. 3 is that the present invention develops out the preferred embodiment schematic diagram about zero lap sample-pulse signal generator;
Fig. 4 (a) (b) (c) is the waveform schematic diagram of preferred embodiment of the present invention.
Each included in the accompanying drawing of the present invention assembly lists as follows:
| Horizontal scanning circuit 10 | Switching circuit S1, S2 |
| Data wire Y1, Y2 | Overlapping region 20 |
| Pulse disperser 30 | Offset buffer 301,302,303 |
| NAND gate 311,312,313 | Logical operation circuit 31 |
| Defence signal generator 32 | Current potential is adjusted circuit 33 |
| Ring inverter 331 | Diverter switch 341,342,343 |
Embodiment
See also Fig. 3, it is the preferred embodiment schematic diagram of the present invention about zero lap sample-pulse signal generator, wherein pulse disperser 30 is by several offset buffers 301 in the present embodiment, 302,303 ... be formed by connecting Deng institute, it mainly is the triggering of response one starting impulse STH and the clock signal clk 1 of a pair of complementation, the control of CLK2 and produce several pulse signals of phase place inequality in regular turn, and respectively with corresponding output SR0, SR1, SR2 ... Deng being exported, its waveform correlation sees also the waveform schematic diagram shown in Fig. 4 (a), since the more than one variation that comprises clock signal clk 1 (or CLK2) when the areas of high potential of starting impulse STH along the time, the pulse signal SR0 that is generated, SR1, SR2 ... high potential will overlap phenomenon.And in the present embodiment, because the areas of high potential of starting impulse STH contains two variation edges of clock signal clk 1 (or CLK2), so adjacent pulse signal SR0, SR1, SR2 ... high potential will overlap phenomenon (shown in Fig. 4 (b)).Therefore, in the present embodiment, each NAND gate 311,312,313 in the logical operation circuit 31 ... carry out logical operation Deng receiving the adjacent pulse signal that high potential overlaps phenomenon respectively, and then export corresponding Ф 1, Φ 2, Φ 3 ... Deng sampled signal.
And the image distortion that causes data entry error to cause in order to ensure the sampled signal of being exported can not overlap provides a defence signal generator 32 to improve this defective.Defence signal generator 32 is connected to each NAND gate and sends a defence signal, shown in Fig. 4 (c), this defence signal switches between high potential and electronegative potential, but the time T d that this defence signal is in electronegative potential is contained this variation that complementary clock signal is switched along the zone, in then being in high potential At All Other Times.Thus, must have a time interval Td between the sampling range of adjacent two sampled signals and avoid overlapping, can effectively solve the defective of conventional means.And after these sampled signals adjust the effect of circuit 33 through a current potential again, form switch pulse (Switching pulse) S11, the S12 (or S21, S22 and S31, S32 etc.) of a pair of complementation, and then control the diverter switch of being finished with transmission gate (Transmission Gate) 341,342,343 ... Deng.And current potential adjustment circuit 33 is mainly the buffer that several inverters are connected to form, in order to sampled signal is adjusted to suitable potential to promote diverter switch.And be can make between anti-phase each other switch pulse (Switching pulse) S11, the S12 (or S21, S22 and S31, S32) synchronously, current potential is adjusted and is provided with a ring inverter 331 (ring inverter) in the circuit 33 and reaches this purpose.
In sum, the present invention develops out about zero lap sample-pulse signal generator and can solve in the typical thin films transistor liquid crystal display (TFT-LCD) because of the image distortion that signal overlap caused, and so this technology also can be widely used in the various active matrix display device.
Claims (9)
1, a kind of zero lap sample-pulse signal generator is applied to it is characterized in that on the active matrix display device that this signal generator comprises:
One pulse disperser, it responds the triggering of a starting impulse and produces several pulse signals in regular turn also respectively with corresponding output output, and has phase difference between the pulse signal of these outputs outputs;
One defence signal generator produces a defence signal, and this defence signal switches between one first current potential and one second current potential; And
One logical operation circuit, be electrically connected on this pulse disperser and this defence signal generator, this logical operation circuit carries out logical operation to these received pulse signals and this defence signal, and then export several sampled signals in regular turn, and be in time of this second current potential according to this defence signal, have a time interval between the sampling range of adjacent two sampled signals to avoid overlapping.
2, zero lap sample-pulse signal generator as claimed in claim 1 is characterized in that, this pulse disperser is formed by connecting by several offset buffers.
3, zero lap sample-pulse signal generator as claimed in claim 2, it is characterized in that, these offset buffers more respond the clock signal of a pair of complementation and operate, and the time that this defence signal that this defence signal generator is produced is in this second current potential is contained this variation that complementary clock signal is switched along the zone.
4, zero lap sample-pulse signal generator as claimed in claim 1, it is characterized in that, this logical operation circuit includes several NAND gates, and each NAND gate receives several pulse signals respectively and this defence signal carries out logical operation, and then exports corresponding sampled signal.
5, zero lap sample-pulse signal generator as claimed in claim 1 is characterized in that, its applied this active matrix display device is a Thin Film Transistor-LCD.
6, a kind of zero lap sample-pulse signal production method is applied to it is characterized in that on the active matrix display device that this signal generating method comprises the following steps:
Respond the triggering of a starting impulse and produce several pulse signals of phase place inequality and output respectively in regular turn;
One defence signal is provided, and this defence signal switches between one first current potential and one second current potential; And
Receive these pulse signals and this defence signal and carry out a computing exporting several sampled signals in regular turn, and be in time of this second current potential, have a time interval between the sampling range of adjacent two sampled signals to avoid overlapping according to this defence signal.
7, zero lap sample-pulse signal production method as claimed in claim 6, it is characterized in that, the clock signal that also responds a pair of complementation produces these pulse signals, and the time that this defence signal is in this second current potential is contained this variation that complementary clock signal is switched along the zone.
8, zero lap sample-pulse signal production method as claimed in claim 6 is characterized in that, this computing is a NAND gate computing.
9, zero lap sample-pulse signal production method as claimed in claim 6 is characterized in that, its applied this active matrix display device is a Thin Film Transistor-LCD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02142690 CN1404300A (en) | 2002-09-17 | 2002-09-17 | No-overlapping sample pulse signal generator and pulse signal producing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02142690 CN1404300A (en) | 2002-09-17 | 2002-09-17 | No-overlapping sample pulse signal generator and pulse signal producing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1404300A true CN1404300A (en) | 2003-03-19 |
Family
ID=4750437
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02142690 Pending CN1404300A (en) | 2002-09-17 | 2002-09-17 | No-overlapping sample pulse signal generator and pulse signal producing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1404300A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100377198C (en) * | 2004-08-03 | 2008-03-26 | 友达光电股份有限公司 | Single time pulse driving shift temporary storage and display driving circuit using it |
| CN101551980B (en) * | 2008-03-31 | 2012-12-26 | 统宝光电股份有限公司 | Image displaying system |
| CN103490751A (en) * | 2012-06-11 | 2014-01-01 | 晨星软件研发(深圳)有限公司 | Non-overlapping clock generator |
-
2002
- 2002-09-17 CN CN 02142690 patent/CN1404300A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100377198C (en) * | 2004-08-03 | 2008-03-26 | 友达光电股份有限公司 | Single time pulse driving shift temporary storage and display driving circuit using it |
| CN101551980B (en) * | 2008-03-31 | 2012-12-26 | 统宝光电股份有限公司 | Image displaying system |
| CN103490751A (en) * | 2012-06-11 | 2014-01-01 | 晨星软件研发(深圳)有限公司 | Non-overlapping clock generator |
| CN103490751B (en) * | 2012-06-11 | 2016-12-28 | 晨星软件研发(深圳)有限公司 | Non-overlapped clock pulse generator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11749158B2 (en) | Shift register unit, gate driving circuit, display device, and driving method | |
| CN103680386B (en) | For GOA circuit and the display device of flat pannel display | |
| US12051386B2 (en) | Shift register unit, signal generation unit circuit, driving method and display device | |
| KR102277072B1 (en) | GOA circuit driving architecture | |
| US20180190227A1 (en) | Shift register unit, gate driving circuit, and driving method thereof | |
| US7180351B2 (en) | Hybrid latch flip-flop | |
| US10522065B2 (en) | Transmitting electrode scan driving unit, driving circuit, driving method and array substrate | |
| CN105185338A (en) | CMOS GOA (Gate Driver on Array) circuit | |
| CN103985344A (en) | Shift register group and method for driving the same | |
| CN109166543B (en) | Data synchronization method, driving device and display device | |
| CN112102768B (en) | GOA circuit and display panel | |
| CN106710550A (en) | GOA cascade circuit used for large-size panel | |
| CN111508402A (en) | Grid driving circuit and touch display device | |
| CN206370275U (en) | Clock control circuit, gate driving circuit and display device | |
| CN105652534A (en) | Gate drive circuit and liquid crystal display thereof | |
| CN111326097A (en) | GOA circuit and display panel | |
| CN1404300A (en) | No-overlapping sample pulse signal generator and pulse signal producing method | |
| CN100538813C (en) | Circuit structure for dual resolution design reaches display panel and the electronic installation of using it | |
| CN102023441B (en) | Single-core interval transflective liquid crystal display and driving method thereof | |
| CN105161062A (en) | Liquid crystal display panel | |
| US5384496A (en) | Sample and hold circuit | |
| CN104347039A (en) | Shift register circuit, forming method thereof and display device comprising shift register circuit | |
| CN114170985B (en) | Display panel and electronic device | |
| CN106935181A (en) | Gate driving circuit | |
| CN1303661C (en) | Precharge apparatus in semiconductor memory device and precharge method using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |