CN101551980B - Image displaying system - Google Patents
Image displaying system Download PDFInfo
- Publication number
- CN101551980B CN101551980B CN 200810088801 CN200810088801A CN101551980B CN 101551980 B CN101551980 B CN 101551980B CN 200810088801 CN200810088801 CN 200810088801 CN 200810088801 A CN200810088801 A CN 200810088801A CN 101551980 B CN101551980 B CN 101551980B
- Authority
- CN
- China
- Prior art keywords
- clock signal
- signal
- horizontal
- horizontal clock
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention relates to an image displaying system with a display device. The display device comprises a time sequence control circuit, a display array, a horizontal driving circuit and a horizontal signal processing circuit. The time sequence control circuit is used for generating a plurality of time sequence signals. The display array comprises a plurality of display elements which are arrangedin a mode of matrix and vertically divided into N display blocks for sequentially updating. The horizontal driving circuit is coupled with the time sequence control circuit and utilizes the time sequ ence signals to generate a plurality of switching signals so as to sequentially starting the display blocks. The horizontal signal processing circuit is coupled with the time sequence control circuit,the horizontal driving circuit and the display array, and utilizes the time sequence signals and the switching signals to determine the starting time of each display block.
Description
Technical field
The present invention relates to a kind of image display system, particularly relate to the image display system that improves image quality look uneven (mura).
Background technology
Liquid crystal indicator (liquid crystal display; LCD), thereby become state-of-the-art a kind of display technology at present owing to have high resolving power, low power consumption, low-voltage demand and characteristic such as frivolous.Liquid crystal indicator is applied even more extensively in all kinds of portable information display devices, for example: personal digital assistant (personal digital assistant; PDA), portable computer and mobile phone etc.
Generally speaking, in order to reduce cost and to reduce the integrated circuit layout area, can required driving circuit be integrated in the liquid crystal indicator, for example usually: through low temperature polycrystalline silicon (low temperaturepolycrystalline silicon; LTPS) thin film transistor (TFT) (thin film transistors; TFTs), driving circuit is manufactured on the glass substrate of display pannel.This kind liquid crystal indicator comprises a vertical drive circuit and a horizontal drive circuit, and the former is in order to select a row display element in the array of being made up of display element, and the latter is then in order to write to video data in the display element of selected row.
Further, can also be a plurality of demonstration blocks (bank) with the array partition that display element is formed, and utilize many data line signal Refreshing Every demonstration in regular turn block, reduce required data line signal number by this.For reaching this purpose, known unlatching of going up through each demonstration block of switch control.When a specific demonstration block is opened, the then said data line signal of activation operation that this specific demonstration block is upgraded.When this specific demonstration block upgrades completion, could the next renewal operation that shows block of activation.Therefore, need correctly control the unlatching that each shows block, go to have influence on the data of the demonstration block that upgrades at present to avoid the next data of block that show, and then cause the problem of image quality look uneven (mura).
(array of display of BANK_1, BANK_2, BANK_3～BANK_N) is an example, and each shows that block controlled by switching signal S1, S2～SN respectively to be distinguished into a plurality of demonstration blocks.Please refer to Fig. 1, it show block BANK_1, the switching signal S1 of BANK_2, the S2 synoptic diagram that is coupled.In Fig. 1, switching signal S1 and S2 overlap each other (overlap).In this embodiment, when the pairing demonstration block of switching signal S1 BANK_1 upgrades operation, because the also corresponding renewal operation that shows block BANK_2 of activation of switching signal S2; Therefore, the data line signal that update displayed block BANK_1 is required is with the influence that receives the data line signal that switching signal S2 controlled.When the degree of coupling of switching signal S1 and S2 is high more, promptly Fig. 1 overlapping intersection point when high more, show the data line signal of block BANK_2, will produce very big influence to showing block BANK_1.
Fig. 2 shows under the switching signal degree of coupling condition of different, a display frame synoptic diagram that is produced.As stated, opening the switching signal that each shows block, can be other signal of collocation usually, for example horizontal clock signal ... wait and produce.Because element do not match, temperature or other factors, when switching signal maybe should collocation signal etc. one of them produce when postponing, or when the delay of signals degree varies caused to each other, the degree of coupling of the switching signal that is produced was also inequality.Thus, with making this display frame produce demonstration block problem (bank problem), have a strong impact on the image display quality, that is cause the problem of above-mentioned mura like Fig. 2.
Summary of the invention
In view of this, the present invention provides a kind of image display system, when the update displayed block, can avoid opening between the switching signal that shows block the demonstration block problem that causes coupled to each other effectively.
This image display system has a display device, and this display device comprises: a sequential control circuit, an array of display, a horizontal drive circuit and a horizontal signal processing circuit.This sequential control circuit is in order to produce a plurality of clock signals.This array of display comprises a plurality of display elements, arranges with matrix-style.Above-mentioned display element is N by vertical division in regular turn and shows block, in order to upgrade in regular turn.This horizontal drive circuit couples this sequential control circuit, utilizes said clock signal to produce a plurality of switching signals, in order to open said demonstration block in regular turn.This horizontal signal processing circuit couples this sequential control circuit, this horizontal drive circuit and this array of display, utilizes said clock signal and said switching signal, shows the opening time of block in order to determine each.
Based on above-mentioned purpose, the present invention also provides a kind of image display system, has a display device, and this display device comprises: a sequential control circuit, an array of display, clock signal adjustment circuit and a horizontal drive circuit.This sequential control circuit is in order to produce a plurality of clock signals.This array of display comprises a plurality of display elements, arrange with matrix-style, and said display element is N demonstration block by vertical division, in order to upgrade in regular turn.This clock signal adjustment circuit couples this sequential control circuit, in order to adjust the work period of said clock signal.This horizontal drive circuit couples this clock signal adjustment circuit, utilizes adjusted said clock signal to produce a plurality of switching signals, to open said demonstration block in regular turn.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, hereinafter is special lifts embodiment, and is described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 shows in the known technology, shows the switching signal coupling synoptic diagram of block;
During Fig. 2 shows that known technology switches, under the signal degree of coupling different situations, a display frame synoptic diagram that is produced;
Fig. 3 shows the image display system calcspar according to the embodiment of the invention;
One sequential chart of the horizontal drive circuit of Fig. 4 displayed map 1;
Fig. 5 shows the horizontal signal processing circuit calcspar according to the embodiment of the invention;
Fig. 6 shows the image display system calcspar according to the embodiment of the invention;
Fig. 7 shows the horizontal signal processing circuit calcspar according to the embodiment of the invention; And
Fig. 8 shows the image display system synoptic diagram according to the embodiment of the invention.
The reference numeral explanation
100,600,810～display device;
102,602～sequential control circuit;
104,604～array of display;
106,606～horizontal drive circuit;
108,508～horizontal signal processing circuit;
110,610～vertical drive circuit;
120,620～clock signal;
S1, S2,122,624～switching signal;
126～vertical scanning signal;
510～the first logical circuits;
520～the second logical circuits;
608,708～clock signal adjustment circuit;
622～update signal;
710～the first NAND gate circuits;
712～the second NAND gate circuits;
720,730,724,734～phase inverter;
722,732～Sheffer stroke gate;
800～image display system; And
820～electric supply installation.
Embodiment
Please refer to Fig. 3, it shows the image display system calcspar according to the embodiment of the invention.This image display system has a display device 100, and this display device 100 comprises: a sequential control circuit 102, an array of display 104, a horizontal drive circuit 106 and a horizontal signal processing circuit 108.This sequential control circuit 102 is in order to produce a plurality of clock signals 120.This array of display 104 comprises a plurality of display elements, for example: liquid crystal display cells, said display element is arranged (not shown) with matrix-style, and wherein, said display element is N by vertical division and shows block (bank), in order to upgrade in regular turn.In one embodiment; If this display device 100 has 24 data line signals in order to upgrade; Then when each row comprises 960 display elements; Just can the display frame vertical division be 40 and show blocks (being that N is 40), BANK_1 as shown in Figure 3, BANK_2, BANK_3 ..., BANK_N etc. shows block, and each shows that block includes the display element of similar number.Further, this horizontal drive circuit 106 couples this sequential control circuit 102, utilizes said clock signal 120 to produce a plurality of switching signals 122, in order to open said demonstration block in regular turn and to upgrade said display element.This horizontal signal processing circuit 108 couples this sequential control circuit 102, this horizontal drive circuit 106 and this array of display 104; Utilize said clock signal 120 and said switching signal 122; In order to determine each to show the opening time of block, will further combine Fig. 5 to be specified in down.
In one embodiment, this display device 100 comprises a vertical drive circuit 110 further, comprises a plurality of vertical scanning signals 126, puts execution vertical scanning in order to this demonstration is adorned 104, to open said display element.
Please refer to Fig. 4, a sequential chart of this horizontal drive circuit 106 of its displayed map 3.In one embodiment, the above-mentioned clock signal 120 of these sequential control circuit 102 generations comprises a horizontal enabling signal STH (start pulse horizontal), a horizontal clock signal C KH (clock horizontal) and a complementary horizontal clock signal XCKH.As shown in Figure 4, when this horizontal enabling signal STH was high-voltage level, at first this first driving circuit 106 of activation produced a plurality of first control signal HSR_1～HSR_N.For example, when this horizontal enabling signal STH is a high-voltage level, and this horizontal clock signal C KH is when being triggered high-voltage level, and this first driving circuit 106 produces signal HSR_1.Behind a horizontal clock signal period, anticipate promptly, when this horizontal clock signal C KH was triggered high-voltage level once more, this first driving circuit 106 produced signal HSR_3, by that analogy.Likewise, when this horizontal enabling signal STH is a high-voltage level, and when should the horizontal clock signal XCKH of complementation being triggered high-voltage level, this first driving circuit 106 produces signal HSR_2.Behind a horizontal clock signal period of complementation, anticipate promptly, when the horizontal clock signal XCKH of this complementation was triggered high-voltage level once more, this first driving circuit 106 produced next control signal HSR_4 (not icon) in regular turn, by that analogy.
Further; This horizontal drive circuit 106 utilize these horizontal clock signal C KH, the horizontal clock signal XCKH of this complementation and said first control signal (HSR_1, HSR_2, HSR_3 ..., HSR_N); Further produce said switching signal 122; Promptly in order to open the switching signal that each shows block, 122-1 as shown in Figure 4,122-2,122-3... etc.In this embodiment, pairing demonstration blocks such as switching signal 122-1,122-2,122-3... for example are demonstration block BANK_1 shown in Figure 3, BANK_2, BANK_3... etc.
Please refer to Fig. 5, it shows a horizontal signal processing circuit 508 calcspars according to the embodiment of the invention.In this embodiment, this horizontal signal processing circuit 508 comprises one first logical circuit 510 and a plurality of second logical circuit 520.This first logical circuit 510 comprises the phase inverter of two serial connections, receives the switching signal 122-1 that shows block (BANK_1 as shown in Figure 3) corresponding to first, in order to producing one first corrected signal 124-1, with determine this first show opening time of block.
Further, each second logical circuit 520 comprises a Sheffer stroke gate and a phase inverter, in order to receive corresponding to second to N demonstration block (said switching signal 122-2～122-N of BANK_2 as shown in Figure 3～BANK_N).Simultaneously; Each second logical circuit 520 also receives this horizontal clock signal C KH or should the horizontal clock signal XCKH of complementation; In order to produce a plurality of second corrected signal 124-2～124-N, to open second (BANK_2 as shown in Figure 3) in regular turn to N demonstration block (BANK_N as shown in Figure 3).Pass through present embodiment; This horizontal signal processing circuit 508 can correctly produce the switching signal 124-1～124-N of non-overlapping copies; Effectively improve the phenomenon of switching signal coupling, or reduce the degree of coupling of said switching signal 124-1～124-N, and then promote the quality that image shows.
Please refer to Fig. 6, it shows the image display system calcspar according to the embodiment of the invention.This image display system has a display device 600, and this display device 600 comprises: a sequential control circuit 602, an array of display 604, a clock signal adjustment circuit 608, a horizontal drive circuit 606 and a vertical drive circuit 610.In Fig. 6, the functional similarity of element shown in this sequential control circuit 602, this array of display 604, this horizontal drive circuit 606 and this vertical drive circuit 610 and Fig. 1 embodiment is in this its details that repeats no more.Different with Fig. 3 embodiment is after this sequential control circuit 602 produces a plurality of clock signals 620, comprising: a horizontal clock signal C KH and a complementary horizontal clock signal XCKH just are sent to this clock signal adjustment circuit 608 with above-mentioned clock signal.The work period of the said clock signal 620 of this clock signal adjustment circuit 608 adjustment,, comprising to produce one group of update signal 622: one more new height clock signal C KH ' and upgrade complementary horizontal clock signal XCKH '.Then, this horizontal drive circuit 606 can further produce the switching signal 624 of non-overlapping copies, to open said demonstration block in regular turn.
Please refer to Fig. 7, it shows clock signal adjustment circuit 708 calcspars according to the embodiment of the invention.In this embodiment, this clock signal adjustment circuit 708 comprises one first NAND gate circuit 710 and one second NAND gate circuit 712, in order to adjust the work period (duty cycle) of this horizontal clock signal C KH and the horizontal clock signal XCKH of this complementation.
As shown in Figure 7, this first NAND gate circuit 710 comprises: first phase inverter 720, one second Sheffer stroke gate 722 and one the 3rd phase inverter 724 of odd number serial connection.First phase inverter 720 of this odd number serial connection receives this horizontal clock signal C KH, with the inversion signal 740 that produces this horizontal clock signal.This second Sheffer stroke gate 722 couples first phase inverter 720 of this odd number serial connection; One first termination of this second Sheffer stroke gate 722 is received above-mentioned inversion signal 740; And one second termination of this second Sheffer stroke gate 722 is received should the horizontal clock signal XCKH of complementation, in order to produce one first output signal 742.The 3rd phase inverter 724 couples this second Sheffer stroke gate 722, receives this first output signal 742, to produce a new height clock signal C KH ' more.
Likewise, this second NAND gate circuit 712 comprises the 4th phase inverter 730, one the 5th Sheffer stroke gate 732 and a hex inverter 734 of odd number serial connection.The 4th phase inverter 730 of this odd number serial connection receives should the horizontal clock signal XCKH of complementation, with the inversion signal 744 that produces this horizontal clock signal.The 5th Sheffer stroke gate 732 couples the 4th phase inverter 730 of this odd number serial connection; One first termination of the 5th Sheffer stroke gate 732 is received above-mentioned inversion signal 744; And one second termination of the 5th Sheffer stroke gate 732 receive should the horizontal clock signal C KH of complementation, in order to produce one second output signal 746.This hex inverter 734 couples the 5th Sheffer stroke gate 732, receives this second output signal 746, upgrades complementary horizontal clock signal XCKH ' to produce one.
In this embodiment; This first NAND gate circuit 710; Time delay of the rising edge through increasing this horizontal clock signal C KH, and reduce time delay of the falling edge of this horizontal clock signal C KH is to produce the work period less than this new height clock signal C KH ' more of 50%.Likewise; This second NAND gate circuit 712 also passes through the time delay of the rising edge of the horizontal clock signal XCKH of this complementation of increase; And reduce time delay of the falling edge of the horizontal clock signal of this complementation, with produce the work period less than 50% this upgrade complementary horizontal clock signal XCKH '.Thus, utilize adjusted clock signal C KH ' and XCKH ', the switching signal 624 that this horizontal drive circuit 606 is produced will not have overlapping problem.
Please refer to Fig. 8, it shows an image display system 800 synoptic diagram according to the embodiment of the invention.In the present embodiment, this image display system 800 is embodied as an electronic installation.This electronic installation comprises: a display device 810 and an electric supply installation 820.For example, this display device 810 can be a liquid crystal indicator, and this electric supply installation 820 couples this display device 810, in order to supply power to this display device 810, in order to produce image.For example, this electronic installation can be escope, a flat computer or a mobile phone on a digital camera, a PDA(Personal Digital Assistant), a monitor, a mobile computer, the car.
Though the present invention discloses as above with preferred embodiment; But it is not in order to qualification the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; When can doing a little change and modification, so protection scope of the present invention should be as the criterion with claim of the present invention.
Claims (4)
1. an image display system has a display device, comprising:
One sequential control circuit is in order to produce a plurality of clock signals;
One array of display comprises a plurality of display elements, arranges with matrix-style, and said display element is N by vertical division and shows block, in order to upgrade in regular turn;
One clock signal adjustment circuit couples this sequential control circuit, in order to adjust the work period of said clock signal; And
One horizontal drive circuit couples this clock signal adjustment circuit, utilizes adjusted said clock signal to produce a plurality of switching signals, to open said demonstration block in regular turn;
Wherein, said switching signal is non-overlapped signal,
Wherein, said clock signal comprises: a horizontal enabling signal, a horizontal clock signal and a complementary horizontal clock signal;
Wherein, this clock signal adjustment circuit comprises one first NAND gate circuit, and in order to adjust the work period of this horizontal clock signal, this first NAND gate circuit comprises:
First phase inverter of odd number serial connection receives this horizontal clock signal, to produce the inversion signal of this horizontal clock signal;
One second Sheffer stroke gate; Couple first phase inverter of this odd number serial connection; One first termination of this second Sheffer stroke gate is received the inversion signal of this horizontal clock signal, and one second termination of this second Sheffer stroke gate is received should the horizontal clock signal of complementation, to produce one first output signal; And
One the 3rd phase inverter couples this second Sheffer stroke gate, receives this first output signal, to produce a new height clock signal more;
Wherein, this clock signal adjustment circuit more comprises one second NAND gate circuit, and in order to adjust the work period of the horizontal clock signal of this complementation, this second NAND gate circuit comprises:
The 4th phase inverter of odd number serial connection, reception should the horizontal clock signals of complementation, to produce the inversion signal of the horizontal clock signal of this complementation;
One the 5th Sheffer stroke gate; Couple the 4th phase inverter of this odd number serial connection; One first termination of the 5th Sheffer stroke gate is received the inversion signal of the horizontal clock signal of this complementation, and one second termination of the 5th Sheffer stroke gate is received this horizontal clock signal, to produce one second output signal; And
One hex inverter couples the 5th Sheffer stroke gate, receives this second output signal, upgrades complementary horizontal clock signal to produce one,
Wherein, This first NAND gate circuit and this second NAND gate circuit; Increase the time delay of the rising edge of this horizontal clock signal and the horizontal clock signal of this complementation respectively, and the time delay that reduces the falling edge of this horizontal clock signal and the horizontal clock signal of this complementation respectively.
2. image display system as claimed in claim 1 also comprises:
One vertical drive circuit couples this array of display, and this vertical drive circuit comprises a plurality of vertical scanning signals, in order to this array of display is carried out vertical scanning, to open said display element.
3. image display system as claimed in claim 1, wherein above-mentioned image display system is an electronic installation, also comprises an electric supply installation, couples this display device, in order to supply power to this display device.
4. image display system as claimed in claim 3, wherein, this electronic installation is escope, a flat computer or a mobile phone on a digital camera, a personal digital assistant, a monitor, a mobile computer, the car.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810088801 CN101551980B (en) | 2008-03-31 | 2008-03-31 | Image displaying system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810088801 CN101551980B (en) | 2008-03-31 | 2008-03-31 | Image displaying system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101551980A CN101551980A (en) | 2009-10-07 |
| CN101551980B true CN101551980B (en) | 2012-12-26 |
Family
ID=41156191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810088801 Active CN101551980B (en) | 2008-03-31 | 2008-03-31 | Image displaying system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101551980B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6130749B2 (en) * | 2013-07-12 | 2017-05-17 | アズビル株式会社 | Control system and data collection display method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883609A (en) * | 1994-10-27 | 1999-03-16 | Nec Corporation | Active matrix type liquid crystal display with multi-media oriented drivers and driving method for same |
| US6512545B1 (en) * | 1996-12-20 | 2003-01-28 | Olympus Optical Co., Ltd. | Solid-state image pickup apparatus for reading pixel signals out at a high frame rate |
| CN1404300A (en) * | 2002-09-17 | 2003-03-19 | 统宝光电股份有限公司 | No-overlapping sample pulse signal generator and pulse signal producing method |
| CN1486482A (en) * | 2001-10-17 | 2004-03-31 | ���ṫ˾ | Display apparatus |
| CN1503213A (en) * | 2002-11-25 | 2004-06-09 | ���µ�����ҵ��ʽ���� | Horizontal shift clock pulse selection circuit use of driving color LCD screen |
| US7053943B2 (en) * | 2000-11-21 | 2006-05-30 | Minolta Co., Ltd. | Scanning circuit, and imaging apparatus having the same |
| CN1797530A (en) * | 2004-12-29 | 2006-07-05 | 苏柏宪 | LCD module and control method |
-
2008
- 2008-03-31 CN CN 200810088801 patent/CN101551980B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883609A (en) * | 1994-10-27 | 1999-03-16 | Nec Corporation | Active matrix type liquid crystal display with multi-media oriented drivers and driving method for same |
| US6512545B1 (en) * | 1996-12-20 | 2003-01-28 | Olympus Optical Co., Ltd. | Solid-state image pickup apparatus for reading pixel signals out at a high frame rate |
| US7053943B2 (en) * | 2000-11-21 | 2006-05-30 | Minolta Co., Ltd. | Scanning circuit, and imaging apparatus having the same |
| CN1486482A (en) * | 2001-10-17 | 2004-03-31 | ���ṫ˾ | Display apparatus |
| CN1404300A (en) * | 2002-09-17 | 2003-03-19 | 统宝光电股份有限公司 | No-overlapping sample pulse signal generator and pulse signal producing method |
| CN1503213A (en) * | 2002-11-25 | 2004-06-09 | ���µ�����ҵ��ʽ���� | Horizontal shift clock pulse selection circuit use of driving color LCD screen |
| CN1797530A (en) * | 2004-12-29 | 2006-07-05 | 苏柏宪 | LCD module and control method |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平5－313608A 1993.11.26 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101551980A (en) | 2009-10-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9972270B1 (en) | Display device, TFT substrate and GOA driving circuit | |
| US20200020291A1 (en) | Shift Register Circuit, Method for Driving the Same, Gate Drive Circuit, and Display Panel | |
| US9495930B2 (en) | Shift register, method for driving the same, and display device | |
| US8643584B2 (en) | Gate drive circuit and display apparatus having the same | |
| CN101335050B (en) | Shift register and liquid crystal display using the same | |
| US10152939B2 (en) | Gate driving circuit, method for driving the same, and display device | |
| CN102270509B (en) | Shift register circuit | |
| EP2750127A2 (en) | Gate driving circuit, display module and display device | |
| US20160266700A1 (en) | Gate driving circuit, array substrate, display device and driving method | |
| KR20170020591A (en) | Display device | |
| CN102654968A (en) | Shift register, grid driver and display device | |
| US20120169679A1 (en) | Liquid crystal display device | |
| CN107689221B (en) | GOA circuit | |
| CN105807518A (en) | Liquid crystal display panel | |
| CN102956186A (en) | Shift register, grid drive circuit and liquid crystal display | |
| CN109300445B (en) | Array substrate row driving circuit and display device | |
| WO2020134947A1 (en) | Display module and display apparatus | |
| US10818212B2 (en) | Display substrate and method for driving the same, display panel and display apparatus | |
| CN105047155A (en) | Liquid crystal display apparatus and GOA scanning circuit | |
| US20170256219A1 (en) | GOA Circuit and Method for Driving the Same and LCD | |
| US11600242B2 (en) | Single-stage gate driving circuit with multiple outputs and gate driving device | |
| CN106920498A (en) | GIP circuits and its driving method and panel display apparatus | |
| CN109389957A (en) | Array substrate row driving circuit and display device | |
| US20100033418A1 (en) | Liquid crystal display | |
| CN101521043B (en) | Shift buffer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |