CN106710550A - GOA cascade circuit used for large-size panel - Google Patents
GOA cascade circuit used for large-size panel Download PDFInfo
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- CN106710550A CN106710550A CN201611260240.0A CN201611260240A CN106710550A CN 106710550 A CN106710550 A CN 106710550A CN 201611260240 A CN201611260240 A CN 201611260240A CN 106710550 A CN106710550 A CN 106710550A
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The invention relates to a GOA cascade circuit used for a large-size panel. The GOA cascade circuit mainly solves the technical problem of horizontal bright and dark lines appeared in a large-size display panel due to great difference between output signals of GOA units in a GOA cascade circuit in the prior art. The GOA cascade circuit adopts a technical scheme of carrying out differential control on an STV pulse signal of a pull-up driving module of a previous a stage GOA unit in an N-stage GOA cascade circuit having 2a CK clock signals, effectively solves the problem, and can be applied to the production of the large-size panel.
Description
Technical field
The present invention relates to technical field of display panel, a kind of GOA cascade circuits for large size panel are related specifically to.
Background technology
Gate driving circuit and method Gate Driver On Array, abbreviation GOA, that is, using existing film crystal
Pipe liquid crystal display Array processing procedures on Array substrates, realize to Gate line by line Gate row scanning drive signal circuit productions
One technology of the type of drive of scanning.
Existing GOA circuits, generally include multiple GOA units of cascade, and Primary plateaus are driven per one-level GOA unit correspondence
Scan line.The primary structure of GOA unit includes pull-up module, pulling drive module, lower transmission module, drop-down module and drop-down maintenance
Module, and responsible current potential lifting bootstrap capacitor.Pull-up circuit is mainly responsible for for clock signal CK being output as signal；On
Drive circuit is drawn to be responsible for the opening time of pullup drive circuit, the biography signal down that general connection earlier stages GOA circuits are passed over；
Pull-down circuit is responsible for scanning drive signal G (N) in the very first time down for low potential, that is, close G (N)；Drop-down holding circuit
Then it is responsible for maintaining the G (N) of G (N) output signals and pull-up circuit in off position, i.e. negative potential, includes two drop-down dimensions
Hold module alternating action；Bootstrap capacitor is then responsible for the secondary lifting of Q (N) points, is so conducive to the G (N) of pull-up circuit to export.It is existing
In some GOA circuits, whole GOA unit is divided into a groups, CK1 correspondence CKa+1, CK2 correspondence CKa+2, CK3 correspondence CKa+3 ... from
And the load of whole panel is divided into a parts, go to reduce every group of load on the GOA grades of road that conducts electricity.When panel is under critical conditions,
In the presence of the output signal of a group GOA units can be made to make a difference, cause display panel that bright concealed wire of level etc. occurs in high temperature no
It is good, so as to influence the technical problem of the reliability of whole panel.Therefore it provides a kind of output signal difference of a groups GOA unit subtracts
Small circuit is just necessary.
The content of the invention
The technical problem to be solved in the present invention is that panel present in prior art is in when under critical conditions, and GOA is mono- for a groups
The output signal of unit makes a difference, and the technical problem of the bright concealed wire of level occurs in panel.The present invention provides a kind of a groups GOA unit
The GOA drive circuits that output signal difference is reduced.
In order to solve the above technical problems, the present invention is adopted the following technical scheme that：
A kind of GOA cascade circuits for large size panel, including the multiple GOA units for cascading, N grades of GOA unit pair
N grades of horizontal scanning line G (N) should be driven, the N grades of GOA unit includes 2a CK clock signal；
Pull-up module for CK clock signals to be output as signal, the pull-up module connects N grades of level and sweeps
Retouch line G (N) and CK clock signals；
The lower transmission module being connected with CK clock signals, signal ST (N) is passed down for exporting；
By N grades of horizontal scanning line G (N) down for the drop-down module of low potential, N grades of horizontal scanning line G (N) is connected,
N+a grades of horizontal scanning line G (N+a) and VSS DC low-voltages；
N grades of horizontal scanning line G (N) signal is maintained the drop-down maintenance module of negative potential, the drop-down maintenance module
Connection Q (N) point, N grades of horizontal scanning line G (N) and VSS DC low-voltages；
The drop-down maintenance module includes alternating action, the first drop-down holding circuit of mirror image connection and the second drop-down maintenance
Circuit；First the first low-frequency clock signal of drop-down maintenance module connection LC1, the second drop-down maintenance module connection second
Low-frequency clock signal LC2；
And for the bootstrap capacitor Cb of lifting current potential, the drop-down maintenance module, Q (N) are connected described in bootstrap capacitor Cb
Point and N grades of horizontal scanning line G (N)；
I-stage GOA unit in the N grades of GOA unit in preceding a grades of GOA unit circuit also includes that control pull-up module is opened
The pulling drive module of time is opened, the pulling drive module connects STVi pulse signals and Q (N) point；
Wherein i=1,2,3 ... a, a are the natural number less than N/2, and N is natural number.
Further, in the i-stage GOA unit, STVi pulse signals are drained and the seven or eight by the seven or seven transistor T77
Transistor T78 source electrodes are exported jointly, and the seven or the seven transistor gate T77 connects cki clock signals, source electrode connection VSS direct currents
Low pressure；The seven or eight transistor T78 being connected with the seven or seven transistor T77, the seven or eight transistor T78 grids, drain electrode are all connected with STV
Pulse signal.
Further, the first low-frequency clock signal LC1 and second low-frequency clock signal (LC2) are opposite in phase
Low frequency signal source.
Further, the described first drop-down maintenance module connects the pulling drive module, including：5th two-transistor
T52；The May 4th transistor T54 being connected with the grid of the 5th two-transistor T52；It is connected with the 5th two-transistor T52 drain electrodes
May Day transistor T51 source electrodes and the five or three transistor gate T53, May Day transistor T51 grids, drain electrode and the five or three
The drain electrode of transistor T53 is connected in the first low-frequency clock signal LC1；The May 4th being connected with the 5th two-transistor T52 grids is brilliant
The grid of body pipe T54；The three or two crystal being connected simultaneously with the five or three transistor T53 source electrodes and the May 4th transistor T54 drain electrodes
Pipe T32 grids；The 4th two-transistor T42 grids being connected with the 3rd two-transistor T32 grids；The 4th two-transistor T42
Drain electrode N grades of signal Q (N) point of connection.
Further, the drain electrode of the five or the three transistor T53 is changed to connection CK signals all the time.
Further, the described second drop-down maintenance module connects the pulling drive module, including：6th two-transistor
T62；The six or four transistor T64 being connected with the grid of the 6th two-transistor T62；It is connected with the 6th two-transistor T62 drain electrodes
6th 1 transistor T61 source electrodes and the six or three transistor T63 grids, the 6th 1 transistor gate T61, drain electrode and the six or three
The drain electrode of transistor T63 is connected in the second low-frequency clock signal LC2；The six or four be connected with the 6th two-transistor T62 grids is brilliant
The grid of body pipe T64；The three or three crystal being connected simultaneously with the six or three transistor T63 source electrodes and the six or four transistor T64 drain electrodes
Pipe T33 grids；The four or three transistor T43 grids being connected with the three or three transistor T33 grids；Four or the three transistor T43
Drain electrode N grades of signal Q (N) point of connection.
Further, the drain electrode of the six or the three transistor T63 is changed to connect XCK clock signals.
Further, the drop-down module includes the 4th 1 transistor T41 and the 3rd 1 transistor T31, the described 4th 1
The grid of transistor T41 and the 3rd 1 transistor T31 connects N+a grades of horizontal scanning line G (N+a), the common connection of drain electrode jointly
VSS DC low-voltages.
Further, the grid of the 4th 1 transistor T41 and the 3rd 1 transistor T31 N+a+1 grades of connection jointly
Horizontal scanning line G (N+a+1).
Further, the a=4.
The present invention is driven in the N grades of GOA cascade circuit that ck clock signals are 2a by the pull-up to preceding a grades of GOA unit
Dynamic input STV1, STV2, STV3 ... STVa pulse signals carry out differentiation control, instead of preceding a grades of GOA unit in the prior art
STV1, STV2, STV3 ... STVa pulse signals are same to be set to STV pulse signals.This technical scheme can reduce a groups
The output signal of GOA unit makes a difference.
Therefore, the beneficial effects of the invention are as follows：
Effect one：Reduce the output difference of GOA unit；
Effect two：Reduce panel and the troublesome frequencies of the bright concealed wire of level occur；
Effect three：Improve the reliability using the display panel of GOA cascade circuits.
Brief description of the drawings
Fig. 1 is preceding a grades of GOA unit module diagram in the prior art；
Fig. 2 is preceding a grades of GOA unit module diagram in the present invention；
Fig. 3 is preceding a=4 grades of GOA unit circuit diagram in the present invention；
Fig. 4 be in the prior art in preceding a=4 grades of GOA unit circuit diagram；
Fig. 5 is STV1/2/3/4 pulse signal generative circuit schematic diagrames in preceding a=4 grades of GOA unit in the present invention；
Fig. 6 is a=4,2a CK grades of GOA circuit signal schematic diagram in the prior art；
Fig. 7 is a=4 in the present invention, 2a CK grades of GOA circuit signal schematic diagram；
Fig. 8 is preceding a grades of signal output waveform figure in the prior art；
Fig. 9 is preceding a grades of signal output waveform figure in the present invention.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to embodiments, to the present invention
It is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not used to
Limit the present invention.
Fig. 1 is preceding a grades of GOA unit module diagram in the prior art, and the Fig. 2 that compares is preceding a grades of GOA unit in the present invention
Module diagram；Fig. 3 the present invention in preceding a=4 grades of GOA unit circuit diagram, corresponding Fig. 4 be in the prior art in preceding a=4
Level GOA unit circuit diagram；Fig. 5 is STV (Vertical Start Pluse, frame in preceding a=4 grades of GOA unit in the present invention
Unbalanced pulse signal) 1/2/3/4 pulse signal generative circuit schematic diagram；Fig. 6 a=4 in the prior art, 2a CK grades of GOA circuits letter
Number schematic diagram；A=4,2a CK grades of GOA circuit signal schematic diagram in Fig. 7 present invention；Fig. 8 preceding a grades of output signal in the prior art
Oscillogram；Preceding a grades of signal output waveform figure in Fig. 9 present invention.
Embodiment 1：
Comparison diagram 1, as shown in Fig. 2 the present embodiment provides a kind of GOA cascade circuits for large size panel, including level
Multiple GOA units of connection, N grades of GOA unit correspondence drives N grades of horizontal scanning line G (N), has 8 in the N grades of GOA unit
CK clock signals, i-stage GOA unit in preceding 4 grades of GOA unit circuits, i=1,2,3.4, including：CK clock signals are output as
The pull-up module of signal, the pull-up module connects N grades of horizontal scanning line (G (N)) and CK clock signals；Pulling drive
The pulling drive module of module opening time, the pulling drive module connects STVi pulse signals and Q (N) point；With CKi clocks
The lower transmission module of signal connection, signal ST (N) is passed down for exporting；By N grades of horizontal scanning line (G (N)) down for low potential
Drop-down module, connect N grades of horizontal scanning line G (N), N+i grades of horizontal scanning line G (N+i) and VSS DC low-voltages；By N
Level horizontal scanning line G (N) signal maintains the drop-down maintenance module of negative potential, described drop-down maintenance module connection Q (N) point, N
Level horizontal scanning line G (N) and VSS DC low-voltages；It is first drop-down that the drop-down maintenance module includes that alternating action, mirror image are connected
Holding circuit and the second drop-down holding circuit；The first low-frequency clock signal of first drop-down maintenance module connection LC1, described the
Two drop-down maintenance modules connect the second low-frequency clock signal LC2；And the bootstrap capacitor Cb of current potential lifting, connect drop-down maintenance mould
Block, Q (N) points and N grades of horizontal scanning line G (N).
As described in Figure 5, in i-stage GOA unit, STVi pulse signals are drained by the seven or seven transistor T77 and the seven or eight is brilliant
Body pipe T78 source electrodes are exported jointly, and the seven or the seven transistor gate T77 connects cki clock signals, and source electrode connection VSS direct currents are low
Pressure；The seven or eight transistor T78 being connected with the seven or seven transistor T77, the seven or eight transistor T78 grids, drain electrode are all connected with STV arteries and veins
Rush signal.
As described in Fig. 3 and 4：First drop-down maintenance module includes：5th two-transistor T52；With the 5th two-transistor T52's
The May 4th transistor T54 of grid connection；With the 5th two-transistor T52 May Day transistor T51 source electrodes for being connected of drain electrode and the
Five or three transistor gate T53, May Day transistor T51 grids, drain electrode and the drain electrode of the five or three transistor T53 are connected in the
One low-frequency clock signal LC1；The grid of the May 4th transistor T54 being connected with the 5th two-transistor T52 grids；It is brilliant with the five or three
Body pipe T53 source electrodes and the 3rd two-transistor T32 grids of the May 4th transistor T54 drain electrodes connection simultaneously；With the 3rd two-transistor
4th two-transistor T42 grids of T32 grids connection；The 4th two-transistor T42 drain electrodes N grades of signal Q (N) of connection
Point.First low-frequency clock signal LC1 and the low frequency signal source that the second low-frequency clock signal LC2 is opposite in phase.Under second
Drawing maintenance module includes：6th two-transistor T62；The six or four transistor T64 being connected with the grid of the 6th two-transistor T62；
The 6th 1 transistor T61 source electrodes and the six or three transistor T63 grids being connected with the 6th two-transistor T62 drain electrodes, the described 6th
One transistor gate T61, drain electrode and the drain electrode of the six or three transistor T63 are connected in the second low-frequency clock signal LC2；With the six or two
The grid of the six or four transistor T64 of transistor T62 grids connection；With the six or three transistor T63 source electrodes and the six or four transistor
Three or three transistor T33 grids of T64 drain electrodes connection simultaneously；The four or three transistor being connected with the three or three transistor T33 grids
T43 grids；Four or three transistor T43 drain electrodes N grades of signal Q (N) point of connection.
As shown in figure 4, drop-down module includes the 4th 1 transistor T41 and the 3rd 1 transistor T31, the 4th 1 crystal
The grid of pipe T41 and the 3rd 1 transistor T31 connects N+a grades of horizontal scanning line (G (N+a)), the common connection VSS of drain electrode jointly
DC low-voltage.
Such as Fig. 6, Fig. 7 is respectively to prior art and the present embodiment input STV signals and 8 CK clock signals；
During opening time T=100, the Fig. 9 of comparison diagram 8 obtains following result：
The output signal difference of the present embodiment GOA unit is significantly less than the defeated of the GOA unit of prior art in Fig. 8 in Fig. 9
Go out signal difference, therefore the present embodiment can solve the problem that the problem of the bright concealed wire of level occurs in panel.
Embodiment 2
The present embodiment further illustrates the described first drop-down maintenance module and connects the first low frequency on the basis of embodiment 1
Other selections outside clock signal LC1:
As described in Fig. 2 and Fig. 4, the first drop-down maintenance module includes：5th two-transistor T52；With the 5th two-transistor T52
Grid connection the May 4th transistor T54；With the 5th two-transistor T52 May Day transistor T51 source electrodes for being connected of drain electrode and
Five or three transistor gate T53, May Day transistor T51 grids, drain electrode and the drain electrode of the five or three transistor T53 connection CK
Clock signal；The grid of the May 4th transistor T54 being connected with the 5th two-transistor T52 grids；With the five or three transistor T53 sources
Pole and the 3rd two-transistor T32 grids of the May 4th transistor T54 drain electrodes connection simultaneously；Connect with the 3rd two-transistor T32 grids
The 4th two-transistor T42 grids for connecing；4th two-transistor T42 drain electrodes N grades of signal Q (N) point of connection.
Embodiment 3
The present embodiment further illustrates the first drop-down maintenance module and connects the first low-frequency clock on the basis of embodiment 1
Other selections outside signal LC1：
As described in Fig. 2 and Fig. 4, the second drop-down maintenance module includes：6th two-transistor T62；With the 6th two-transistor T62
Grid connection the six or four transistor T64；With the 6th two-transistor T62 the 6th 1 transistor T61 source electrodes that are connected of drain electrode and
Six or three transistor T63 grids, the 6th 1 transistor gate T61, drain electrode and the drain electrode of the six or the three transistor T63 connect
Connect XCK clock signals；The grid of the six or four transistor T64 being connected with the 6th two-transistor T62 grids；With the six or three transistor
T63 source electrodes and the three or three transistor T33 grids of the six or four transistor T64 drain electrodes connection simultaneously；With the three or three transistor T33 grid
Four or three transistor T43 grids of pole connection；Four or three transistor T43 drain electrodes N grades of signal Q (N) point of connection.
Embodiment 4
The present embodiment further illustrates second annexation of drop-down module on the basis of embodiment 1, such as Fig. 2 and
Described in Fig. 4, the grid of the 4th 1 transistor T41 and the 3rd 1 transistor T31 connects N+i+1 grades of horizontal scanning line (G (N jointly
+i+1)。
Although being described to illustrative specific embodiment of the invention above, in order to the technology of the art
Personnel are it will be appreciated that the present invention, but the present invention is not limited only to the scope of specific embodiment, to the common skill of the art
For art personnel, as long as long as various change is in appended claim restriction and the spirit and scope of the invention for determining, one
The innovation and creation using present inventive concept are cut in the row of protection.
Claims (10)
1. a kind of GOA cascade circuits for large size panel, it is characterised in that including the multiple GOA units for cascading, N grades
GOA unit correspondence drives N grades of horizontal scanning line (G (N)), and the N grades of GOA unit includes 2a CK clock signal；
Pull-up module for CK clock signals to be output as signal, the pull-up module connects N grades of horizontal scanning line
(G (N)) and CK clock signals；
The lower transmission module being connected with CK clock signals, signal ST (N) is passed down for exporting；
By N grades of horizontal scanning line (G (N)) down for the drop-down module of low potential, N grades of horizontal scanning line (G (N)) is connected,
N+a grades of horizontal scanning line (G (N+a)) and VSS DC low-voltages；
N grades of horizontal scanning line (G (N)) signal is maintained the drop-down maintenance module of negative potential, the drop-down maintenance module connects
Connect Q (N) point, N grades of horizontal scanning line (G (N)) and VSS DC low-voltages；
The drop-down maintenance module includes the first drop-down holding circuit and the second drop-down maintenance electricity that alternating action, mirror image are connected
Road；The first drop-down maintenance module connects the first low-frequency clock signal (LC1), the second drop-down maintenance module connection second
Low-frequency clock signal (LC2)；
And for the bootstrap capacitor (Cb) of lifting current potential, bootstrap capacitor (Cb) described connection drop-down maintenance module, Q (N)
Point and N grades of horizontal scanning line (G (N)；
I-stage GOA unit also includes the pulling drive module of control pull-up module opening time, institute in preceding a grades of GOA unit circuit
State pulling drive module connection STVi pulse signals and Q (N) point；
Wherein i=1,2,3 ... a, a are the natural number less than N/2, and N is natural number.
2. GOA cascade circuits for large size panel according to claim 1, it is characterised in that：The i-stage GOA
In unit, STVi pulse signals are drained by the seven or seven transistor (T77) and the seven or eight transistor (T78) source electrode is exported jointly, institute
State the seven or seven transistor gate (T77) connection cki clock signals, source electrode connection VSS DC low-voltages；With the seven or seven transistor
(T77) the seven or eight transistor (T78) of connection, the seven or eight transistor (T78) grid, drain electrode are all connected with STV pulse signals.
3. GOA cascade circuits for large size panel according to claim 1, it is characterised in that：First low frequency
Clock signal (LC1) and the low frequency signal source that second low-frequency clock signal (LC2) is opposite in phase.
4. GOA cascade circuits for large size panel according to claim 1, it is characterised in that：Described first is drop-down
Maintenance module connects the pulling drive module, including：5th two-transistor (T52)；With the grid of the 5th two-transistor (T52)
The May 4th transistor (T54) of connection；With the 5th two-transistor (T52) May Day transistor (T51) source electrode for being connected of drain electrode and
Five or three transistor gate (T53), May Day transistor (T51) grid, drain electrode and the drain electrode of the five or three transistor (T53)
It is connected in the first low-frequency clock signal (LC1)；The May 4th transistor (T54) being connected with the 5th two-transistor (T52) grid
Grid；The 3rd two-transistor being connected simultaneously with the five or three transistor (T53) source electrode and the May 4th transistor (T54) drain electrode
(T32) grid；The 4th two-transistor (T42) grid being connected with the 3rd two-transistor (T32) grid；4th two-transistor
(T42) N grades of signal Q (N) point of drain electrode connection.
5. GOA cascade circuits for large size panel according to claim 4, it is characterised in that：Described 5th 3 is brilliant
The drain electrode of body pipe (T53) is changed to connection CK signals all the time.
6. GOA cascade circuits for large size panel according to claim 1, it is characterised in that：Described second is drop-down
Maintenance module connects the pulling drive module, including：6th two-transistor (T62)；With the grid of the 6th two-transistor (T62)
Six or four transistor (T64) of connection；With the 6th two-transistor (T62) the 6th 1 transistor (T61) source electrode that is connected of drain electrode and
Six or three transistor (T63) grid, the 6th 1 transistor gate (T61), drain electrode and the drain electrode of the six or three transistor (T63)
It is connected in the second low-frequency clock signal (LC2)；The six or four transistor (T64) being connected with the 6th two-transistor (T62) grid
Grid；The three or three transistor being connected simultaneously with the six or three transistor (T63) source electrode and the drain electrode of the six or four transistor (T64)
(T33) grid；The four or three transistor (T43) grid being connected with the three or three transistor (T33) grid；Four or three transistor
(T43) N grades of signal Q (N) point of drain electrode connection.
7. GOA cascade circuits for large size panel according to claim 6, it is characterised in that：Described 6th 3 is brilliant
The drain electrode of body pipe (T63) is changed to connect XCK clock signals.
8. GOA cascade circuits for large size panel according to claim 1, it is characterised in that：The drop-down module
Including the 4th 1 transistor (T41) and the 3rd 1 transistor (T31), the 4th 1 transistor (T41) and the 3rd 1 transistor
(T31) grid connects N+a grades of horizontal scanning line (G (N+a)), the common connection VSS DC low-voltages of drain electrode jointly.
9. GOA cascade circuits for large size panel according to claim 1, it is characterised in that：Described 4th 1 is brilliant
The grid of body pipe (T41) and the 3rd 1 transistor (T31) connects N+a+1 grades of horizontal scanning line (G (N+a+1)) jointly.
10. according to any described GOA cascade circuits for large size panel of claim 1-9, it is characterised in that：The a
=4.
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| CN108922488A (en) * | 2018-08-31 | 2018-11-30 | 重庆惠科金渝光电科技有限公司 | array substrate, display panel and display device |
| CN109036316A (en) * | 2018-09-07 | 2018-12-18 | 深圳市华星光电技术有限公司 | Goa circuit and liquid crystal display panel |
| CN109102782A (en) * | 2018-10-16 | 2018-12-28 | 深圳市华星光电半导体显示技术有限公司 | Gate driving circuit and the liquid crystal display for using the gate driving circuit |
| WO2020019407A1 (en) * | 2018-07-23 | 2020-01-30 | 深圳市华星光电技术有限公司 | Goa circuit and liquid crystal display device having goa circuit |
| CN111883066A (en) * | 2020-07-09 | 2020-11-03 | 深圳市华星光电半导体显示技术有限公司 | Gate electrode drive design method and device and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107610668A (en) * | 2017-10-20 | 2018-01-19 | 深圳市华星光电半导体显示技术有限公司 | A kind of GOA circuits and liquid crystal panel, display device |
| WO2019075792A1 (en) * | 2017-10-20 | 2019-04-25 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit, liquid crystal panel and display apparatus |
| CN107610668B (en) * | 2017-10-20 | 2019-05-24 | 深圳市华星光电半导体显示技术有限公司 | A kind of GOA circuit and liquid crystal display panel, display device |
| WO2020019407A1 (en) * | 2018-07-23 | 2020-01-30 | 深圳市华星光电技术有限公司 | Goa circuit and liquid crystal display device having goa circuit |
| US10957270B1 (en) | 2018-07-23 | 2021-03-23 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | GOA circuit and liquid crystal display device having the same |
| CN108922488A (en) * | 2018-08-31 | 2018-11-30 | 重庆惠科金渝光电科技有限公司 | array substrate, display panel and display device |
| US11151954B2 (en) | 2018-08-31 | 2021-10-19 | Chongqing Hkc Optoelectronics Technology Co., Ltd. | Array substrate, display panel and display device |
| CN109036316A (en) * | 2018-09-07 | 2018-12-18 | 深圳市华星光电技术有限公司 | Goa circuit and liquid crystal display panel |
| CN109102782A (en) * | 2018-10-16 | 2018-12-28 | 深圳市华星光电半导体显示技术有限公司 | Gate driving circuit and the liquid crystal display for using the gate driving circuit |
| WO2020077924A1 (en) * | 2018-10-16 | 2020-04-23 | 深圳市华星光电半导体显示技术有限公司 | Gate driving circuit and liquid crystal display using same |
| CN111883066A (en) * | 2020-07-09 | 2020-11-03 | 深圳市华星光电半导体显示技术有限公司 | Gate electrode drive design method and device and electronic equipment |
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|---|---|
| CN106710550B (en) | 2019-03-19 |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |