CN206370275U - Clock control circuit, gate driving circuit and display device - Google Patents
Clock control circuit, gate driving circuit and display device Download PDFInfo
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- CN206370275U CN206370275U CN201720007636.8U CN201720007636U CN206370275U CN 206370275 U CN206370275 U CN 206370275U CN 201720007636 U CN201720007636 U CN 201720007636U CN 206370275 U CN206370275 U CN 206370275U
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Abstract
The utility model discloses a kind of clock control circuit, gate driving circuit and display device, belong to display technology field.The clock control circuit is connected by first node with the 3rd clock signal terminal, is connected by Section Point with the 4th clock signal terminal, the 3rd clock signal can be exported to Section Point, and export the 4th clock signal to first node.Therefore it is the composite signal of the 3rd clock signal and the 4th clock signal that the clock signal that the first node and Section Point are exported, which can be caused, and wherein the first node and Section Point are the clock signal input node of each shift register cell in gate driving circuit.Therefore, the clock control circuit that the utility model is provided can provide the clock signal with top rake waveform to each shift register cell, so as to slow down the potential change amplitude for the drive signal that each shift register cell is exported, avoid display picture from the phenomenons such as flicker and image retention occur, improve the display effect of display device.
Description
Technical field
The utility model is related to display technology field, more particularly to a kind of clock control circuit, gate driving circuit and aobvious
Showing device.
Background technology
Display device is in display image, it is necessary to be scanned using gate driving circuit to pixel cell, raster data model
Circuit includes multiple cascaded shift registers units, and each shift register cell corresponds to one-row pixels unit, and can be to this
The grid output scanning pulse signal of thin film transistor (TFT), is realized by multiple shift register cells and display is filled in row pixel cell
The progressive scan driving of middle multirow pixel cell is put, with display image.
In gate driving circuit in correlation technique, each shift register cell can by from clock signal terminal when
Clock signal output to output end, the clock signal of the output is generally square-wave signal.But, the film crystal in each pixel cell
Generally there is parasitic capacitance, so when shift register output end is applied to the grid of thin film transistor (TFT) between the grid and source electrode of pipe
When the level of the scanning pulse signal of pole changes, such as low level is changed to by high level, the grid electricity of the thin film transistor (TFT)
Position can produce huge fall.And influenceed by parasitic capacitance, the source potential of the thin film transistor (TFT) can also produce it is huge fall, hold
Logical (feed through) phenomenon of bursting is also easy to produce, and then causes the display picture of display device the phenomenons such as flicker and image retention occur,
The display effect of display device is poor.
Utility model content
In order to solve the problem of phenomenons such as flicker and image retention easily occurs in the display picture of the display device in correlation technique,
The utility model provides a kind of clock control circuit, gate driving circuit and display device.The technical scheme is as follows：
First aspect is there is provided a kind of clock control circuit, applied in gate driving circuit, the gate driving circuit
Include the shift register cell of at least two cascades；
The clock control circuit is connected with the first clock signal terminal, second clock signal end and power supply signal end respectively,
The clock control circuit is also connected by first node with the 3rd clock signal terminal, and passes through Section Point and the 4th clock
Signal end is connected, and the first node and the Section Point are each shift register cell in the gate driving circuit
Clock signal input node；
The clock control circuit is used in the first clock signal from first clock signal terminal, from described the
Under the control of the second clock signal of two clock signal terminals and power supply signal from the power supply signal end, to described second
Node exports the 3rd clock signal from the 3rd clock signal terminal, and to first node output from described the
4th clock signal of four clock signal terminals；
Wherein, first clock signal is identical with the frequency of the second clock signal, and phase is different, when the described 3rd
Clock signal is identical with the frequency of the 4th clock signal, opposite in phase, and the frequency of first clock signal is described the
Twice of the frequency of three clock signals.
Optionally, the clock control circuit, including：Control module and switch module；
The control module respectively with first clock signal terminal, the second clock signal end, the power supply signal
End and switching node connection, for the control in first clock signal, the second clock signal and the power supply signal
Under, control the current potential of the switching node；
The switch module is connected with the switching node, and passes through the first node and the 3rd clock signal terminal
Connection, and is connected by the Section Point with the 4th clock signal terminal, under the control of the switching node,
The 3rd clock signal is exported to the Section Point, and the 4th clock signal is exported to the first node.
Optionally, the control module, including：The first transistor and second transistor；
The grid of the first transistor and the first pole are connected with first clock signal terminal respectively, the second pole with it is described
Switching node is connected；
The grid of the second transistor is connected with the second clock signal end, and the first pole connects with the power supply signal end
Connect, the second pole is connected with the switching node.
Optionally, the switch module, including：Third transistor and the first capacitor；
The grid of the third transistor is connected with the switching node, the first pole and the 4th clock signal terminal and institute
Section Point connection is stated, the second pole is connected with the 3rd clock signal terminal and the first node；
One end of first capacitor is connected with the switching node, and the other end is connected with the Section Point.
Optionally, the ratio between conducting channel width of the second transistor and the first transistor is more than or equal to default
Threshold value.
Optionally, the transistor is N-type transistor.
Second aspect includes there is provided a kind of gate driving circuit, the gate driving circuit：
Clock control circuit as described in relation to the first aspect, and at least two shift register cells cascaded；
It is described at least two cascade shift register cells in, each shift register cell respectively with input signal
End, reset signal end, first node, Section Point and the connection of power supply signal end, in the first node, the second section
Point, the power supply signal from the power supply signal end, the input signal from the input signal end and from it is described reset
Under the control of the reset signal of signal end, the current potential of the output end of each shift register cell is controlled.
Optionally, each shift register cell includes：Output control module and output module；
The output control module respectively with the input signal end, the reset signal end, the power supply signal end, institute
Section Point, pull-up node and output end connection are stated, in the input signal, the reset signal, the power supply signal
Under control with the Section Point, the current potential of the pull-up node and the output end is controlled；
The output module is connected with the first node, the pull-up node and the output end respectively, in institute
Under the control for stating pull-up node and the first node, the current potential of the output end is controlled.
Optionally, the output control module, including：4th transistor, the 5th transistor, the 6th transistor, the 7th crystalline substance
Body pipe, the 8th transistor, the 9th transistor, the tenth transistor, the 11st transistor and the tenth two-transistor；The output mould
Block, including：13rd transistor and the second capacitor；
The grid of 4th transistor and the first pole are connected with the input signal end, the second pole and the pull-up node
Connection；
The grid of 5th transistor is connected with the reset signal end, and the first pole is connected with the power supply signal end,
Second pole is connected with the pull-up node；
The grid of 6th transistor is connected with the reset signal end, and the first pole is connected with the power supply signal end,
Second pole is connected with the output end；
The grid of 7th transistor is connected with pull-down node, and the first pole is connected with the power supply signal end, the second pole
It is connected with the pull-up node；
The grid of 8th transistor is connected with the pull-down node, and the first pole is connected with the power supply signal end, the
Two poles are connected with the output end；
The grid of 9th transistor and the first pole are connected with the Section Point, the second pole and the tenth transistor
Grid connection；
The grid of tenth transistor respectively with the second pole of the 9th transistor and the 11st transistor
Second pole is connected, and the first pole of the tenth transistor is connected with the Section Point, and the second pole is connected with the pull-down node；
The grid of 11st transistor is connected with the pull-up node, and the first pole is connected with the power supply signal end,
Second pole is connected with the grid of the tenth transistor；
The grid of tenth two-transistor is connected with the pull-up node, and the first pole is connected with the power supply signal end,
Second pole is connected with the pull-down node.
The grid of 13rd transistor is connected with the pull-up node, and the first pole is connected with the first node, the
Two poles are connected with the output end；
One end of second capacitor is connected with the pull-up node, and the other end is connected with the output end.
The third aspect includes there is provided a kind of display device, the display device：
Gate driving circuit as described in second aspect.
The beneficial effect brought of technical scheme that the utility model is provided is：
The utility model provides a kind of clock control circuit, gate driving circuit and display device, clock control electricity
Road is connected by first node with the 3rd clock signal terminal, is connected by Section Point with the 4th clock signal terminal.And the clock
Circuit is controlled to export the 3rd to Section Point after saltus step occurs for the current potential of the 3rd clock signal or the 4th clock signal
Clock signal, and the 4th clock signal is exported to first node, wherein first node and Section Point is raster data model electricity
The clock signal input node of each shift register cell in road.Due to the frequency of the 3rd clock signal and the 4th clock signal
Rate is identical, opposite in phase, therefore can cause after the jump in potential of the 3rd clock signal or the 4th clock signal, first segment
The clock signal that point and Section Point are exported is the composite signal of the 3rd clock signal and the 4th clock signal, so as to avoid this
The clock signal of two node outputs directly drops to the second current potential from the first current potential.Shift register in gate driving circuit
When the clock signal that unit is exported according to two nodes is scanned driving to pixel cell, it can slow down thin in pixel cell
The amplitude of film transistor grid potential change, and then display picture can be avoided the phenomenons such as flicker and image retention occur, improve display
The display effect of device.
Brief description of the drawings
, below will be to needed for embodiment description in order to illustrate more clearly of the technical scheme in the utility model embodiment
The accompanying drawing to be used is briefly described, it should be apparent that, drawings in the following description are only some realities of the present utility model
Example is applied, for those of ordinary skill in the art, on the premise of not paying creative work, can also be according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is a kind of structural representation for clock control circuit that the utility model embodiment is provided；
Fig. 2 is the structural representation for another clock control circuit that the utility model embodiment is provided；
Fig. 3 is the structural representation for another clock control circuit that the utility model embodiment is provided；
Fig. 4 is a kind of partial structural diagram for gate driving circuit that the utility model embodiment is provided；
Fig. 5 is the partial structural diagram for another gate driving circuit that the utility model embodiment is provided；
Fig. 6 is a kind of driving method flow chart for clock control circuit that the utility model embodiment is provided；
Fig. 7 is a kind of driving process timing diagram for clock control circuit that the utility model embodiment is provided.
Embodiment
It is new to this practicality below in conjunction with accompanying drawing to make the purpose of this utility model, technical scheme and advantage clearer
Type embodiment is described in further detail.
The transistor used in all embodiments of the utility model can for thin film transistor (TFT) or FET or other
Characteristic identical device, the transistor used according to effect embodiment of the present utility model in circuit is mainly that switch is brilliant
Body pipe.Because the source electrode of the switching transistor that uses here, drain electrode are symmetrical, so its source electrode, drain electrode can be exchanged.
In the utility model embodiment, to distinguish the two poles of the earth of transistor in addition to grid, wherein it will be referred to as the first pole by source electrode, drain electrode claims
For the second pole.Provide that the intermediate ends of transistor are that grid, signal input part are that source electrode, signal output part are by the form in accompanying drawing
Drain electrode.The switching transistor that the utility model embodiment is used can be N-type switching transistor, and N-type switching transistor is
Turn on, end when grid is low potential when grid is high potential.In addition, multiple letters in each embodiment of the utility model
Number all to that should have the first current potential and the second current potential, the current potential that the first current potential and the second current potential only represent the signal has 2 quantity of states,
Not representing the first current potential or the second current potential in full text has specific numerical value.
Fig. 1 is a kind of structural representation for clock control circuit that the utility model embodiment is provided, as shown in figure 1, should
Clock control circuit 10 can apply in gate driving circuit, and the gate driving circuit can include：At least two cascades
Shift register cell 00.
With reference to Fig. 1, the clock control circuit 10 respectively with the first clock signal terminal CLK1, second clock signal end CLK2 and
Power supply signal end VSS connections, the clock control circuit 10 is also connected by first node P1 with the 3rd clock signal terminal CLK3, with
And be connected by Section Point P2 with the 4th clock signal terminal CLK4.From figure 1 it appears that first node P1 and second section
Point P2 is the clock signal input node of each shift register cell 00 in the gate driving circuit.
The clock control circuit 10 can the first clock signal from first clock signal terminal CLK1, from this
Under the control of two clock signal terminal CLK2 second clock signal and power supply signal from power supply signal end VSS, to this
Two node P2 export the 3rd clock signal from the 3rd clock signal terminal CLK3, and are come to first node P1 outputs
4th clock signal terminal CLK4 the 4th clock signal.
Wherein, first clock signal is identical with the frequency of the second clock signal, and phase is different, the 3rd clock signal
It is identical with the frequency of the 4th clock signal, opposite in phase, and the frequency of first clock signal is the 3rd clock signal
Twice of frequency.
In summary, the utility model provides a kind of clock control circuit, and the clock control circuit passes through Section Point
It is connected, is connected by first node with the 3rd clock signal terminal with the 4th clock signal terminal.And the clock control circuit can be
The current potential of 3rd clock signal or the 4th clock signal occurs after saltus step, and the 3rd clock signal is exported to Section Point, and
The 4th clock signal is exported to first node, wherein first node and Section Point is posted for each displacement in gate driving circuit
The clock signal input node of storage unit.Because the 3rd clock signal is identical with the frequency of the 4th clock signal, phase phase
Instead, therefore it can cause after the jump in potential of the 3rd clock signal or the 4th clock signal, first node and Section Point
The clock signal of output is the composite signal of the 3rd clock signal and the 4th clock signal, so as to avoid two node outputs
Clock signal directly drop to the second current potential from the first current potential.Shift register cell in gate driving circuit according to this two
When the clock signal of individual node output is scanned driving to pixel cell, thin-film transistor gate in pixel cell can be slowed down
The amplitude of potential change, and then display picture can be avoided the phenomenons such as flicker and image retention occur, improve the display effect of display device
Really.
Fig. 2 is a kind of structural representation for clock control circuit that the utility model embodiment is provided, with reference to Fig. 2, this when
Clock circuit 10 can include：Control module 101 and switch module 102.
The control module 101 is believed with first clock signal terminal CLK1, second clock signal end CLK2, the power supply respectively
Number end VSS and switching node P3 connections, for the control in first clock signal, the second clock signal and the power supply signal
Under, control switching node P3 current potential.
The switch module 102 is connected with switching node P3, and passes through first node P1 and the 3rd clock signal terminal
CLK3 connections, and be connected by Section Point P2 with the 4th clock signal terminal CLK4, for switching node P3's
Under control, the 3rd clock signal is exported to Section Point P2, and the 4th clock signal is exported to first node P1.
Understand that under the control of the 3rd clock signal terminal CLK3 and the clock control circuit 10, first node P1 is final with reference to Fig. 2
The clock signal exported to each shift register cell is CLK3-S；In the 4th clock signal terminal CLK4 and the clock control
Under the control of circuit 10, the final clock signals exported to each shift register cell of Section Point P2 are CLK4-S.
Fig. 3 is the structural representation for another clock control circuit that the utility model embodiment is provided, with reference to Fig. 3, should
Control module 101 can include：The first transistor M1 and second transistor M2.
The first transistor M1 grid and the first pole are connected with first clock signal terminal CLK1 respectively, and the second pole is with being somebody's turn to do
Switching node P3 connections.
Second transistor M2 grid is connected with second clock signal end CLK2, the first pole and the power supply signal end
VSS connections, the second pole is connected with switching node P3.
Wherein, the second transistor M2 conducting channel width W2 and the first transistor M1 conducting channel width W1 it
Than：W2/W1 can be more than or equal to predetermined threshold value.During so that proper second transistor M2 and the first transistor M1 being both turned on,
Switching node P3 current potential can be the current potential of the power supply signal.Example, in actual applications, the predetermined threshold value can be
5, the second transistor M2 conducting channel width W2 can be 50 microns (um), the first transistor M1 conducting channel width W1
Can be 10um.
Optionally, as shown in figure 3, the switch module 102 can include：Third transistor M3 and the first capacitor C1.
Third transistor M3 grid is connected with switching node P3, the first pole and the 4th clock signal terminal CLK4 and
Section Point P2 connections, the second pole is connected with the 3rd clock signal terminal CLK3 and first node P1.
First capacitor C1 one end is connected with switching node P3, when the other end is with Section Point P2 and the 4th
The CLK4 connections of clock signal end.
In summary, the utility model provides a kind of clock control circuit, and the clock control circuit passes through Section Point
It is connected, is connected by first node with the 3rd clock signal terminal with the 4th clock signal terminal.And the clock control circuit can be
The current potential of 3rd clock signal or the 4th clock signal occurs after saltus step, and the 3rd clock signal is exported to Section Point, and
The 4th clock signal is exported to first node, wherein first node and Section Point is posted for each displacement in gate driving circuit
The clock signal input node of storage unit.Because the 3rd clock signal is identical with the frequency of the 4th clock signal, phase phase
Instead, therefore it can cause after the jump in potential of the 3rd clock signal or the 4th clock signal, first node and Section Point
The clock signal of output is the composite signal of the 3rd clock signal and the 4th clock signal, so as to avoid two node outputs
Clock signal directly drop to the second current potential from the first current potential.Shift register cell in gate driving circuit according to this two
When the clock signal of individual node output is scanned driving to pixel cell, thin-film transistor gate in pixel cell can be slowed down
The amplitude of potential change, and then display picture can be avoided the phenomenons such as flicker and image retention occur, improve the display effect of display device
Really.
The utility model additionally provides a kind of gate driving circuit, and the gate driving circuit can include Fig. 1 to Fig. 3 such as and appoint
Clock control circuit shown in one, and at least two shift register cells cascaded.With reference to Fig. 1, at least two cascade
Shift register cell in, each shift register cell 00 respectively with input signal end IN, reset signal end RST, first
Node P1, Section Point P2 and the VSS connections of power supply signal end, in first node P1, Section Point P2, from input
Signal end IN input signal, the reset signal from reset signal end RST, power supply signal from power supply signal end VSS
Under control, the output end OUT of each shift register cell current potential is controlled.
Fig. 4 is a kind of partial structural diagram for gate driving circuit that the utility model embodiment is provided, and is shown in Fig. 4
Clock control circuit and a shift register cell in gate driving circuit.As shown in figure 4, the gate driving circuit
In each shift register cell 00 can include：Output control module 20 and output module 30.
The output control module 20 respectively with input signal end IN, reset signal end RST, power supply signal end VSS, second section
Point P2, pull-up node PU and output end OUT connections, in the input signal from input signal end IN, from the reset
Under the control of signal end RST reset signal, the power supply signal from power supply signal end VSS and Section Point P2, control
Pull-up node PU and output end OUT current potential.
The output module 30 is connected with first node P1, pull-up node PU and output end OUT respectively, on this
Under the control for drawing node PU and first node P1, output end OUT current potential is controlled.
Further, as shown in figure 5, the output control module 20 can include：4th transistor M4, the 5th transistor
M5, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the tenth transistor M10, the 11st crystalline substance
Body pipe M11 and the tenth two-transistor M12.The output module 30 can include：13rd transistor M13 and the second capacitor C2.
Wherein, the 4th transistor M4 grid and the first pole are connected with input signal end IN, the second pole and the pull-up
Node PU connections.
5th transistor M5 grid is connected with reset signal end RST, and the first pole connects with power supply signal end VSS
Connect, the second pole is connected with pull-up node PU；6th transistor M6 grid is connected with reset signal end RST, the first pole
It is connected with power supply signal end VSS, the second pole is connected with output end OUT.
7th transistor M7 grid is connected with pull-down node PD, and the first pole is connected with power supply signal end VSS, and second
Pole is connected with pull-up node PU；8th transistor M8 grid is connected with pull-down node PD, and the first pole is believed with the power supply
Number end VSS connections, the second pole is connected with output end OUT.
9th transistor M9 grid and the first pole are connected with Section Point P2, the second pole and the tenth transistor
M10 grid connection.
Tenth transistor M10 grid the second pole respectively with the 9th transistor M9 and the 11st transistor M11
The connection of the second pole, the tenth transistor M10 the first pole be connected with Section Point P2, the second pole and pull-down node PD companies
Connect.
11st transistor M11 grid is connected with pull-up node PU, and the first pole connects with power supply signal end VSS
Connect, the second pole is connected with the tenth transistor M10 grid.
Tenth two-transistor M12 grid is connected with pull-up node PU, and the first pole connects with power supply signal end VSS
Connect, the second pole is connected with pull-down node PD.
13rd transistor M13 grid is connected with pull-up node PU, and the first pole is connected with first node P1, the
Two poles are connected with output end OUT；Second capacitor C2 one end is connected with pull-up node PU, the other end and the output end
OUT connections.
Further, with reference to Fig. 1, the input signal end IN of each shift register cell 00 can be posted with upper level displacement
The output end OUT of storage unit is connected, and the reset signal end RST of each shift register cell 00 can be posted with next stage displacement
The output end OUT of storage unit is connected.For example, the input signal end IN of shift register cell 2 and shift register list in Fig. 1
The output end OUT of member 1 is connected, and reset signal end RST is connected with the output end OUT of shift register cell 3.
It should be noted that with reference to Fig. 5, the first order displacement in some shift register cell is gate driving circuit
During register cell, the 14th transistor M14, the 14th transistor can also be included in the first order shift register cell
M14 grid and the first pole are connected with frame open signal end STV, and the second pole is connected with pull-down node PD, in each frame figure
As starting before scanning, pull-down node PD current potential being drawn high, pull-up node PU being carried out with will pass through the 7th transistor M7
Noise reduction, and noise reduction is carried out to output end OUT by the 8th transistor M8.
In summary, the utility model provides a kind of gate driving circuit, the clock when gate driving circuit includes
Circuit processed, the clock control circuit can provide the clock signal with top rake waveform to each shift register cell, so that
The potential change amplitude of the drive signal of each shift register cell output is slow down, display picture can be avoided to flash
With the phenomenon such as image retention, the display effect of display device is improved.
With reference to Fig. 6, the driving method flow chart of the clock control circuit provided it illustrates the utility model embodiment, ginseng
Examine Fig. 6 and understand that the driving method can include：
Step 401, first stage, the first clock signal of the first clock signal terminal CLK1 outputs are in the first current potential, the
The second clock signal of two clock signal terminal CLK2 outputs is in the second current potential, the control module 101 controlling switch node P3's
Current potential is the first current potential, and switch module 102 exports the 3rd clock from the 3rd clock signal terminal CLK3 to Section Point P2 to be believed
Number, and export the 4th clock signal from the 4th clock signal terminal CLK4 to first node P1.
Step 402, second stage, the first clock signal of the first clock signal terminal CLK1 outputs are in the first current potential, the
The second clock signal of two clock signal terminal CLK2 outputs is in the first current potential, the control module 101 controlling switch node P3's
Current potential is to be turned off between the second current potential, the control of switch module 102 first node P1 and Section Point P2.
Step 403, phase III, the first clock signal of the first clock signal terminal CLK1 outputs are in the second current potential, the
The second clock signal of two clock signal terminal CLK2 outputs is in the first current potential, the control module 101 controlling switch node P3's
Current potential is to be turned off between the second current potential, the control of switch module 102 first node P1 and Section Point P2.
Afterwards, should when the first clock signal saltus step to the first current potential again that first clock signal terminal CLK1 is exported
Clock control circuit can continue to repeat above-mentioned steps 401 to step 403.
Fig. 7 be the utility model embodiment provide clock control circuit drive process timing diagram, with shown in Fig. 3 when
Exemplified by clock circuit, the driving principle of the clock control circuit is discussed in detail.
As shown in fig. 7, in the first stage in T1, the first clock signal of the first clock signal terminal CLK1 outputs is in first
Current potential, the second clock signal of second clock signal end CLK2 outputs is in the second current potential.Now the first transistor M1 is opened, should
First clock signal is charged to the first capacitor C1, and switching node P3 current potential is drawn high so that third transistor M3 is opened
Open.Now first node P1 and Section Point P2 conductings.Because now the 3rd clock signal is in the second current potential, the 4th clock letter
Number the first current potential is in, after the conducting of two nodes, the electric charge of two clock signals is shared so that first node P1 and second
Node P2 current potential is identical, and is the current potential of the composite signal of the 3rd clock signal and the 4th clock signal.It that is to say, join
Fig. 7 is examined, the signal CLK4-S's that now current potential and Section Point P2 for the signal CLK3-S that first node P1 is exported are exported
Current potential is all higher than second current potential, and less than first current potential.
In second stage T2, the first clock signal of the first clock signal terminal CLK1 outputs is in the first current potential, second
The second clock signal of clock signal terminal CLK2 outputs is in the first current potential.Now second transistor M2 is opened, power supply signal end
VSS exports the power supply signal in the second current potential to switching node P3.Simultaneously as the first transistor M1 is now also at
Opening, the first clock signal terminal CLK1 can export the first clock signal in the first current potential to switching node P3.
The ratio between conducting channel width W2 and the first transistor M1 conducting channel width W1 due to second transistor M2 W2/W1 is more than
Or equal to predetermined threshold value (such as W2/W1 >=5), therefore when now switching node P3 current potential is the second current potential, the 3rd crystal
Pipe M3 is turned off, and is not turned between first node P1 and Section Point P2.Now as shown in fig. 7, the signal of first node P1 outputs
CLK3-S current potential is identical with the current potential of the 3rd clock signal (being now the second current potential), the signal of Section Point P2 outputs
CLK4-S current potential is identical with the current potential of the 4th clock signal (being now the first current potential).
In phase III T3, the first clock signal of the first clock signal terminal CLK1 outputs is in the second current potential, second
The second clock signal of clock signal terminal CLK2 outputs is in the first current potential.Now second transistor M2 continues to keep it turned on shape
State, the first transistor M1 shut-offs.Power supply signal end VSS exports the power supply signal in the second current potential to switching node P3, makes
Obtain third transistor M3 to continue to turn off, do not turned between first node P1 and Section Point P2.Now as shown in fig. 7, first segment
The signal CLK3-S of point P1 outputs current potential is identical with the current potential of the 3rd clock signal, the signal CLK4-S of Section Point P2 outputs
Current potential it is identical with the current potential of the 4th clock signal.
Afterwards, when the first clock signal transitions to the first current potential that the first clock signal terminal CLK1 is exported, you can continue
Repeat for above-mentioned first to phase III.
In summary, in the utility model embodiment, in the presence of the clock control circuit, first node P1 and
The clock signal of Section Point P2 outputs is the clock signal with top rake waveform, the change of the current potential of the clock signal in saltus step
Change amplitude is smaller, so as to the potential change amplitude for the drive signal for reducing each shift register cell output.Also, ginseng
Examine Fig. 7 to understand, in order to ensure that the clock that the clock control circuit enables to first node P1 and Section Point P2 to export is believed
Number there is top rake waveform, the frequency that first clock signal and the frequency of second clock signal are the 3rd clock signal can be caused
Twice of rate (frequency that is to say the 4th clock signal).And it is possible in the 3rd clock signal and the 4th clock signal
During jump in potential so that the second clock signal is from the first jump in potential to the second current potential so that first clock signal is from
Two jumps in potential to the first current potential.
Further, cutting for the clock signal that first node P1 and Section Point P2 is exported is can also be seen that from Fig. 7
The duration in angle stage (i.e. first stage T1) is equal with the duration of the second current potential in the second clock signal.Therefore in reality
In, can by adjusting the dutycycle of first clock signal and second clock signal, come adjust first node P1 and
The top rake waveform of the clock signal of Section Point P2 outputs.Optionally, the duty of first clock signal and second clock signal
Than 9/10ths can be more than or equal to.It that is to say, each of the first clock signal (or second clock signal) can be caused
In clock cycle the duration of the second current potential be less than first clock signal (or second clock signal) clock cycle is very
One of.
It is and the first current potential phase using each transistor as N-type transistor it should be noted that in the various embodiments described above
Explanation for the second current potential to be carried out exemplified by high potential.Certainly, each transistor can also use P-type transistor, when each
When transistor uses P-type transistor, first current potential can be low potential relative to second current potential, and each signal end is defeated
The potential change of the signal entered can be opposite with the potential change shown in Fig. 7 (i.e. the phase difference 180 degree of the two).
In addition, the utility model embodiment also provides a kind of display device, the display device can include such as Fig. 4 or Fig. 5
Shown gate driving circuit.The display device can be：Liquid crystal panel, Electronic Paper, oled panel, AMOLED panel, mobile phone,
Any product or portion with display function such as tablet personal computer, television set, display, notebook computer, DPF, navigator
Part.
Preferred embodiment of the present utility model is the foregoing is only, it is all in this practicality not to limit the utility model
Within new spirit and principle, any modification, equivalent substitution and improvements made etc. should be included in guarantor of the present utility model
Within the scope of shield.
Claims (10)
1. a kind of clock control circuit, it is characterised in that applied in gate driving circuit, the gate driving circuit is included extremely
The shift register cell of few two cascades；
The clock control circuit is connected with the first clock signal terminal, second clock signal end and power supply signal end respectively, described
Clock control circuit is also connected by first node with the 3rd clock signal terminal, and passes through Section Point and the 4th clock signal
End connection, the first node and the Section Point are the clock of each shift register cell in the gate driving circuit
Signal input node；
The clock control circuit be used for the first clock signal from first clock signal terminal, from described second when
Under the control of the second clock signal of clock signal end and power supply signal from the power supply signal end, to the Section Point
Export the 3rd clock signal from the 3rd clock signal terminal, and to the first node output come from the described 4th when
4th clock signal of clock signal end；
Wherein, first clock signal is identical with the frequency of the second clock signal, and phase is different, the 3rd clock letter
Number, opposite in phase identical with the frequency of the 4th clock signal, and the frequency of first clock signal is when being the described 3rd
Twice of the frequency of clock signal.
2. clock control circuit according to claim 1, it is characterised in that the clock control circuit, including：Control mould
Block and switch module；
The control module respectively with first clock signal terminal, the second clock signal end, the power supply signal end and
Switching node is connected, under the control of first clock signal, the second clock signal and the power supply signal, controlling
Make the current potential of the switching node；
The switch module is connected with the switching node, and is connected by the first node and the 3rd clock signal terminal
Connect, and be connected by the Section Point with the 4th clock signal terminal, under the control of the switching node, to
The Section Point exports the 3rd clock signal, and exports the 4th clock signal to the first node.
3. clock control circuit according to claim 2, it is characterised in that the control module, including：The first transistor
And second transistor；
The grid of the first transistor and the first pole are connected with first clock signal terminal respectively, the second pole and the switch
Node is connected；
The grid of the second transistor is connected with the second clock signal end, and the first pole is connected with the power supply signal end,
Second pole is connected with the switching node.
4. clock control circuit according to claim 2, it is characterised in that the switch module, including：Third transistor
With the first capacitor；
The grid of the third transistor is connected with the switching node, the first pole and the 4th clock signal terminal and described the
Two nodes are connected, and the second pole is connected with the 3rd clock signal terminal and the first node；
One end of first capacitor is connected with the switching node, and the other end is connected with the Section Point.
5. clock control circuit according to claim 3, it is characterised in that
The ratio between conducting channel width of the second transistor and the first transistor is more than or equal to predetermined threshold value.
6. according to any described clock control circuit of claim 3 to 5, it is characterised in that
The transistor is N-type transistor.
7. a kind of gate driving circuit, it is characterised in that the gate driving circuit includes：
Clock control circuit as described in claim 1 to 6 is any, and at least two shift register cells cascaded；
In the shift register cells of at least two cascade, each shift register cell respectively with input signal end, multiple
Position signal end, first node, Section Point and power supply signal end connection, for the first node, the Section Point, come
Power supply signal from the power supply signal end, the input signal from the input signal end and from the reset signal end
Reset signal control under, control the current potential of the output end of each shift register cell.
8. gate driving circuit according to claim 7, it is characterised in that each shift register cell includes：
Output control module and output module；
The output control module respectively with the input signal end, the reset signal end, the power supply signal end, described
Two nodes, pull-up node and output end connection, in the input signal, the reset signal, the power supply signal and institute
Under the control for stating Section Point, the current potential of the pull-up node and the output end is controlled；
The output module is connected with the first node, the pull-up node and the output end respectively, for described
Under the control for drawing node and the first node, the current potential of the output end is controlled.
9. gate driving circuit according to claim 8, it is characterised in that the output control module, including：4th is brilliant
Body pipe, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor, the 9th transistor, the tenth transistor, the 11st
Transistor and the tenth two-transistor；The output module, including：13rd transistor and the second capacitor；
The grid of 4th transistor and the first pole are connected with the input signal end, and the second pole connects with the pull-up node
Connect；
The grid of 5th transistor is connected with the reset signal end, and the first pole is connected with the power supply signal end, and second
Pole is connected with the pull-up node；
The grid of 6th transistor is connected with the reset signal end, and the first pole is connected with the power supply signal end, and second
Pole is connected with the output end；
The grid of 7th transistor is connected with pull-down node, and the first pole is connected with the power supply signal end, the second pole and institute
State pull-up node connection；
The grid of 8th transistor is connected with the pull-down node, and the first pole is connected with the power supply signal end, the second pole
It is connected with the output end；
The grid of 9th transistor and the first pole are connected with the Section Point, the second pole and the grid of the tenth transistor
Pole is connected；
The grid of tenth transistor respectively with the second pole of the 9th transistor and the 11st transistor second
Pole is connected, and the first pole of the tenth transistor is connected with the Section Point, and the second pole is connected with the pull-down node；
The grid of 11st transistor is connected with the pull-up node, and the first pole is connected with the power supply signal end, and second
Pole is connected with the grid of the tenth transistor；
The grid of tenth two-transistor is connected with the pull-up node, and the first pole is connected with the power supply signal end, and second
Pole is connected with the pull-down node；
The grid of 13rd transistor is connected with the pull-up node, and the first pole is connected with the first node, the second pole
It is connected with the output end；
One end of second capacitor is connected with the pull-up node, and the other end is connected with the output end.
10. a kind of display device, it is characterised in that the display device includes：
Gate driving circuit as described in claim 7 to 9 is any.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720007636.8U CN206370275U (en) | 2017-01-04 | 2017-01-04 | Clock control circuit, gate driving circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720007636.8U CN206370275U (en) | 2017-01-04 | 2017-01-04 | Clock control circuit, gate driving circuit and display device |
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| Publication Number | Publication Date |
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| CN206370275U true CN206370275U (en) | 2017-08-01 |
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| CN201720007636.8U Expired - Fee Related CN206370275U (en) | 2017-01-04 | 2017-01-04 | Clock control circuit, gate driving circuit and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107342038A (en) * | 2017-09-13 | 2017-11-10 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method, gate driving circuit and display device |
| CN109389926A (en) * | 2017-08-11 | 2019-02-26 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, array substrate |
| CN110767194A (en) * | 2019-11-11 | 2020-02-07 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display panel |
| CN114360457A (en) * | 2022-01-26 | 2022-04-15 | 深圳市华星光电半导体显示技术有限公司 | Emission drive circuit and display device |
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2017
- 2017-01-04 CN CN201720007636.8U patent/CN206370275U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109389926A (en) * | 2017-08-11 | 2019-02-26 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, array substrate |
| US11244593B2 (en) | 2017-08-11 | 2022-02-08 | Boe Technology Group Co., Ltd. | Shift-register circuit, gate-driving circuit, and array substrate of a display panel |
| CN109389926B (en) * | 2017-08-11 | 2022-02-25 | 京东方科技集团股份有限公司 | Shift register, grid drive circuit and array substrate |
| CN107342038A (en) * | 2017-09-13 | 2017-11-10 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method, gate driving circuit and display device |
| US10685615B2 (en) | 2017-09-13 | 2020-06-16 | Boe Technology Group Co., Ltd. | Shift register and driving method thereof, gate driving circuit, and display device |
| CN107342038B (en) * | 2017-09-13 | 2021-04-02 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof, grid driving circuit and display device |
| CN110767194A (en) * | 2019-11-11 | 2020-02-07 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display panel |
| CN114360457A (en) * | 2022-01-26 | 2022-04-15 | 深圳市华星光电半导体显示技术有限公司 | Emission drive circuit and display device |
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