CN108665930A - A kind of nand flash memory chip - Google Patents
A kind of nand flash memory chip Download PDFInfo
- Publication number
- CN108665930A CN108665930A CN201710212610.1A CN201710212610A CN108665930A CN 108665930 A CN108665930 A CN 108665930A CN 201710212610 A CN201710212610 A CN 201710212610A CN 108665930 A CN108665930 A CN 108665930A
- Authority
- CN
- China
- Prior art keywords
- module
- signal
- register
- shift register
- flash memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008054 signal transmission Effects 0.000 claims abstract description 11
- 230000015654 memory Effects 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000010923 batch production Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
Abstract
The embodiment of the invention discloses a kind of nand flash memory chips, the chip includes the first module and multiple second modules, first module is to each multiple signals of second module transfer, it include register in each second module, multiple second mould registers in the block connect into shift register, first module is connected to the input terminal of the shift register, for passing through the shift register, and under clock control, successively to the signal needed for each second module transfer, wherein, the number for completing the clock cycle needed for whole signal transmissions is identical as the number of the second module.Nand flash memory chip provided in an embodiment of the present invention can solve in the prior art, and because the connecting line quantity of intermodule is more, the problem of influencing chip area utilization rate has achieved the effect that improve chip area utilization rate.
Description
Technical field
The present embodiments relate to memory technology more particularly to a kind of nand flash memory chips.
Background technology
Nand flash memory is one kind of Flash memories, belongs to nonvolatile semiconductor memory.
Include multiple and different modules in nand flash memory, and there are more signal transmissions, such as Fig. 1 between different modules
It is shown, module 1 to be provided respectively to module a, module b, module c and module d a plurality of signal such as signal a1-an, signal b1-bn,
Signal c1-cn and signal d1-dn, wherein module 1 is, for example, the gating circuit of X-direction, and module a-d is, for example, data block a-d,
Gating circuit is connect with each data multiple wordline in the block, and required voltage can be provided for wordline by gating circuit.
Multiple signal transmissions between disparate modules are required for being embodied on domain, and enough spaces are needed on domain
It realizes.Therefore, chip area utilization rate how is improved, urgent problem to be solved is become.
Invention content
The embodiment of the present invention provides a kind of nand flash memory chip, to improve chip area utilization rate.
In a first aspect, an embodiment of the present invention provides a kind of nand flash memory chip, the chip includes the first module and more
A second module, the first module to each multiple signals of second module transfer,
Include register in each second module, multiple second mould registers in the block connect into shift register, the
One module is connected to the input terminal of the shift register, for passing through the shift register, and under clock control, successively
To the signal needed for each second module transfer, wherein complete the number and second of the clock cycle needed for whole signal transmissions
The number of module is identical.
Further, when signal number all same of first module to each second module transfer, each second module
In register digit and the signal number all same.
Further, when the first module is differed to the signal number of each second module transfer, each second module
In register digit it is identical, and the digit and the signal number phase needed for the largest number of second modules of desired signal
Together.
Further, when the first module is differed to the signal number of each second module transfer, according to the second module
Required signal number arranges the second module, and each second from the near to the distant from more to few sequence, and with the first module
Respectively required signal number is identical for the digit of mould register in the block and each second module.
The embodiment of the present invention is in the block by the second mould by the first module signal multiple to each second module transfer
Register constitutes shift register, and under the control of the clock signal of shift register, the multiple signal is transmitted respectively
To the multiple second module, the connecting line quantity solved in the prior art because of intermodule is more, influences chip area utilization
The problem of rate, has achieved the effect that improve chip area utilization rate.
Description of the drawings
Fig. 1 is the nand flash memory domain schematic diagram of the prior art；
Fig. 2 is the nand flash memory chip domain arrangement schematic diagram that the embodiment of the present invention one provides；
Fig. 3 is nand flash memory chip domain arrangement schematic diagram provided by Embodiment 2 of the present invention；
Fig. 4 is the nand flash memory chip domain arrangement schematic diagram that the embodiment of the present invention three provides.
Specific implementation mode
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limitation of the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
Fig. 2 is the nand flash memory chip domain arrangement schematic diagram that the embodiment of the present invention one provides, and the present embodiment is applicable to
NAND flash memory equipment, the NAND chip include the first module and multiple second modules, and the first module is to each second module transfer
Multiple signals.The nand flash memory chip that the embodiment of the present invention one provides specifically includes：
Include register in each second module, multiple second mould registers in the block connect into shift register, the
One module is connected to the input terminal of the shift register, for passing through the shift register, and under clock control, successively
To the signal needed for each second module transfer, wherein complete the number and second of the clock cycle needed for whole signal transmissions
The number of module is identical.
Wherein, there are data transmission relations with each second module for the first module, due to the first module and each second mould
Block is all the function module in nand flash memory chip, so transmitting the digit of signal between the first module and each second module is
It is thick-and-thin.Every piece is latched for example, the first module is data, the second module is programming drive module, nand flash memory chip work
It is fixed from data latch module to the signal programming drive module when making, so, setting is posted the second mould is in the block
Storage digit can be by the signal of data transmission determines between the first module in the module routine.
It should be noted that can be identical module between multiple second modules, it can also be different module, and
The embodiment of the present invention does not limit the quantity of the second module, gives 4 the second modules for convenience of description, in Fig. 2 as a kind of
Example.
When multiple second moulds register in the block constitutes shift register, can under the control of clock control signal,
The function of realizing shift register controls the shift register signal transmission that sends out the first module extremely by clock control signal
Corresponding second module.Wherein, in conjunction with Fig. 2, the signal that the first module is sent out is preferentially to send out the 4th the second module (right end
The second module) signal, followed by the signal of third the second module, followed by the signal of second the second module, most
The signal of first the second module afterwards, in this way, shift register can under control of the clock signal will transmission signal according to
It is secondary to move to right, to be transmitted to corresponding second module successively.And in signal data transmission process, whole signal transmissions are completed
The number of required clock cycle is identical with the second number of modules, and this makes it possible to ensure the first module to each second mould
The signal that block is sent out can correctly be transmitted to corresponding second module, the phenomenon that avoiding the occurrence of error of transmission.
Preferably, when signal number all same of first module to each second module transfer, in each second module
Register digit and the signal number all same.
As shown in Fig. 2, equally as an example, the digit of signal received by each second module is signal 1- letters
Number n is n total, thus a n-bit register can be arranged in each second inside modules.It should be noted that each second
Signal 1- signals n between module can be identical signal, can also be different signal, the application does not do any limit
It is fixed.
The benefit that register is arranged in each second module is can to believe to each second module transfer to avoid the first module
Number when, be required for configuration with transmission signal respective numbers cabling, improve the utilization rate of domain.
The embodiment of the present invention is in the block by the second mould by the first module signal multiple to each second module transfer
Register constitutes shift register, and under the control of the clock signal of shift register, the multiple signal is transmitted respectively
To the multiple second module, the connecting line quantity solved in the prior art because of intermodule is more, influences chip area utilization
The problem of rate, has achieved the effect that improve chip area utilization rate.
Embodiment two
Fig. 3 is nand flash memory chip domain arrangement schematic diagram provided by Embodiment 2 of the present invention, in above-mentioned technical proposal
On the basis of, carry out further optimization.
When the first module is differed to the signal number of each second module transfer, each second mould register in the block
Digit it is identical, and the digit is identical as the signal number needed for the largest number of second modules of desired signal.
Illustratively, the signal digit that multiple second modules receive the first module can be different, can also be
Part is identical.As shown in figure 3, first the second module (the second module of left end) receives the first module in normal work
Signal be signal 1- signals a, a total, second receives the first module with a second module of third in normal work
Signal is signal 1- signals b, and b total, the 4th the second module (the second module of right end) receives first in normal work
The signal of module is signal 1- signals c, c total.
In the present embodiment, if a>b>The register of identical digit can be then arranged in c in each second module, and
Shift register is constituted under the control of clock control signal.Wherein, each second mould register digit in the block can be a,
It is i.e. identical as the signal number needed for the largest number of second modules of desired signal, to ensure the normal work of shift register
Make.
The present embodiment on the basis of the above embodiments, solves multiple second modules being connected with same first module
In, respectively receive signal difference in the case of, be each second module configuration register when, only with reference in multiple second modules with
First module carries out the most signal of signal transmission digit, and can ensure signal in this way stablizes transmission, and is being every
When a second module configuration register, configuration register is carried out to each second module using identical production technology, is realized
The production technology for simplifying nand flash memory chip, convenient for the advantageous effect of batch production and configuration.
Embodiment three
Fig. 4 is the nand flash memory chip domain arrangement schematic diagram that the embodiment of the present invention three provides, in above-mentioned technical proposal
On the basis of, carry out further optimization.
When the first module is differed to the signal number of each second module transfer, each second mould register in the block
Digit it is identical, and the digit is identical as the signal number needed for the largest number of second modules of desired signal.
Illustratively, as shown in figure 4, multiple second modules need the signal number for receiving the first module different,
The signal that first the second module receives the first module in normal work is signal 1- signals a, a total, second and the
The signal that three the second modules receive the first module in normal work is signal 1- signals b, b total, the 4th the second mould
The signal that block receives the first module in normal work is signal 1- signals c, c total.
In the present embodiment, if a>b>C, then can for the second module according to the signal digit of transmission from more to few suitable
Sequence is ranked up, and being linked in sequence from the near to the distant with the first module, and the digit of each second mould register in the block with
Signal number needed for the second module of place is identical.As shown in figure 4, with the first module it is nearest be desired signal number be a
Then second module is the second module that desired signal number is b and desired signal number is c successively, wherein due to required letter
Number number is there are two the second modules of b, then the sequence of the two the second modules can be configured as needed, it can't
Influence the normal transmission to signal data of shift register.The benefit being arranged in this way is：According to the operation principle of register,
The signal of first module transfer is moved to right by a bit registers to b bit registers successively, then is moved to right to b and deposited by b bit registers
Device is finally moved to right by b bit registers to c bit registers, thus can be higher than proximal end to avoid because of the register digit of distal end,
And lead to the spilling of signal digit, can not normal transmission signal the problem of.Illustratively, as in Fig. 4, first the second module
When (the second module of left end) and the signal digit of the first module transfer are 16, then 16 bit registers are configured for it,
When second and third the second module (two intermediate the second modules) and the signal digit of the first module transfer are 8, then
It is respectively that two the second modules configure eight bit registers for its configuration, the 4th the second module (the second module of right end) and the
When the signal digit of one module transfer is 4, then 4 bit registers are configured for it, setting can be according to each second in this way
The digit of signal transmission between module and the first module configures the register of corresponding digit for it, has saved the occupancy of register
Area, and saved cost.
The present embodiment solves multiple second modules and receives signal different problems on the basis of the various embodiments described above,
While improving domain utilization rate, the digit that signal can also be received according to each second module is configured corresponding digit
Register, and ensure that the stability of signal transmission according to sorting to it, while having saved cost.
Note that above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiments described here, can carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out to the present invention by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
May include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (4)
1. a kind of nand flash memory chip, the chip includes the first module and multiple second modules, and the first module is to each second
The multiple signals of module transfer, which is characterized in that
Include register in each second module, multiple second mould registers in the block connect into shift register, the first mould
Block is connected to the input terminal of the shift register, for passing through the shift register, and under clock control, successively to every
Signal needed for a second module transfer, wherein complete the number and the second module of the clock cycle needed for whole signal transmissions
Number it is identical.
2. chip according to claim 1, which is characterized in that
When signal number all same of first module to each second module transfer, the position of each second mould register in the block
Number and the signal number all same.
3. chip according to claim 1, which is characterized in that
When the first module is differed to the signal number of each second module transfer, the position of each second mould register in the block
Number is identical, and the digit is identical as the signal number needed for the largest number of second modules of desired signal.
4. chip according to claim 1, which is characterized in that
When the first module is differed to the signal number of each second module transfer, according to the signal number needed for the second module
The second module, and each second mould register in the block are arranged from the near to the distant from more to few sequence, and with the first module
Digit and each second module respectively required signal number is identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710212610.1A CN108665930A (en) | 2017-04-01 | 2017-04-01 | A kind of nand flash memory chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710212610.1A CN108665930A (en) | 2017-04-01 | 2017-04-01 | A kind of nand flash memory chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108665930A true CN108665930A (en) | 2018-10-16 |
Family
ID=63784253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710212610.1A Pending CN108665930A (en) | 2017-04-01 | 2017-04-01 | A kind of nand flash memory chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108665930A (en) |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4630241A (en) * | 1982-12-28 | 1986-12-16 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of programming for programmable circuit in redundancy circuit system |
| US5566323A (en) * | 1988-12-20 | 1996-10-15 | Bull Cp8 | Data processing system including programming voltage inhibitor for an electrically erasable reprogrammable nonvolatile memory |
| US20010003418A1 (en) * | 1999-12-09 | 2001-06-14 | Shin Fujita | Electro-optical device, clock signal adjusting method and circuit therefor, producing method therefor, and electronic equipment |
| US6437768B1 (en) * | 1997-04-23 | 2002-08-20 | Sharp Kabushiki Kaisha | Data signal line driving circuit and image display apparatus |
| JP2004152482A (en) * | 2003-11-20 | 2004-05-27 | Sharp Corp | Shift register and image display device |
| US20060171501A1 (en) * | 2005-01-28 | 2006-08-03 | Samsung Electronics Co., Ltd. | Shift register having low power consumption and method of operation thereof |
| CN1866403A (en) * | 2005-05-20 | 2006-11-22 | 株式会社半导体能源研究所 | Semiconductor circuit, display device, and electronic appliance therewith |
| CN1941174A (en) * | 2005-09-28 | 2007-04-04 | 海力士半导体有限公司 | Multi-port memory device |
| US20080074936A1 (en) * | 2006-09-21 | 2008-03-27 | Hynix Semiconductor Inc. | Read operation of multi-port memory device |
| CN101165759A (en) * | 2001-08-29 | 2008-04-23 | 日本电气株式会社 | Semiconductor device for driving current load device and current load device equipped with the same |
| CN101207384A (en) * | 2006-12-18 | 2008-06-25 | 财团法人工业技术研究院 | Analog-to-digital converting system |
| US20140168044A1 (en) * | 2012-12-14 | 2014-06-19 | Hefei Boe Optoelectronics Technology Co., Ltd. | Shift register unit, gate driving circuit and display device |
| US20150248867A1 (en) * | 2013-06-26 | 2015-09-03 | Boe Technology Group Co., Ltd. | Shift register unit, gate driving circuit and display device |
| US20160133211A1 (en) * | 2014-11-07 | 2016-05-12 | Boe Technology Group Co., Ltd. | Shift register unit, gate drive circuit, and display device |
| CN206672642U (en) * | 2017-04-01 | 2017-11-24 | 北京兆易创新科技股份有限公司 | A kind of nand flash memory chip |
-
2017
- 2017-04-01 CN CN201710212610.1A patent/CN108665930A/en active Pending
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4630241A (en) * | 1982-12-28 | 1986-12-16 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of programming for programmable circuit in redundancy circuit system |
| US5566323A (en) * | 1988-12-20 | 1996-10-15 | Bull Cp8 | Data processing system including programming voltage inhibitor for an electrically erasable reprogrammable nonvolatile memory |
| US6437768B1 (en) * | 1997-04-23 | 2002-08-20 | Sharp Kabushiki Kaisha | Data signal line driving circuit and image display apparatus |
| US20010003418A1 (en) * | 1999-12-09 | 2001-06-14 | Shin Fujita | Electro-optical device, clock signal adjusting method and circuit therefor, producing method therefor, and electronic equipment |
| CN101165759A (en) * | 2001-08-29 | 2008-04-23 | 日本电气株式会社 | Semiconductor device for driving current load device and current load device equipped with the same |
| JP2004152482A (en) * | 2003-11-20 | 2004-05-27 | Sharp Corp | Shift register and image display device |
| US20060171501A1 (en) * | 2005-01-28 | 2006-08-03 | Samsung Electronics Co., Ltd. | Shift register having low power consumption and method of operation thereof |
| CN1866403A (en) * | 2005-05-20 | 2006-11-22 | 株式会社半导体能源研究所 | Semiconductor circuit, display device, and electronic appliance therewith |
| CN1941174A (en) * | 2005-09-28 | 2007-04-04 | 海力士半导体有限公司 | Multi-port memory device |
| US20080074936A1 (en) * | 2006-09-21 | 2008-03-27 | Hynix Semiconductor Inc. | Read operation of multi-port memory device |
| CN101207384A (en) * | 2006-12-18 | 2008-06-25 | 财团法人工业技术研究院 | Analog-to-digital converting system |
| US20140168044A1 (en) * | 2012-12-14 | 2014-06-19 | Hefei Boe Optoelectronics Technology Co., Ltd. | Shift register unit, gate driving circuit and display device |
| US20150248867A1 (en) * | 2013-06-26 | 2015-09-03 | Boe Technology Group Co., Ltd. | Shift register unit, gate driving circuit and display device |
| US20160133211A1 (en) * | 2014-11-07 | 2016-05-12 | Boe Technology Group Co., Ltd. | Shift register unit, gate drive circuit, and display device |
| CN206672642U (en) * | 2017-04-01 | 2017-11-24 | 北京兆易创新科技股份有限公司 | A kind of nand flash memory chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107274921B (en) | Method and circuit for self-training reference voltage and memory system | |
| US10642769B2 (en) | Serial peripheral interface daisy chain mode system and apparatus | |
| CN104424154A (en) | Universal Spi (serial Peripheral Interface) | |
| CN103559863B (en) | LED lamp panel and LED display screen | |
| JPH0678019A (en) | Interface device | |
| US11637903B2 (en) | Memory device with a multi-mode communication mechanism | |
| US20180225060A1 (en) | Memory system | |
| US8321649B2 (en) | Memory controller address and data pin multiplexing | |
| CN109165176B (en) | Amplitude-phase control chip and bus type data transmission assembly | |
| CN105391442B (en) | Routing network for programmable logic device | |
| CN206672642U (en) | A kind of nand flash memory chip | |
| CN108665930A (en) | A kind of nand flash memory chip | |
| CN100461134C (en) | Controller of external storing device and address change method based on same | |
| US7551514B2 (en) | Semiconductor memory utilizing a method of coding data | |
| CN104050121A (en) | Double-receiving double-emitting programmable ARINC 429 communication interface chip | |
| US7519742B2 (en) | Asynchronous serial data apparatus for transferring data between one transmitter and a plurality of shift registers, avoiding skew during transmission | |
| CN107220424A (en) | A kind of isometric system and method for adjust automatically high speed wire harness based on Cadence skill | |
| EP0506060A1 (en) | Bidirectional programmable I/O driver | |
| CN101303894A (en) | Shift register and shift register apparatus | |
| CN109884516B (en) | Asynchronous reset trigger verification circuit and integrated circuit verification device | |
| CN203535933U (en) | LED lamp plate | |
| US20220164141A1 (en) | Memory Controller Utilizing Sets of Access Settings Corresponding to Memory Dies, and Control Method thereof | |
| US6442097B2 (en) | Virtual channel DRAM | |
| JP2014149669A (en) | Semiconductor memory device | |
| CN101145769A (en) | Calibration circuit for resistance component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Applicant after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Applicant before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
|
| CB02 | Change of applicant information |