CN104050121A - Double-receiving double-emitting programmable ARINC 429 communication interface chip - Google Patents

Abstract

The invention provides a double-receiving double-emitting programmable ARINC 429 communication interface chip, and aims to provide a double-receiving double-emitting HT 429 communication chip which is fast in data transmission, stable and reliable in work and higher in universality. The technical scheme of the invention is that a controller CPU (Central Processing Unit) performs data communication with the HT 429 interface chip through a bothway tristate data bus and a three-bit address bus, and the controller CPU carries out read and write operation on a transmitting controller, a receiving control register, a bumper occupancy state register, a work state register and four data registers of a communication interface unit in the HT 429 chip through the address bus and the data bus; the HT 429 chip carries out odd-even check and volume label check on received data, and data in accordance with requirements are input into an ARINC 429 received data storage; the CPU carries out write operation on two ARINC 429 transmitting data storage FIFO through the communication interface unit of the HT 429 chip respectively, data emitting of two channels is finished, data receiving of the two channels is finished by reading the FIFO data, and the double-receiving double-emitting HT 429 communication chip is formed.

Description

The two programmable A RINC429 communication interface chips of sending out of two receipts

Technical field

The present invention relates to a kind of a large amount of a kind of ARINC429 interface chips that use in aeroengine electronic controller that are mainly applicable to, the communication chip able to programme particularly with multiple communication speed, can realize the two pair ARINC429 Communication specific IC of receiving of ARINC429.

Background technology

Along with the development of digital technology and the appearance of microcomputer, increasing avionic device has adopted aeronautical data bus to carry out communication.Wherein ARINC429 has become the aircraft industry standard of avionics system communication regulation as a kind of digital carrier system.ARINC429 defines avionic device and system and a kind of standard of intercommunication mutually each other, is in 1977, within 09 month, to deliver and obtain the technical standard of use by ARINC (U.S. radiotelegraphy company).ARINC429 is used a kind of one-way data transmission standard.ARINC429 technical standard is described as " open loop " transfer mode by aviation bus.This type bus is described as single work bus of supporting multiple collector.In a bus, can only have a transmitter, transmitter is always in transmitted signal state: or send 32 words, or spacing wave.And a bus has a receiver at least, can there be at most 20.In ARINC429 bus, be a pair of unidirectional, differential coupling, twisted-pair shielded wire.Signal voltage range on every line is+5V is between-5V.Article one, line is called A (or+), and another line is called B (or-).Pattern on circuit is bipolarity return-to-zero code.In existing product, ARINC429 circuit form is differed from one another, on interface, have based on PCI, ISA, PC/104 and VXI, that plate borne processor has is MCS-51, Intel80196, Intel80386, FPGA etc., and function is various, use complexity, also certainly will cause data communication board expensive.Although adopt the design of FPGA field programmable gate array can simplify hardware design, development difficulty is large, the cycle is long.ARINC429 is a kind of one-way fashion broadcast type number bus, and the medium of transmission is comprised of twisted-pair feeder, and essence belongs to serial communication category.System is defined on a pair of transmission line, do not allow bi-directional transfer of data information, modulation system adopts bipolar return-to-zero system (BPRZ) tri-state coding mode, process secondary differential driving when data send, prime V+, V-is Transistor-Transistor Logic level, ARINC429 normal transmission voltage is within the scope of 10 ± 1V, and have generating positive and negative voltage minute, signal level range can characterize 3 states, logical one level voltage 7.25:11V (between A B), logical zero level voltage-7.25:-11V (between AB), dummy status level voltage-0.5:0.5V (between AB), when transmitting data continuously, between every 32 words, at least inserting a dummy status isolates, bus data transmission sequence is 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 ... 32.ARINC429 bus interface card major function is to play function served as bridge between ARINC429 bus and pci bus, realizes reception and the transmission of 429 bus data information.At present commercially available ARINC429 interface chip transmitter and ARINC429 Bus Interface Chip special chip based on FPGA is two single-shot special chips of receiving mostly, single reception frequency acquisition, send FIFO storer and only have 8 32 words, do not receive FIFO, do not receive data tag and filter audit function.For meeting two two communication needs of sending out of receiving, aviation ARINC429 communication generally adopts FPGA, DSP and high speed submersible processor etc. to realize at present, and these implementations need software and hardware technology comparatively complicated, and power consumption is larger, and versatility is poor.

Summary of the invention

The object of the invention is the weak point existing for prior art, provide a kind of data transmission fast, working stability is reliable, can reduce and use ARINC429 communication chip and peripheral circuit, alleviating programming requires and difficulty, there is larger versatility, especially can realize the two HT429 Communication specific ICs of receiving two of ARINC429 for engine electronic control system device.

Above-mentioned purpose of the present invention can reach by following measures.A kind of two two programmable A RINC429 communication interface chips of sending out of receiving, include two communications interface units that carry out communication with controller CPU, it is characterized in that: two ARINC429 receiving elements in parallel are converted to parallel data by the serial data receiving, the data that each receiving cable received by parity check sum volume label check unit are carried out parity check sum volume label check, undesirable data are abandoned, satisfactory data input ARINC429 receives data memory FIFO, controller CPU reads by the communications interface unit of HT429 chip the data that receive data memory FIFO, the communications interface unit of HT429 chip is to there being the data space of 8 addresses, this communications interface unit be connected with three bit address line AD1～AD3, the two-way three-state data bus D0～D15 of controller CPU transmission of control signals, response signal and reset RST clock, controller CPU carries out read-write operation to the transmit control register of HT429 chip communication interface unit, reception control register, buffer zone seizure condition register and duty register, completes initialization setting and status poll to HT429 chip, controller CPU carries out write operation to two ARINC429 transmission data memory FIFO respectively by the communications interface unit of HT429 chip, completes to the data of two sendaisles and sends, the communications interface unit of controller CPU by HT429 chip reads 1 of HT429 chip internal and receives the data receiver that data memory FIFO data complete two passages, so just forms two HT429 communication chips of receiving two.

The present invention has following beneficial effect than prior art.

HT429 chip of the present invention is to meet two two ARINC429 interface chips of sending out of receiving completely, is encapsulated as JLCC44, and Applicable temperature scope is-55 ℃-125 ℃, and operating voltage range is 4.5V-5.5V.By this chip, can realize duplex data communication with outside two devices simultaneously, use chip of the present invention to reduce and use ARINC429 communication chip and peripheral circuit, reduce the work load of controller CPU.

The data that the present invention receives each receiving cable are carried out parity check sum volume label check, undesirable data will be abandoned, satisfactory data enter receive data buffer FIFO, so just greatly alleviate controller CPU communications interface unit burden, alleviated requirement and the difficulty of programming.

The present invention adopts the memory buffer FIFO that transmits and receive data with larger capacity, and engine electronic control system device CPU can disposable transmission of short time or received the data of a plurality of words, and remaining task just completes transmission or reception task automatically by HT429 chip.HT429 chip has that when communication sends data, to take the controller CPU time short thus, has the larger slack time to wait for that controller CPU processes while receiving data, can be because CPU task be heavy obliterated data.

HT429 chip of the present invention can arrange arbitrarily and send or receive communication speed communication, each channel communications speed of this chip can be set to arbitrarily one of tri-kinds of 1M, 100K, 12.5K, two sendaisle communication speeds of two transmitting elements can be inconsistent, and chip of the present invention like this can be realized flexibly from the device of two different communication speeds and carry out duplex signaling.

HT429 chip of the present invention is the ARINC429 communication chip with control able to programme, and three bit address lines of this chip form the address space of 8 16 bit data.Electronic controller CPU carries out read-write operation to chip address space can be completed two passages and transmit and receive data, can read and write in addition and receive label data, transmit control register, reception control register, buffer zone seizure condition register, duty register etc., function that can flexible configuration chip to the operation of these registers, makes this chip have larger versatility.

This chip initiation arranges and is simply easy to programming, takies cpu resource less during work.Through a large amount of real works, observe, this chip operation is reliable and stable, is applicable to air communications field completely.

HT429 interface chip of the present invention perfect in shape and function, excellent performance,, flexible and convenient to use, control simple and reliablely, can convenient communicate with various CPU.By being easy to chip setting to the setting of inner control register, the programming of CPU communications interface unit is required to simply, there is no complicated calculating and setting.The peripheral circuit that uses this chip is also fairly simple, and peripheral components is few, and pin package is suitable, arranges that pcb board is easier to.HT429 operating voltage is in 5V left and right, and chip power-consumption is lower, does not occur fever phenomenon, and chip antijamming capability is strong, has no any fault at present, for aviation field mechanics of communication provides the selection that reliability is higher in work.

Accompanying drawing explanation

Below in conjunction with drawings and Examples, the present invention is further described.

Fig. 1 is that two receipts of the present invention twoly sends out communication interface chip HT429 circuit theory schematic diagram able to programme.

Fig. 2 is the schematic diagram of HT429 chip communication interface unit in Fig. 1.

Fig. 3 is the waveform schematic diagram that in Fig. 1, HT429 chip received and sent communication data.

Fig. 4 is HT429 chip and pin schematic diagram thereof.

Embodiment

Twoly in Fig. 1 receive that two to send out communication interface chip HT429 able to programme be the ARINC429 communication chip with control able to programme.HT429 chip internal has two receiving elements, two transmitting elements, a parity check sum volume label check unit, a communications interface unit, 64 * 16bit label data cell, 32 * 32 reception data FIFO, two 16 * 32bit to send data FIFO.Controller CPU carries out data communication by the communications interface unit of two-way three-state data bus D0～D15 and three bit address line AD1～AD3 and HT429 chip, HT429 chip has the data space of 8 addresses, controller CPU by three bit address lines, 16 BDB Bi-directional Data Bus and control bus to the transmit control register of HT429 chip, receive control register, buffer zone seizure condition register and duty register and carry out that read-write operation completes initialization setting and state reads; Two receiving elements of HT429 chip are converted to parallel data by the serial data of reception, then the data that by the parity check sum volume label check unit of HT429 chip, each receiving cable received are carried out parity check sum volume label check, undesirable data are abandoned, satisfactory data are input to the reception data memory FIFO of HT429 chip, and the communications interface unit of controller CPU by HT429 chip carries out read operation and complete reception data receiving data memory FIFO; Controller CPU carries out write operation by the communications interface unit of HT429 chip to two ARINC429 transmission data memory FIFO in parallel, two transmitting elements of HT429 chip send to external drive chip from the parallel series of two transmission data buffer FIFO reading out datas respectively, complete data and send, thereby form two two HT429 communication chips of sending out of receiving.

HT429 chip has two independently receiving elements, and outside three level datas are converted to COMS digital signal level by chips such as other similar HI-8588.HT429 chip receiving element constantly carries out level detection to input signal pin, when finding that there is data, judge whether data pulse duration and interval meet the requirements, the data that meet the requirements are just carried out shifting processing, when receiving 32 bit data, judge whether to receive, whether meet the requirements with next 32 word spaces, the data that only have the data bit duration, data bit interval, reception figure place, word interval all meet just enter HT429 label and parity checking.

HT429 chip communicates by its communications interface unit and controller CPU, and two receiving elements are converted to parallel data by the serial data of reception, send receive data buffer FIFO after parity check sum volume label check; Two transmitting elements send to external drive chip from the parallel series of two transmission data buffer FIFO reading out datas respectively.Controller CPU reads the data of receive data buffer FIFO by the read operation of the data register 1 to HT429 chip and data register 2, thereby complete, receives reading of data; Controller CPU writes data to two transmission buffer FIFO by the data register 1 to HT429 chip to the write operation of data register 4, thereby complete, sends writing of data.

What in the HT429 interface chip communications interface unit shown in Fig. 2, register address was 0 is transmit control register, address be 1 be to receive control register, address be 2 be that data buffer FIFO takies situation register, address is 3 to be state warning information registers, address is 4 to be data registers 1, address be 5 be data register 2, what address was 6 is data register 3, what address was 7 is data register 4.AD1～AD3 be three from three bit address lines of controller CPU, D0～D15 is the two-way three-state data bus that interface chip is communicated by letter with controller CPU while carrying out data communication.CS is for selecting control signal from the sheet of controller CPU.

Controller CPU carries out read-write operation by HT429 communications interface unit to transmit control register, reception control register, buffer zone seizure condition register and duty register.The data that HT429 chip parity check sum label detecting unit receives two receiving cables are carried out parity check sum volume label check, and undesirable data are abandoned, and satisfactory data input receives data memory FIFO.Controller CPU reads by data register 1 and the data register 2 of the communications interface unit of HT429 chip the data that receive data memory FIFO.The controller CPU also data register 1～data register 4 of the communications interface unit by HT429 chip writes data to respectively two and sends data data memory FIFO, two transmitting elements are from sending data FIFO reading out data and sending by turn 32 bit data of each word according to waveform format shown in Fig. 3, thereby form two two HT429 communication chips of sending out of receiving.

The sequential that controller CPU writes data to chip by HT429 chip communication interface unit is: first controller CPU is dealt into data in 16 bit data bus, after a clock, controller CPU uprises output enable signal OE, then then after two clocks, address AD 1～AD3 data are dealt in address wire simultaneously, controller CPU read-write RW is set to low level, chip selection signal CS is set to low level, then HT429 chip reads the data on D0～D15 data bus, after HT429 interface chip complete operation, answer signal DSACK is set to low level, after 1～2 clock, controller CPU is set to high level by chip selection signal CS, HT429 chip is set to high level by answer signal DSACK simultaneously, after 1～2 clock, controller CPU sets high level by read-write RW, cancel AD1～AD3 address, enable signal OE signal step-down level, cancel the data in 16 bit data bus, so just complete controller CPU and by communications interface unit, write data to the process of HT429 chip.

Sequential from HT429 chip reading out data to controller CPU, controller CPU is put into three bit address line AD1～AD3 by the address signal that reads HT429 chip data, chip selection signal CS and enable signal OE set low level simultaneously, read-write RW sets high level, then HT429 chip internal starts to process the communicating requirement of controller CPU, correct data are put on D0～D15 data bus, and chip DSACK is set to low level, when detecting the negative edge of answer signal DSACK of HT429 chip output, controller CPU just starts the data on readout data bus, generally after answer signal DSACK negative edge, 1～2 clock controller CPU reading out data is complete, then controller CPU sets high level by CS and enable signal OE, HT429 chip sets high level by answer signal DSACK simultaneously, after a clock, controller CPU sets low level by read-write RW, cancel the operation address on address bus, so just completed controller CPU by communications interface unit the process from HT429 chip reading out data.

When the initialization of HT429 chip, first controller CPU takies the buffer zone of HT429 chip in situation register is 0x0000, after carrying out this instruction, reset HT429 chip internal is received and is sent buffer zone, the pointer of HT429 chip internal read-write label data is reset to 0, then HT429 chip transmit control register is set is 0x0010 to controller CPU, and then writing successively volume label check data to the data register 1 of HT429 chip communication interface unit, last data writing 0xff00 represents that writing volume label checks ED.Label data are write after interface chip, and then controller CPU arranges HT429 chip buffer zone, and to take situation register be 0x0000, then controller CPU arranges the configuration data of transmit control register and reception control register, has so just completed the initialization setting of HT429 chip.

When completing to HT429 chip transmit control register with after receiving the arranging of control register, controller CPU just can start to send communication data to peripheral control unit.Controller CPU first reads the data that HT429 chip buffer zone takies situation register before sending every group of data, and judgement sending and receiving buffer data is how many; Then the data of controller CPU read work status register, judge whether it has warning information, when its read work status data is 0x0000, representative is without any warning information, then controller CPU is write data 0x0000 to state alarm register, the state warning information that resets all.

When controller CPU is reported data to HT429 chip sendaisle 1, first write low 16 bit data to HT429 chip data register 1, then write high 16 bit data to data register 2, complete like this and write one and complete 32 words to HT429 chip sendaisle 1, repeat above operation control CPU and just can send a plurality of 32 digital data to HT429 chip sendaisle 1.When same controller CPU is reported data to HT429 chip sendaisle 2, first write low 16 bit data to HT429 chip data register 3, then write high 16 bit data to data register 4, controller CPU completes and writes one and complete 32 words to HT429 chip sendaisle 2 like this, repeats above operation and just can send a plurality of 32 digital data and arrive HT429 chip sendaisle 2.The data that controller CPU writes HT429 chip are not do parity checking, data are sent into after HT429 chip, when sending data, interface chip has all been done parity checking automatically, and then HT429 chip sends to outside similar HI-8585 communication according to form shown in Fig. 3 waveform by data and drives chip.

During controller CPU received communication data, first read and judge that HT429 chip internal buffer zone takies situation register, high 7 of this register data shows to receive in FIFO have how many data, then controller CPU reads the data that HT429 internal work status register is preserved, and data writing 0x0000 is to HT429 chip operation state storage, empties the warning information of duty register.Controller CPU according to HT429 chip buffer zone take situation register show data number read reception buffer zone data.When receiving data, automatically done HT429 chip parity check and the data check of volume label, the underproof data of every parity check sum label data check are all abandoned, and the underproof corresponding warning information of parity check sum volume label check can show in state alarm register.

The reception data of HT429 chip receiving cable 1 and receiving cable 2 are delivered to respectively HT429 chip internal parity check sum volume label check unit, data through passed examination have all been delivered to same reception data FIFO, when controller CPU reads HT429 chip received communication data, first read low 16 bit data of HT429 chip data register 1, then high 16 bit data of read data register 2, controller CPU completes and reads complete 32 words like this, repeats above operation control CPU and just can read a plurality of 32 word received communication data.

For guaranteeing that CPU communications interface unit control program has time enough to process other task, HT429 interface chip has larger data buffer, the size of receive data buffer FIFO is 32 words, the size that each passage sends data buffer FIFO is 16 words, and the RAM that preserves label data is 64 16bit words.

Consult shown in Fig. 4, HT429 chip has 4 input pins, 4 output pins, its input-output wave shape as shown in Figure 3, input pin IN1A, IN1B, IN2A, IN2B are from chips such as peripheral ARINC429 receiving integrate circuit HT-8588, and output pin OUT1A, OUT1B, OUT2A, OUT2B are for outputing to the chips such as peripheral ARINC429 drive integrated circult HI-8585.HT429 chip has 16 bi-directional data pin D0～D15,3 bit address pin AD1～AD3, a sheet selects input pin CS, a read-write input pin RW, an output enable input pin OE, a 10M clock input pin CLK, an operation completes replys output pin DSACK, an interrupt response output pin IRQ.Sheet shows while selecting input pin CS to be low level that controller CPU chooses this interface chip, and HT429 chip and controller CPU just have exchanges data, and when HT429 chip is idle, sheet selects pin CS in high level state, and chip D0～D15 is externally high-impedance state.RST is reseting input signal, HT429 chip reset when it is low level.RW is the read-write from controller CPU, when it is data writing during for low level, during for high level, is reading out data.OE is output enable signal, and when enable signal OE is high level, ARINC429 interface chip receives D0～D15 data of controller CPU, and when enable signal OE is low level, HT429 chip output data to data bus D0～D15 is to controller CPU.DSACK is that HT429 chip completes the signal of exporting to CPU after controller CPU operates accordingly, represents that HT429 chip operation completes.DSACK pin is high level usually, after CS chooses interface chip, and interface chip built-in function completes, is set to low level, once controller CPU detects its negative edge, just carries out lower step work.DSACK pulse width is generally 1 10MHZ clock period, if controller CPU is checked through this signal, will does not wait and stay always, can not carry out next-step operation.10MCLK is the work clock signal of HT429 chip, and its frequency is 10MHZ.

Above-described is only the preferred embodiments of the present invention.It should be pointed out that for the person of ordinary skill of the art, under the premise without departing from the principles of the invention, can also make some distortion and improvement, these changes and change should be considered as belonging to protection scope of the present invention.

Claims (10)

1. two receipts pair are sent out programmable A RINC429 communication interface chips, include two communications interface units that carry out communication with controller CPU, it is characterized in that: two ARINC429 receiving elements in parallel are converted to parallel data by the serial data receiving, the data that each receiving cable received by parity check sum volume label check unit are carried out parity check sum volume label check, undesirable data are abandoned, satisfactory data input ARINC429 receives data memory FIFO, controller CPU reads by the communications interface unit of HT429 chip the data that receive data memory FIFO, the communications interface unit of HT429 chip is to there being the data space of 8 addresses, this communications interface unit be connected with three bit address line AD1～AD3, the two-way three-state data bus D0～D15 of controller CPU transmission of control signals, response signal and reset RST clock, controller CPU carries out read-write operation to the transmit control register of HT429 chip communication interface unit, reception control register, buffer zone seizure condition register and duty register, completes initialization setting and status poll to HT429 chip, controller CPU carries out write operation to two ARINC429 transmission data memory FIFO respectively by the communications interface unit of HT429 chip, completes to the data of two sendaisles and sends, the communications interface unit of controller CPU by HT429 chip reads 1 of HT429 chip internal and receives the data receiver that data memory FIFO data complete two passages, so just forms two HT429 communication chips of receiving two.

2. two two programmable A RINC429 communication interface chips of sending out of receiving as claimed in claim 1, is characterized in that: HT429 chip has two independently receiving elements, and outside three level datas are converted to COMS digital signal level by other similar HI-8588 chip; HT429 chip receiving element constantly carries out level detection to input signal pin, when finding that there is data, judge whether data pulse duration and interval meet the requirements, the data that meet the requirements are just carried out shifting processing, when receiving 32 bit data, judge whether to receive, whether meet the requirements with next 32 word spaces, the data that only have the data bit duration, data bit interval, reception figure place, word interval all meet just enter HT429 label and parity check unit.

3. two two programmable A RINC429 communication interface chip HT429 of sending out that receive as claimed in claim 1, is characterized in that: three bit address lines form the address space of 8 16 bit data.

4. two receipts pair as claimed in claim 1 are sent out programmable A RINC429 communication interface chip HT429, it is characterized in that: controller CPU sends to data in 16 bit data bus, after a clock, controller CPU uprises enable signal OE output enable signal, then after two clocks, controller CPU is dealt into address AD 1～AD3 data in address wire simultaneously, controller CPU read-write RW is set to low level, sheet selects control signal CS to be set to low level, HT429 chip internal operates, after complete operation, chip DSACK is set to low level, after 1～2 clock, controller CPU is set to high level by chip selection signal CS, HT429 chip is set to high level by its DSACK simultaneously, after 1～2 clock, controller CPU sets high level by read-write RW again, cancel AD1～AD3 address, enable signal OE signal step-down level, cancel the data in 16 bit data bus, so just complete the process that controller CPU writes data to HT429 chip.

5.

Two two programmable A RINC429 communication interface chip HT429 of sending out that receive as claimed in claim 1, it is characterized in that: controller CPU is put into three bit address line AD1～AD3 by reading address signal, CS and enable signal OE set low level simultaneously, read-write RW sets high level, then HT429 chip internal starts to process the requirement of controller CPU, correct data are put on data bus, DSACK is set to low level simultaneously, when controller CPU detects the negative edge of DSACK of HT429 chip, start the data on readout data bus, after a clock, controller CPU sets high level by CS and enable signal OE, HT429 chip is set to high level by its DSACK simultaneously, after a clock, CPU communications interface unit sets low level by read-write RW, cancel the operation address on address bus, so just complete the process that controller CPU reads HT429 chip data.

6. two receipts pair as claimed in claim 1 are sent out programmable A RINC429 communication interface chip HT429, it is characterized in that: in the initialization procedure of interface chip, during initialization HT429 chip, first controller CPU arranges the data that HT429 chip communication interface unit buffer zone takies situation register is 0x0000, its inner reception and transmission buffer zone resets, read-write label pointer is reset to 0, the data that then transmit control register is set are 0x0010, then write successively volume label check data to HT429 chip data register 1, last data writing 0xff00 represents that writing volume label checks ED.

7. two receipts pair as claimed in claim 1 are sent out programmable A RINC429 communication interface chip HT429, it is characterized in that: controller CPU send or receive every group of data before first read the data that HT429 chip buffer zone takies situation register, judgement sending and receiving buffer data size, controller CPU just determines send or receive how many data according to this register data; Then controller CPU reads the data of HT429 chip operation status register again, whether interpretation it have warning information, and when its data that read are 0x0000, representative is without any warning information, then will write data 0x0000 to state alarm register, the state warning information that resets all.

8. two receipts pair as claimed in claim 1 are sent out programmable A RINC429 communication interface chip HT429, it is characterized in that: when controller CPU is reported data to HT429 chip sendaisle 1, first write low 16 bit data to HT429 interface chip data register 1, then write high 16 bit data to data register 2, complete and write one and complete 32 words to HT429 interface chip passage 1, repeat above operation and send a plurality of digital data and arrive HT429 chip sendaisle 1.

9. two receipts pair as claimed in claim 1 are sent out programmable A RINC429 communication interface chip HT429, it is characterized in that: when controller CPU is reported data to HT429 chip sendaisle 2, first write low 16 bit data to HT429 interface chip data register 3, then write high 16 bit data to data register 4, complete and write one and complete 32 words to HT429 interface chip passage 2, repeat above operation and send a plurality of digital data and arrive HT429 chip sendaisle 2.

10. two receipts pair as claimed in claim 1 are sent out programmable A RINC429 communication interface chips, it is characterized in that: when CPU communications interface unit receives data, first read and judge that HT429 chip buffer zone takies situation register, high 7 of these data show to receive in FIFO have how many data, then read the data of HT429 chip operation status register, data writing 0x0000, to state alarm register, empties the warning information of state alarm register; Controller CPU according to HT429 chip buffer zone take situation register show data number read reception buffer zone data; When receiving data, automatically done HT429 chip parity check and label data check, data through passed examination have all been delivered to the same reception data FIFO of HT429 chip internal, the underproof data of every parity check sum label data check are all abandoned, and the underproof corresponding warning information of parity check sum volume label check can show in state alarm register; Controller CPU reads low 16 bit data that first read HT429 chip data register 1 while receiving data, then high 16 bit data of read data register 2, controller CPU completes and reads complete 32 words like this, repeats the received communication data that above operation control CPU just can read a plurality of words.