CN109656856A - Multiplex bus and multiplex bus interconnect device and method are realized using FPGA - Google Patents
Multiplex bus and multiplex bus interconnect device and method are realized using FPGA Download PDFInfo
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- CN109656856A CN109656856A CN201811406543.8A CN201811406543A CN109656856A CN 109656856 A CN109656856 A CN 109656856A CN 201811406543 A CN201811406543 A CN 201811406543A CN 109656856 A CN109656856 A CN 109656856A
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- fpga
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
Abstract
Multiplex bus and multiplex bus interconnect device and method are realized using FPGA the present invention relates to a kind of, and technical characterstic is: including MCU processor, FPGA system and equipment；The FPGA system is connected with MCU processor and equipment respectively, MCU processor is for reading the data that equipment end is sent in FPGA system, and in the data write-in FPGA system for being sent to equipment end, FPGA system then generates the bus write address and read-write data of control signal control equipment end according to equipment end read-write sequence, and then realizes MCU processor to the read-write operation of equipment.The present invention can be realized seamless interfacing between MCU processor and external apparatus interface, realize the function of being similar to South Bridge chip in intel earlier chip group, FPGA flexibly configurable.
Description
Technical field
The invention belongs to the interconnection technique fields between bus, are related to multiplex bus and multiplex bus interconnect device, especially
It is a kind of interconnect device and method that multiplex bus and multiplex bus are realized using FPGA.
Background technique
With the continuous development of science and technology, embedded technology is grown rapidly.At the same time, it is transmitted between chip
The interface mode of data is also more and more, and the CPU of traditional X86, MIPS, MCU framework is multiplex bus (i.e. address sum number
According to independence), computer external interface chip part such as network, USB, serial ports, CAN etc. is that (address and data are multiple for multiplex bus
With).How fast and easy flexibly realizes that the interaction between two kinds of buses becomes problem to be solved.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, propose a kind of reasonable, the convenient and practical, fast and flexible of design
Realize multiplex bus and multiplex bus interconnect device and method using FPGA.
The present invention solves its realistic problem and adopts the following technical solutions to achieve:
It is a kind of to realize multiplex bus and multiplex bus interconnect device using FPGA, including MCU processor, FPGA system and
Equipment；The FPGA system is connected with MCU processor and equipment respectively, and MCU processor is sent to for reading equipment end
Data in FPGA system, and in the data write-in FPGA system for being sent to equipment end, FPGA system is then read according to equipment end
It writes timing and generates the bus write address and read-write data of control signal control equipment end, and then realize MCU processor to equipment
Read-write operation.
Moreover, the biography of data is carried out between the MCU processor and FPGA system using the GPMC bus of MCU processor
Defeated, data/address bus, address bus and the control bus that MCU processor is connected with FPGA have the low 12 bit address bus of MCU, low 8
Bit data bus, static memory chip selection signal and low level effectively, write enable signal and low level effectively, read enable signal and
Low level effectively, address valid signal and low level effectively, external interrupt signal and low level effectively and reset signal and low electricity
It is flat effective.
Moreover, 8 BITBUS network address dates, piece that the signal wire that the FPGA system is connected with equipment has data address to be multiplexed
Select signal, read signal, write signal, address latch signal, fpga_ interrupt signal and reset signal.
A kind of interconnected method for realizing multiplex bus and multiplex bus using FPGA, including read cycle method and write cycle time
Method two parts；The read cycle method, comprising the following steps:
Step 1 by MCU provides address by multiplex bus first, provides chip selection signal, reads enable signal and address and have
Imitate signal；
Step 2, FPGA system end program are by state machine, so that the reading timing that multiplex bus timing meets equipment is wanted
It asks, realizes when each reading enable signal failing edge comes, the 8bit data on equipment end data address multiplex bus are sent
To the data port at MCU processor end；
Step 3, when equipment receives data and receives buffer full, interrupt pin can generate low level interruptions and believe
Number, as long as FPGA receives low level interrupt signal, interruption is sent to MCU processor, to trigger the outside of MCU processor
It interrupts, by reading function in the reception buffer of reading data to MCU in the interrupt service routine of MCU processor, thus
Data are read；
The write cycle time method, comprising the following steps:
Step 1 by MCU provides address by multiplex bus first, provides chip selection signal, write enable signal and address and have
Imitate signal；
Step 2, FPGA system end program are by state machine, so that the timing of writing that multiplex bus timing meets equipment is wanted
It asks, realizes when each write enable signal failing edge comes, the 8bit data write-in in the data port at MCU processor end
In FPGA internal register, data are then sent to the multiplexing of equipment end data address always from FPGA internal register when write condition meets
On line, thus the transmission buffer of write device.
The advantages of the present invention:
The present invention uses FPGA as the interface between MCU processor and equipment, and MCU processor end asynchronous read and write timing is adopted
It is non-address/data multiplexer mode, and equipment end address/data is time-sharing multiplex.The control signal of processor passes through
FPGA internal logic generates the control signal that equipment needs, while meeting the read-write sequence requirement of equipment.The present invention utilizes FPGA
The interconnection for realizing multiplex bus and multiplex bus, i.e., realized seamless between MCU processor and external apparatus interface with FPGA
The function of being similar to South Bridge chip in intel earlier chip group, FPGA flexibly configurable are realized in docking.
Detailed description of the invention
Fig. 1 is hardware interface functional block diagram of the invention；
Fig. 2 is FPGA internal logic block diagram of the invention；
Fig. 3 is read-write sequence state transition figure inside FPGA of the invention.
Specific embodiment
The embodiment of the present invention is described in further detail below in conjunction with attached drawing:
It is a kind of to realize multiplex bus and multiplex bus interconnect device using FPGA, as shown in Figure 1, include MCU processor,
FPGA system and equipment；The FPGA system is connected with MCU processor and equipment respectively, and MCU processor is for reading equipment
The data being sent in FPGA system are held, and in the data write-in FPGA system for being sent to equipment end；FPGA system then basis
Equipment end read-write sequence generates the bus write address of control signal (read/write signal, address latch signal) control equipment end and reads
Data are write, and then realize that MCU processor to the read-write operation of equipment, is finally reached MCU processor and passes through equipment communication with the outside world
Purpose.
In the present embodiment, it is counted between the MCU processor and FPGA system using the GPMC bus of MCU processor
According to transmission, data/address bus, address bus and the control bus that MCU processor is connected with FPGA have low 12 bit address of MCU total
The address line gpmc_ [11:0], least-significant byte data/address bus gpmc_ data [7:0], static memory chip selection signal (choosing of gpmc_ piece) and
Low level is effective, write enable signal (gpmc_ writes enabled) and low level are effective, reads enable signal (gpmc_ reads enabled) and low electricity
It is flat effectively, address valid signal (address gpmc_ is effective) and low level effectively, external interrupt signal and low level effectively and reset
Signal and low level is effective.
8 BITBUS networks that the signal wire that in the present embodiment, the FPGA system is connected with equipment has data address to be multiplexed
Location data [7:0], chip selection signal [3:0], read signal, write signal, address latch signal, fpga_ interrupt signal and reset signal.
The logic diagram realized inside FPGA is as shown in Figure 2.The address signal gpmc_ [11:0] be it is unidirectional, by interface control
No matter logic module input address processed, control signal relevant to equipment read-write, read and write, it is necessary to first output address.Signal
Gpmc_ data [7:0] two-way circulate, and address date [7:0] signal is address/data time-sharing multiplex.Module for reading and writing
It is made of dual port interface, inputs, exports design separately.Module for reading and writing when being connected with interface control logic interface module,
The data of output and the data of input are also designed and are separated.The open signal of general module for reading and writing is with read/write selection signal also by connecing
Mouth control logic provides.Main logic control program uses the form of three-stage state machine inside FPGA, and state transition figure is such as
Shown in Fig. 3, FPGA controls equipment end read-write operation by state machine, realizes non-address in GPMC interface and equipment end communication process
Matching and conversion between data-reusing bus and address date multiplex bus.Whole cycle includes bus free S0, address lock
(S1 and S2) is deposited, data (S3_R and S4_R) is read and writes 6 states of data (S3_W and S4_W), FPGA is the core of this system,
It controls each letter of different read-write states by state machine according to GPMC bus read-write sequence and equipment end read-write sequence
Number, to realize MCU processor to the Read-write Catrol of equipment end bus.
A kind of interconnected method for realizing multiplex bus and multiplex bus using FPGA, including read cycle method and write cycle time
Method two parts；
By taking the read cycle as an example, comprising the following steps:
Step 1 by MCU provides address by multiplex bus first, provides chip selection signal, reads enable signal and address and have
Imitate signal；
Step 2, FPGA system end program are by state machine, so that the reading timing that multiplex bus timing meets equipment is wanted
It asks, realizes when each reading enable signal (gpmc_ reads enabled) failing edge comes, equipment end data address multiplex bus
8bit data on (data address [7:0]) are sent to the port data (gpmc_ data [7:0]) at MCU processor end；
Step 3, when equipment receives data and receives buffer full, interrupt pin can generate low level interruptions and believe
Number, as long as FPGA receives low level interrupt signal, interruption is sent to MCU processor, to trigger the outside of MCU processor
It interrupts, by reading function in the reception buffer of reading data to MCU in the interrupt service routine of MCU processor, thus
Data are read；
Equally by taking write cycle time as an example, comprising the following steps:
Step 1 by MCU provides address by multiplex bus first, provides chip selection signal, write enable signal and address and have
Imitate signal；
Step 2, FPGA system end program are by state machine, so that the timing of writing that multiplex bus timing meets equipment is wanted
It asks, realizes data (the gpmc_ number at MCU processor end when each write enable signal (gpmc_ writes enabled) failing edge comes
According to [7:0]) in 8bit data write-in FPGA internal register on port, when write condition satisfaction then posts data inside FPGA
Storage is sent on equipment end data address multiplex bus (data address [7:0]), thus the transmission buffer of write device.
It is emphasized that embodiment of the present invention be it is illustrative, without being restrictive, therefore the present invention includes
It is not limited to embodiment described in specific embodiment, it is all to be obtained according to the technique and scheme of the present invention by those skilled in the art
Other embodiments, also belong to the scope of protection of the invention.
Claims (4)
1. a kind of realize multiplex bus and multiplex bus interconnect device using FPGA, it is characterised in that: including MCU processor,
FPGA system and equipment；The FPGA system is connected with MCU processor and equipment respectively, and MCU processor is for reading equipment
Hold the data that are sent in FPGA system, and in the data write-in FPGA system for being sent to equipment end, FPGA system then basis
Equipment end read-write sequence generates the bus write address and read-write data of control signal control equipment end, and then realizes MCU processor
To the read-write operation of equipment.
2. a kind of utilization FPGA according to claim 1 realizes multiplex bus and multiplex bus interconnect device, feature
It is: carries out the transmission of data, MCU processing between the MCU processor and FPGA system using the GPMC bus of MCU processor
Data/address bus, address bus and the control bus that device is connected with FPGA have the low 12 bit address bus of MCU, least-significant byte data/address bus,
Static memory chip selection signal and low level effectively, write enable signal and low level effectively, read enable signal and low level effectively,
Address valid signal and low level effectively, external interrupt signal and low level effectively and reset signal and low level it is effective.
3. a kind of utilization FPGA according to claim 1 realizes multiplex bus and multiplex bus interconnect device, feature
Be: the signal wire that the FPGA system is connected with equipment have data address be multiplexed 8 BITBUS network address dates, chip selection signal,
Read signal, write signal, address latch signal, fpga_ interrupt signal and reset signal.
4. a kind of described in any one of -3 claims according to claim 1 realize multiplex bus and multiplex bus using FPGA
Interconnected method, it is characterised in that: including read cycle method and write cycle time method two parts；The read cycle method, including with
Lower step:
Step 1 by MCU provides address by multiplex bus first, provides chip selection signal, reads enable signal and address and effectively believe
Number；
Step 2, FPGA system end program are by state machine, so that multiplex bus timing meets the reading timing requirements of equipment, it is real
When present each reading enable signal failing edge comes, the 8bit data on equipment end data address multiplex bus are sent to MCU
The data port at processor end；
Step 3, when equipment receive data and receive buffer full when, interrupt pin can generate low level interrupt signal,
As long as FPGA receives low level interrupt signal, interruption is sent to MCU processor, to trigger in the outside of MCU processor
It is disconnected, by reading function by the reception buffer of reading data to MCU, thus number in the interrupt service routine of MCU processor
According to being read；
The write cycle time method, comprising the following steps:
Step 1 by MCU provides address by multiplex bus first, provides chip selection signal, write enable signal and address and effectively believe
Number；
Step 2, FPGA system end program are by state machine, so that multiplex bus timing meets the timing requirements of writing of equipment, it is real
When present each write enable signal failing edge comes, in the 8bit data write-in FPGA in the data port at MCU processor end
In portion's register, then data are sent on equipment end data address multiplex bus from FPGA internal register when write condition meets,
To the transmission buffer of write device.
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Cited By (4)
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| CN110362521A (en) * | 2019-06-30 | 2019-10-22 | 中国船舶重工集团公司第七一六研究所 | The two-way serial data communication system and method for MCU+FPGA framework |
| CN111914498A (en) * | 2020-05-07 | 2020-11-10 | 电子科技大学 | Time division multiplexing ADIO hardware implementation method of MCU external chip |
| CN113885100A (en) * | 2021-09-28 | 2022-01-04 | 中国船舶重工集团公司第七0七研究所 | Gravity gradiometer platform mass self-gradient compensation method |
| CN115905100A (en) * | 2022-12-27 | 2023-04-04 | 南方电网调峰调频发电有限公司检修试验分公司 | Method and device for realizing data interaction between excitation system and FPGA (field programmable Gate array) by loongson 2K1000 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110362521A (en) * | 2019-06-30 | 2019-10-22 | 中国船舶重工集团公司第七一六研究所 | The two-way serial data communication system and method for MCU+FPGA framework |
| CN110362521B (en) * | 2019-06-30 | 2022-11-18 | 中国船舶重工集团公司第七一六研究所 | MCU + FPGA architecture two-way serial data communication system and method |
| CN111914498A (en) * | 2020-05-07 | 2020-11-10 | 电子科技大学 | Time division multiplexing ADIO hardware implementation method of MCU external chip |
| CN113885100A (en) * | 2021-09-28 | 2022-01-04 | 中国船舶重工集团公司第七0七研究所 | Gravity gradiometer platform mass self-gradient compensation method |
| CN115905100A (en) * | 2022-12-27 | 2023-04-04 | 南方电网调峰调频发电有限公司检修试验分公司 | Method and device for realizing data interaction between excitation system and FPGA (field programmable Gate array) by loongson 2K1000 |
| CN115905100B (en) * | 2022-12-27 | 2023-08-18 | 南方电网调峰调频发电有限公司检修试验分公司 | Method and device for realizing interaction of excitation system and FPGA data by Loongson 2K1000 processor |
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