CN110362521A - The two-way serial data communication system and method for MCU+FPGA framework - Google Patents
The two-way serial data communication system and method for MCU+FPGA framework Download PDFInfo
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- CN110362521A CN110362521A CN201910581913.XA CN201910581913A CN110362521A CN 110362521 A CN110362521 A CN 110362521A CN 201910581913 A CN201910581913 A CN 201910581913A CN 110362521 A CN110362521 A CN 110362521A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
Abstract
The present invention provides a kind of two-way serial data communication systems based on MCU+FPGA framework, including MCU, FPGA, the first serial communication peripheral hardware and the second serial communication peripheral hardware；Data communication is wherein carried out between MCU and FPGA by way of parallel bus, signal between the two includes clock CLK, resets RESETn, chip selection signal CSn, read signal XRDn, write signal XWEn, 7 bit address bus ADDRESS [6:0] and 16 bit data bus DATA [15:0], carries out data communication between FPGA and the first communications peripheral and the second communications peripheral by way of universal serial bus.
Description
Technical field
The present invention relates to a kind of electric technical field of data transmission, especially a kind of two-way based on MCU+FPGA framework is serial
Data communication system and method.
Background technique
FPGA (Field-Programmable GateArray, i.e. field programmable gate array), inside include configurable
Logic module CLB (Configurable Logic Block), input/output module IOB (Input Output Block) and interior
Three parts of portion's line (Interconnect) have the characteristics that the design cycle is most short, development cost are minimum, least risk,
The fields such as the high-speed interface circuit design of communication equipment, Digital Signal Processing are widely used.In many applications,
FPGA requires to be combined design and application with MCU (Micro Controller Unit, micro-control unit), and MCU is chiefly used in
System flow control is run with special algorithm, and FPGA can be used for extending support peripheral hardware, such as serial peripheral.Parallel data communication tool
Have the characteristics that efficiency of transmission is high, therefore is commonly applied to data communication between FPGA and MCU.
In some applications, the combined control system for needing MCU+FPGA this kind of supports difference under different application scene
Serial peripheral, if the software program by modifying MCU and FPGA is needed to be adapted to the different peripheral hardware of communication protocol, nothing every time
Doubting will increase workload and process is cumbersome.
Summary of the invention
The purpose of the present invention is to provide a kind of two-way serial data communication systems and method based on MCU+FPGA framework.
Realize the first technical solution of the object of the invention are as follows: a kind of two-way serial data based on MCU+FPGA framework is logical
Letter system, including MCU, FPGA, the first serial communication peripheral hardware and the second serial communication peripheral hardware；Wherein pass through between MCU and FPGA
The form of parallel bus carries out data communication, signal between the two include clock CLK, reset RESETn, chip selection signal CSn,
Read signal XRDn, write signal XWEn, 7 bit address bus ADDRESS [6:0] and 16 bit data bus DATA [15:0], FPGA with
Data communication is carried out between first communications peripheral and the second communications peripheral by way of universal serial bus.
Using above system, in the one end MCU, file main.c is stated and is determined in principal function main () initialization of variable part
Adopted variable Flag_firstIn is used to indicate whether to first enter or call function GetDevice (), statement and definition pointer
Variable Initial, the pointer are directed toward the address space where peripheral hardware FPGA, and giving initial value is variables D eviceType, effect
To initialize and selecting currently valid serial communication peripheral hardware to number, defined function GetDevice () realize MCU and FPGA it
Between parallel data communication.
Tri-state gate is set using above system, before every serial commu-nication peripheral hardware and file module is arranged in rear end
SerialCom；Two-way serial communication system data flow is described as follows with port mapping, and wherein device1 is the first serial communication
Peripheral hardware, Device2 are the second serial communication peripheral hardware:
(1) data/address bus DATA value by tri-state gate K1 is transmitted to signal device1_ when device_type=1
The port device1_dataIn port mapping of dataIn, signal device1_dataIn and module Device1；Module
Device1 receives and judges the value of port device1_dataIn, and corresponding director data is stored in signal tx1_buffer, and
It is sent to the signal sout1 port mapping of port sout1, port sout1 and file module SerialCom；Module SerialCom
Signal sout1 and port sout port mapping, and peripheral hardware is sent for module Device1 director data by port sout
system；
(2) when device_type=1, signal sin1 and port the sin port mapping of module SerialCom, and signal
The port sin1 port mapping of sin1 and module Device1, SerialCom module receive peripheral hardware system's by port sin
Data；The data of peripheral hardware system are stored in signal rx1_buffer, port device1_ by module Device1 port sin1
DataOut and the signal device1_dataOut of SerialCom module carry out port mapping；Signal device1_dataOut is logical
It crosses tri-state gate k1 and the data of peripheral hardware system is transmitted to data/address bus DATA；
(3) when device_type=2, data/address bus DATA value is transmitted to signal device2_ by tri-state gate K2
The port device2_dataIn port mapping of dataIn, signal device2_dataIn and module Device2；Module
Device2 receives and judges the value of port device2_dataIn, and corresponding director data is stored in signal tx2_buffer, and
It is sent to the signal sout2 port mapping of port sout2, port sout2 and file module SerialCom；Module SerialCom
Signal sout2 and port sout port mapping, and peripheral hardware is sent for module Device2 director data by port sout
system；
(4) when device_type=2, signal sin2 and port the sin port mapping of module SerialCom, and signal
The port sin2 port mapping of sin2 and module Device2, SerialCom module receive peripheral hardware system's by port sin
Data；The data of peripheral hardware system are stored in signal rx2_buffer, port device2_ by module Device2 port sin2
DataOut and the signal device2_dataOut of SerialCom module carry out port mapping；Signal device2_dataOut is logical
It crosses tri-state gate k2 and the data of peripheral hardware system is transmitted to data/address bus DATA.
Realize second of technical solution of the object of the invention are as follows: a kind of data communication of system according to claim 1
Method, the first serial communication peripheral hardware are sent to peripheral hardware by process Process11 and process Process12 and are instructed, and process is passed through
Process13 and process Process14 receives peripheral data；Wherein
(1) the execution process of process Process11 are as follows:
A1 has detected whether clock CLK rising edge event, i.e. rising_edge (CLK), if it is, in order successively
Execute step B1, C1, D1；
B1 judges whether device1_dataIn is 1, if it is, assigning director data cmd1 to signal tx1_
Buffe, and 1 is set by Status Flag tx1_rdy is sent, then execute step D1；If it is not, then successively executing step in order
C1,D1；
C1 judges whether device1_dataIn is 2, if it is, assigning director data cmd2 to signal tx1_
Buffer, and 1 is set by Status Flag tx1_rdy is sent, then execute step D1；If not, thening follow the steps D1；
D1 judges whether signal tx1_rdy is 1, if it is, signal tx1_rdy is set 0；
(2) the execution process of process Process12 are as follows:
A2 has detected whether clock CLK rising edge event, if so, thening follow the steps B2.
B2 has detected whether signal tx1_rdy rising edge event, if it is, the data of signal tx1_buffer are sent out
It is sent to port sout1；
(3) the execution process of process Process13 are as follows:
A3 has detected whether clock CLK rising edge event, i.e. rising_edge (CLK), if it is, in order successively
Execute step B3, C3.
B3 has detected whether data frame receipt initial signal start failing edge event, if it is, by port sin1's
Data receiver sets 1 to signal rx1_buffer, and by signal rx1_rdy, then executes step (3)；If not, thening follow the steps
C3。
C3 judges whether signal rx1_rdy is 1, if it is, signal rx1_rdy is set 0；
(4) the execution process of process Process14 are as follows:
A4 has detected whether clock CLK rising edge event, if so, thening follow the steps B4；
B4 has detected whether signal rx1_rdy rising edge event, if it is, the data of signal rx1_buffer are sent
To port device1_dataOut；
Second serial communication peripheral hardware is sent to peripheral hardware by process Process21 and process Process22 and is instructed, by into
Journey Process23 and process Process24 receives peripheral data；Wherein
(5) the execution process of process Process21 are as follows:
A5 has detected whether clock CLK rising edge event, if it is, successively executing step B5, C5, D5 in order.
B5 judges whether device2_dataIn is 1, if it is, assigning director data cmd3 to signal tx2_
Buffer, and 1 is set by Status Flag tx2_rdy is sent, then execute step D5；If it is not, then successively executing step in order
C5、D5。
C5 judges whether device2_dataIn is 2, if it is, assigning director data cmd4 to signal tx2_
Buffer, and 1 is set by Status Flag tx2_rdy is sent, then execute step D5；If not, thening follow the steps D5；
D5 judges whether signal tx2_rdy is 1, if it is, signal tx2_rdy is set 0；
(6) the execution process of process Process22 are as follows:
A6 has detected whether clock CLK rising edge event, if so, thening follow the steps B6.
B6 has detected whether signal tx2_rdy rising edge event, if it is, the data of signal tx2_buffer are sent out
It is sent to port sout2.
(7) the execution process of process Process23 are as follows:
A7 has detected whether clock CLK rising edge event, i.e. rising_edge (CLK), if it is, in order successively
Execute step B7, C7.
B7 has detected whether data frame receipt initial signal start failing edge event, if it is, by port sin2's
Data receiver sets 1 to signal rx2_buffer, and by signal rx2_rdy, then executes step C7；If not, thening follow the steps
C7。
C7 judges whether signal rx2_rdy is 1, if it is, signal rx2_rdy is set 0.
(8) the execution process of process Process24 are as follows:
A8 has detected whether clock CLK rising edge event, if so, thening follow the steps B8.
B8 has detected whether signal rx2_rdy rising edge event, if it is, the data of signal rx2_buffer are sent
To port device2_dataOut.
The present invention is convenient to select and configure serial peripheral number, eliminates through modification software program and is adapted to peripheral hardware
The workload of agreement.Software architecture of the invention is clear, data flow is clear, is easy to extend and supports more peripheral hardwares.
The invention will be further described with reference to the accompanying drawings of the specification.
Detailed description of the invention
Fig. 1 is two-way serial communication system electrical connection diagram.
Fig. 2 is reference data frame format schematic diagram.
Fig. 3 is that MCU director data receives and dispatches mechanism schematic diagram.
Fig. 4 is 1 schematic diagram of FPGA serial communication peripheral module.
Fig. 5 is 2 schematic diagram of FPGA serial communication peripheral module.
Fig. 6 is FPGA data transmitting-receiving and serial peripheral port mapping schematic diagram.
Fig. 7 is two-way serial communication system data flow and port mapping schematic diagram.
Specific embodiment
As shown in Figure 1, circuit system of the present invention includes micro-control unit MCU, FPGA, the first serial peripheral
Device1 and the second serial peripheral Device2.Wherein between micro-control unit MCU and FPGA by way of parallel bus into
Row data communication, signal between the two include clock CLK, reset RESETn, chip selection signal CSn, read signal XRDn, write letter
Number XWEn, 7 bit address bus ADDRESS [6:0] and 16 bit data bus DATA [15:0].FPGA and the first serial peripheral
Data communication is carried out between Device1 and the second serial peripheral Device2 by way of universal serial bus, receives data RD
It indicates, send data is indicated with TD.
As shown in Figure 2, it is assumed that the serial communication data frame format in the present invention is 18bit/Frame, including 1 starting
Position Start code, 3 Sink code, 2 Frame code, 3 Device address, 5 Command code, 3
A CRC code and 1 stop position Stop code.
As shown in figure 3, in the one end micro-control unit MCU, file main.c lists the partial content of principal function main ()
And implementation.It is stated in initialization of variable part and defines unit type variable Flag_firstIn, initial value 0, the variable
Effect be indicate whether to first enter or calling function GetDevice ().Statement and definition pointer variable Initial, should
Pointer is directed toward the address space where peripheral hardware FPGA, and giving initial value is variables D eviceType, acts on to initialize and selecting
Currently valid serial communication peripheral hardware number, i.e. setting FPGA are communicated with serial peripheral Device1 or serial peripheral Device2
Communication.
The setting of variables D eviceType can be realized by system man-machine interaction unit (such as key+liquid crystal display), herein not
The contents of the section is described.
Defined function GetDevice (), return Value Types are void, parameter void.It is assumed that defined pointer becomes before this
DeviceAddress is measured, which is directed toward the address space where peripheral hardware FPGA, and variable Cmd is the number that MCU is sent to FPGA
According to request instruction.It is assumed that defined pointer variable Devicedata, the pointer are directed toward the address space where peripheral hardware FPGA before this,
Variable R eadData is used to save the data in peripheral hardware FPGA address Devicedata.
The execution process of function GetDevice () are as follows:
(1) data requesting instructions Cmd is sent to peripheral hardware FPGA address DeviceAddress；
(2) judge whether to enter for the first time or call function GetDevice (), if it is, by Status Flag Flag_
FirstIn sets 1 and exits function GetDevice ()；If it is not, then reading peripheral hardware FPGA address Devicedata and protecting
It is stored to variable R eadData.
As shown in figure 4, peripheral module Device1 includes process Process1, process Process2, process Process3
And process Process4, it is clock CLK event-driven, what process Process1 and process Process2 processing peripheral hardware instructed
It sends, the reception of process Process3 and process Process4 processing peripheral data.
The execution process of process Process1 are as follows:
(1) clock CLK rising edge event, i.e. rising_edge (CLK), if it is, in order successively have been detected whether
Execute step (2), (3), (4).
(2) judge whether device1_dataIn is 1, if it is, assigning director data cmd1 to signal tx1_
Buffer (tx1_buffer≤cmd1), and 1 (tx1_rdy≤' 1 ') is set by Status Flag tx1_rdy is sent, then execute
Step (4)；If it is not, then successively executing step (3), (4) in order.
(3) judge whether device1_dataIn is 2, if it is, assigning director data cmd2 to signal tx1_
Buffer (tx1_buffer≤cmd2), and 1 (tx1_rdy≤' 1 ') is set by Status Flag tx1_rdy is sent, then execute
Step (4)；If not, thening follow the steps (4).
(4) judge whether signal tx1_rdy is 1, if it is, signal tx1_rdy is set 0, i.e. tx1_rdy≤' 0 '.
The execution process of process Process2 are as follows:
(1) clock CLK rising edge event, i.e. rising_edge (CLK), if so, thening follow the steps have been detected whether
(2)。
(2) signal tx1_rdy rising edge event, i.e. rising_edge (tx1_rdy), if it is, will have been detected whether
The data of signal tx1_buffer are sent to port sout1.
The execution process of process Process3 are as follows:
(1) clock CLK rising edge event, i.e. rising_edge (CLK), if it is, in order successively have been detected whether
Execute step (2), (3).
(2) detected whether data frame receipt initial signal start failing edge event, i.e. falling_edge (start),
If it is, by the data receiver of port sin1 to signal rx1_buffer (rx1_buffer≤sin1), and by signal rx1_
Rdy sets 1 (rx1_rdy≤' 1 '), then executes step (3)；If not, thening follow the steps (3).
(3) judge whether signal rx1_rdy is 1, if it is, signal rx1_rdy is set 0, i.e. rx1_rdy≤' 0 '.
The execution process of process Process4 are as follows:
(1) clock CLK rising edge event, i.e. rising_edge (CLK), if so, thening follow the steps have been detected whether
(2)。
(2) signal rx1_rdy rising edge event, i.e. rising_edge (rx1_rdy), if it is, will have been detected whether
The data of signal rx1_buffer are sent to port device1_dataOut.
As shown in figure 5, peripheral module Device2 includes process Process1, process Process2, process Process3
And process Process4, it is clock CLK event-driven, what process Process1 and process Process2 processing peripheral hardware instructed
It sends, the reception of process Process3 and process Process4 processing peripheral data.
The execution process of process Process1 are as follows:
(1) clock CLK rising edge event, i.e. rising_edge (CLK), if it is, in order successively have been detected whether
Execute step (2), (3), (4).
(2) judge whether device2_dataIn is 1, if it is, assigning director data cmd3 to signal tx2_
Buffer (tx2_buffer≤cmd3), and 1 (tx2_rdy≤' 1 ') is set by Status Flag tx2_rdy is sent, then execute
Step (4)；If it is not, then successively executing step (3), (4) in order.
(3) judge whether device2_dataIn is 2, if it is, assigning director data cmd4 to signal tx2_
Buffer (tx2_buffer≤cmd4), and 1 (tx2_rdy≤' 1 ') is set by Status Flag tx2_rdy is sent, then execute
Step (4)；If not, thening follow the steps (4).
(4) judge whether signal tx2_rdy is 1, if it is, signal tx2_rdy is set 0, i.e. tx2_rdy≤' 0 '.
The execution process of process Process2 are as follows:
(1) clock CLK rising edge event, i.e. rising_edge (CLK), if so, thening follow the steps have been detected whether
(2)。
(2) signal tx2_rdy rising edge event, i.e. rising_edge (tx2_rdy), if it is, will have been detected whether
The data of signal tx2_buffer are sent to port sout2.
The execution process of process Process3 are as follows:
(1) clock CLK rising edge event, i.e. rising_edge (CLK), if it is, in order successively have been detected whether
Execute step (2), (3).
(2) detected whether data frame receipt initial signal start failing edge event, i.e. falling_edge (start),
If it is, by the data receiver of port sin2 to signal rx2_buffer (rx2_buffer≤sin2), and by signal rx2_
Rdy sets 1 (rx2_rdy≤' 1 '), then executes step (3)；If not, thening follow the steps (3).
(3) judge whether signal rx2_rdy is 1, if it is, signal rx2_rdy is set 0, i.e. rx2_rdy≤' 0 '.
The execution process of process Process4 are as follows:
(1) clock CLK rising edge event, i.e. rising_edge (CLK), if so, thening follow the steps have been detected whether
(2)。
(2) signal rx2_rdy rising edge event, i.e. rising_edge (rx2_rdy), if it is, will have been detected whether
The data of signal rx2_buffer are sent to port device2_dataOut.
As shown in fig. 6, SerialCom.vhd be FPGA software in top document module, including process Process1,
Process Process2, process Process3, element Device1 and instantiation, element Device2 and instantiation.Wherein:
The driving event of process Process1 is chip selection signal CSn and write signal XWEn, executes process are as follows:
(1) whether detection chip selection signal CSn and write signal XWEn is low level, i.e. ' 0 ' AND XWEn=of CSn=simultaneously
' 0 ', step (2), (3), (4) are if it is successively executed in order；
(2) whether the value for judging address bus is variable Initial value, i.e. ADDRESS=Initial, if it is, will
The value of data/address bus assigns signal device_type (device_type≤DATA), and signal flag_type is set 1
(flag_type≤' 1 ') is then log out process Process1, if it is not, then successively executing step (3), (4) in order.
Signal device_type, which is used to indicate, currently to number with FPGA mapping with the serial peripheral communicated, the value of the signal
It can be 1 or 2, when signal value is 1, indicate that currently mapping and communicate with FPGA is peripheral hardware Device1；Conversely, signal value
When being 2, indicate that currently mapping and communicate with FPGA is peripheral hardware Device2.Whether signal flag_type be used to indicate currently
MCU setting selection current peripheral number instruction is received, indicates that receiving MCU setting selection peripheral hardware number refers to when flag_type is 1
It enables.
(3) whether the value for judging signal device_type is 1, if it is, assigning the value of data/address bus to signal
Device1_dataIn simultaneously exits process Process1, if not, thening follow the steps (4).
(4) whether the value for judging signal device_type is 2, if it is, assigning the value of data/address bus to signal
Device2_dataIn simultaneously exits process Process1.
The driving event of process Process2 is chip selection signal CSn and write signal XRDn, executes process are as follows:
(1) whether detection chip selection signal CSn and write signal XRDn is low level, i.e. ' 0 ' AND XRDn=of CSn=simultaneously
' 0 ', step (2), (3) are if it is successively executed in order.
(2) whether the value for judging signal device_type is 1, if it is, by the value of signal device1_dataOut
Data/address bus DATA is assigned, and exits process Process2, if not, thening follow the steps (3).
(3) whether the value for judging signal device_type is 2, if it is, by the value of signal device2_dataOut
Data/address bus DATA is assigned, and exits process Process2.
The driving event of process Process3 is status signal flag_type, executes process are as follows:
(1) flag_type rising edge event, i.e. rising_edge (flag_type), if so, then pressing have been detected whether
Sequence successively executes step (2), (3), (4).
(2) whether the value for judging signal device_type is 1, if it is, signal sout1 is mapped to port sout,
Signal sin1 is mapped to port sin, and executes step (4)；If not, thening follow the steps (3), (4).
(3) whether the value for judging signal device_type is 2, if it is, signal sout2 is mapped to port sout,
Signal sin2 is mapped to port sin, and executes step (4).
(4) signal flag_type is assigned 0, i.e. flag_type≤' 0 '.
Element Device1 and instantiation, port sin1 are mapped to the signal sin1 of SerialCom, port sout1 mapping
The signal device1_ of SerialCom is mapped to the signal sout1 of SerialCom, port device1_dataIn
DataIn, port device1_dataOut are mapped to the signal device1_dataOut of SerialCom, and port CLK is mapped to
The port CLK of SerialCom, port RESETn are mapped to the port RESETn of SerialCom.
Element Device2 and instantiation, port sin2 are mapped to the signal sin2 of SerialCom, port sout2 mapping
The signal device2_ of SerialCom is mapped to the signal sout2 of SerialCom, port device2_dataIn
DataIn, port device2_dataOut are mapped to the signal device2_dataOut of SerialCom, and port CLK is mapped to
The port CLK of SerialCom, port RESETn are mapped to the port RESETn of SerialCom.
As shown in fig. 7, being specifically described this Figure illustrates two-way serial communication system data flow of the present invention and port mapping
Are as follows:
When the value of signal device_type is equal to 1, i.e. device_type=1, tri-state gate k1 are in bidirectionally conductive shape
State, data/address bus DATA value are stored in signal device1_dataIn, the port of signal device1_dataIn and module Device1
Device1_dataIn carries out port mapping.Module Device1 receives and judges the value of port device1_dataIn, will be right
The director data deposit signal tx1_buffer answered, and it is sent to port sout1, port sout1 and top document module
The signal sout1 of SerialCom carries out port mapping.Due to device_type=1, the signal sout1 of module SerialCom
Port mapping is carried out with port sout, and peripheral hardware system is sent for Device1 director data by port sout.
In device_type=1, the signal sin1 and port sin of module SerialCom carries out port mapping, and
The port sin1 of signal sin1 and module Device1 carries out port mapping, and SerialCom module receives peripheral hardware by port sin
The data of system.The data of peripheral hardware system are stored in signal rx1_buffer, port by module Device1 port sin1
Device1_dataOut and the signal device1_dataOut of SerialCom module carry out port mapping.Signal device1_
The data of peripheral hardware system are transmitted to data/address bus DATA by tri-state gate k1 by dataOut.
When the value of signal device_type is equal to 2, i.e. device_type=2, tri-state gate k2 are in bidirectionally conductive shape
State, data/address bus DATA value are stored in signal device2_dataIn, the port of signal device2_dataIn and module Device2
Device2_dataIn carries out port mapping.Module Device2 receives and judges the value of port device2_dataIn, will be right
The director data deposit signal tx2_buffer answered, and it is sent to port sout2, port sout2 and top document module
The signal sout2 of SerialCom carries out port mapping.Due to device_type=2, the signal sout2 of module SerialCom
Port mapping is carried out with port sout, and peripheral hardware system is sent for Device2 director data by port sout.
In device_type=2, the signal sin2 and port sin of module SerialCom carries out port mapping, and
The port sin2 of signal sin2 and module Device2 carries out port mapping, and SerialCom module receives peripheral hardware by port sin
The data of system.The data of peripheral hardware system are stored in signal rx2_buffer, port by module Device2 port sin2
Device2_dataOut and the signal device2_dataOut of SerialCom module carry out port mapping.Signal device2_
The data of peripheral hardware system are transmitted to data/address bus DATA by tri-state gate k2 by dataOut.
Data flow clear and definite of the invention can extend according to this mechanism and support more peripheral hardware agreements.
Claims (4)
1. a kind of two-way serial data communication system based on MCU+FPGA framework, which is characterized in that including MCU, FPGA, first
Serial communication peripheral hardware and the second serial communication peripheral hardware；Wherein
Data communication is carried out between MCU and FPGA by way of parallel bus, signal between the two includes clock CLK, answers
Position RESETn, chip selection signal CSn, read signal XRDn, write signal XWEn, 7 bit address bus ADDRESS [6:0] and 16 data
Bus DATA [15:0],
Data communication is carried out between FPGA and the first communications peripheral and the second communications peripheral by way of universal serial bus.
2. system according to claim 1, which is characterized in that in the one end MCU,
File main.c is stated in principal function main () initialization of variable part and defined variable Flag_firstIn is used to indicate
It whether is to first enter or call function GetDevice (),
Statement and definition pointer variable Initial, the pointer are directed toward the address space where peripheral hardware FPGA, and giving initial value is to become
DeviceType is measured, is acted on to initialize and selecting currently valid serial communication peripheral hardware to number,
Defined function GetDevice () realizes the parallel data communication between MCU and FPGA.
3. system according to claim 1, which is characterized in that tri-state gate is arranged before every serial commu-nication peripheral hardware and rear end is set
Set file module SerialCom；Two-way serial communication system data flow is described as follows with port mapping, and wherein device1 is the
Serial commu-nication peripheral hardware, Device2 are the second serial communication peripheral hardware:
(1) data/address bus DATA value by tri-state gate K1 is transmitted to signal device1_dataIn when device_type=1, believes
The port device1_dataIn port mapping of number device1_dataIn and module Device1；Module Device1 is received and is sentenced
Corresponding director data is stored in signal tx1_buffer, and is sent to port by the value of interruptive port device1_dataIn
The signal sout1 port mapping of sout1, port sout1 and file module SerialCom；The signal of module SerialCom
Sout1 and port sout port mapping, and peripheral hardware system is sent for module Device1 director data by port sout；
(2) when device_type=1, signal sin1 and port the sin port mapping of module SerialCom, and signal sin1
With the port sin1 port mapping of module Device1, SerialCom module receives the data of peripheral hardware system by port sin；
The data of peripheral hardware system are stored in signal rx1_buffer by module Device1 port sin1, port device1_dataOut with
The signal device1_dataOut of SerialCom module carries out port mapping；Signal device1_dataOut passes through tri-state gate
The data of peripheral hardware system are transmitted to data/address bus DATA by k1；
(3) when device_type=2, data/address bus DATA value is transmitted to signal device2_dataIn by tri-state gate K2, letter
The port device2_dataIn port mapping of number device2_dataIn and module Device2；Module Device2 is received and is sentenced
Corresponding director data is stored in signal tx2_buffer, and is sent to port by the value of interruptive port device2_dataIn
The signal sout2 port mapping of sout2, port sout2 and file module SerialCom；The signal of module SerialCom
Sout2 and port sout port mapping, and peripheral hardware system is sent for module Device2 director data by port sout；
(4) when device_type=2, signal sin2 and port the sin port mapping of module SerialCom, and signal sin2
With the port sin2 port mapping of module Device2, SerialCom module receives the data of peripheral hardware system by port sin；
The data of peripheral hardware system are stored in signal rx2_buffer by module Device2 port sin2, port device2_dataOut with
The signal device2_dataOut of SerialCom module carries out port mapping；Signal device2_dataOut passes through tri-state gate
The data of peripheral hardware system are transmitted to data/address bus DATA by k2.
4. a kind of data communications method of system according to claim 1, which is characterized in that the first serial communication peripheral hardware passes through
Process Process11 and process Process12 sends to peripheral hardware and instructs, and is connect by process Process13 and process Process14
Receive peripheral data；Wherein
(1) the execution process of process Process11 are as follows:
A1 has detected whether clock CLK rising edge event, i.e. rising_edge (CLK), if it is, successively executing in order
Step B1, C1, D1；
B1 judges whether device1_dataIn is 1, if it is, assign director data cmd1 to signal tx1_buffe, and
Status Flag tx1_rdy will be sent and set 1, then execute step D1；If it is not, then successively executing step C1, D1 in order；
C1 judges whether device1_dataIn is 2, if it is, assign director data cmd2 to signal tx1_buffer, and
Status Flag tx1_rdy will be sent and set 1, then execute step D1；If not, thening follow the steps D1；
D1 judges whether signal tx1_rdy is 1, if it is, signal tx1_rdy is set 0；
(2) the execution process of process Process12 are as follows:
A2 has detected whether clock CLK rising edge event, if so, thening follow the steps B2.
B2 has detected whether signal tx1_rdy rising edge event, if it is, sending the data of signal tx1_buffer to
Port sout1；
(3) the execution process of process Process13 are as follows:
A3 has detected whether clock CLK rising edge event, i.e. rising_edge (CLK), if it is, successively executing in order
Step B3, C3.
B3 has detected whether data frame receipt initial signal start failing edge event, if it is, by the data of port sin1
Signal rx1_buffer is received, and signal rx1_rdy is set 1, then executes step (3)；If not, thening follow the steps C3.
C3 judges whether signal rx1_rdy is 1, if it is, signal rx1_rdy is set 0；
(4) the execution process of process Process14 are as follows:
A4 has detected whether clock CLK rising edge event, if so, thening follow the steps B4；
B4 has detected whether signal rx1_rdy rising edge event, if it is, sending end for the data of signal rx1_buffer
Mouth device1_dataOut；
Second serial communication peripheral hardware is sent to peripheral hardware by process Process21 and process Process22 and is instructed, and process is passed through
Process23 and process Process24 receives peripheral data；Wherein
(5) the execution process of process Process21 are as follows:
A5 has detected whether clock CLK rising edge event, if it is, successively executing step B5, C5, D5 in order.
B5 judges whether device2_dataIn is 1, if it is, assign director data cmd3 to signal tx2_buffer, and
Status Flag tx2_rdy will be sent and set 1, then execute step D5；If it is not, then successively executing step C5, D5 in order.
C5 judges whether device2_dataIn is 2, if it is, assign director data cmd4 to signal tx2_buffer, and
Status Flag tx2_rdy will be sent and set 1, then execute step D5；If not, thening follow the steps D5；
D5 judges whether signal tx2_rdy is 1, if it is, signal tx2_rdy is set 0；
(6) the execution process of process Process22 are as follows:
A6 has detected whether clock CLK rising edge event, if so, thening follow the steps B6.
B6 has detected whether signal tx2_rdy rising edge event, if it is, sending the data of signal tx2_buffer to
Port sout2.
(7) the execution process of process Process23 are as follows:
A7 has detected whether clock CLK rising edge event, i.e. rising_edge (CLK), if it is, successively executing in order
Step B7, C7.
B7 has detected whether data frame receipt initial signal start failing edge event, if it is, by the data of port sin2
Signal rx2_buffer is received, and signal rx2_rdy is set 1, then executes step C7；If not, thening follow the steps C7.
C7 judges whether signal rx2_rdy is 1, if it is, signal rx2_rdy is set 0.
(8) the execution process of process Process24 are as follows:
A8 has detected whether clock CLK rising edge event, if so, thening follow the steps B8.
B8 has detected whether signal rx2_rdy rising edge event, if it is, sending end for the data of signal rx2_buffer
Mouth device2_dataOut.
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