CN109857685A - A kind of implementation method of MPU and FPGA expanding multiple serial ports - Google Patents
A kind of implementation method of MPU and FPGA expanding multiple serial ports Download PDFInfo
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Abstract
The present invention relates to the implementation methods of a kind of MPU and FPGA expanding multiple serial ports, carry out the transmission and control of data using the dma controller inside MPU in the data transmission；In the side FPGA, when serial ports detects commencing signal, FPGA carries out frame decoding, storage to the data received by the parameter of the register in serial ports configuration module, after being stored in a frame byte, receives FIFO and adds timestamp after this frame data；When sending data, related serial ports carries out framing to the data sent in FIFO according to the parameter of the register in its corresponding serial ports configuration module, is then sent by serial ports；In the side MPU, the transmitting-receiving of serial data is controlled, MPU is addressed to operate by the related register address that every road serial ports that FPGA extends defines, and MPU is periodically polled operation to related serial ports by way of interrupt inquiry.The present invention has the advantages that efficiently accurate, reusability is strong, the lead time is short, at low cost；Product cost is also reduced simultaneously, enhances the ease for maintenance of product.
Description
Technical field
The invention belongs to on-site programmable gate array FPGA technical fields, and in particular to one kind realizes MPU based on DMA technology
With the method for FPGA expanding multiple serial ports.
Background technique
With the continuous development of electronics technology level, the cost performance of high performance integrated circuit is also constantly promoted, as FPGA
Field programmable gate array；The versatility that the companies such as Intel, AMD, Motorola, ARM provide is relatively good, processing capacity is relatively strong,
The update that the good embeded processor of scalability (being together simply referred to as MPU herein) product etc. accelerates electronic product is changed
Generation.
In multi-serial communication field, with the development of FPGA and MPU technology, the common serial ports expansion that largely uses before
The yield of chip is reduced year by year and price also improves year by year, and the later maintenance and cost to relevant design product bring not small
Trouble.
Just because of traditional multi-serial extension method there is a problem of maintenance and it is at high cost, followed by largely
The scheme that MPU is communicated with FPGA extended serial port.However, with the further development of present integrated circuit, a large amount of scheme before
It is no longer desirable for present processing chip, real-time is poor, drags the problems such as slow MPU working efficiency increasingly prominent.
Summary of the invention
In order to solve the above technical problems, the present invention provides and a kind of realizes MPU and FPGA expanding multiple serial ports based on DMA technology
A kind of method.DMA technology is the abbreviation of Direct Memory Access, means " direct memory access (DMA) ", it allows
The direct read/write data between external equipment and memory do not need CPU intervention.The present invention uses in MPU in the data transmission
Portion's dma controller carries out the transmission and control of data, and each serial ports of extension is completely independent, and each serial ports receives and dispatches ring in full duplex
It is independent of each other under border, the parameters such as every road serial port baud rate, even-odd check can be separately provided, required serial ports in real work
The problem of number can be configured in the light of actual conditions, and interrupt priority level is not present in the serial ports of configuration.Skill of the present invention
Art scheme is as follows:
A kind of implementation method of MPU and FPGA expanding multiple serial ports, FPGA and MPU are counted using 8 channel parallel data buses
Addressing operation is realized according to interaction, using 8 road address bus；A clock counter is arranged in the side FPGA to be used to add timestamp,
Per asynchronous serial port unit independent all the way include a data reception module, data transmission blocks, serial ports configuration module and
Baud rate generator, the data reception module include receiving FIFO, data receiver register, the data transmission blocks
Including sending FIFO, data transmitter register, the serial ports configuration module, which is provided with, joins for saving data transmission with control
Several registers carries out the transmission and control of data using the dma controller inside MPU in the data transmission；
When normal work, the receiving end FPGA detects commencing signal.In the side FPGA, when serial ports detects commencing signal,
FPGA carries out frame decoding, storage to the data received by the parameter of the register in serial ports configuration module, when one frame word of deposit
After section, receives FIFO and add timestamp after this frame data；When sending data, related serial ports configures mould according to its corresponding serial ports
The parameter of register in block carries out framing to the data sent in FIFO, is then sent by serial ports；
In the side MPU, the transmitting-receiving of serial data is controlled, the FPGA under is regarded as several cell fifos, MPU passes through FPGA
The related register address that every road serial ports of extension defines is addressed to operate, and MPU is periodically right by way of interrupt inquiry
Related serial ports is polled operation.
MPU and PFGA, using DMA technology, keeps running efficiency of system higher when carrying out related data transmitting-receiving transmission.
Beneficial effects of the present invention:
1) present invention realizes the Unify legislation of asynchronous serial communication, overcomes at conventional asynchronous serial data processing method
Device inefficient, lead time length, defect at high cost are managed, with efficiently accurate, reusability is strong, the lead time is short, at low cost
Advantage.
2) present invention realizes that FPGA extends by the DMA technology of MPU and in communication process in the way of increase timestamp etc.
Real-time, the efficient operation of serial ports, while product cost is also reduced, enhance the ease for maintenance of product.
Detailed description of the invention
Fig. 1 is system general frame block diagram of the invention；
Fig. 2 is the data transmission stream journey block diagram of the invention based on DMA technology.
Specific embodiment
With reference to the accompanying drawing, embodiments of the present invention are illustrated.FPGA in this implementation is using Xilinx (match spirit
Think) Spartan-6 series of products XC6SLX9, it can be connected by parallel bus and the data line of MPU processor, address wire
It connects, to achieve the purpose that extended serial port and meet users on diversity.
As shown in Figure 1, being system general frame block diagram of the invention.FPGA and MPU uses 8 channel parallel data buses
(DATE [0,7]) carries out data interaction, realizes addressing operation using 8 road address bus (ADDR [0,7])；Read enabled (RD:MPU
Read enabled label when data), write enabled (WR:MPU writes enabled label when data).
Reading and writing enable signal is the signal that a pair in the art is total to intellectual, they mainly indicate the read-write data shape of MPU
State, to control the read-write of data.For example, MPU will read data from serial equipment, then at this time MPU will piece phase selection pass set
Standby address, while must there is enabled read signal (being assumed to be low effective) data could be read come up, otherwise data are not read
Come.Write enable signal is similar.The application does not introduce such bus data reading and writing sequential control, therefore does not elaborate.
The present invention includes a data reception module, data hair per asynchronous serial port unit independent all the way in the side FPGA
Module, serial ports configuration module and Baud rate generator are sent, the data reception module is posted including reception FIFO, data receiver
Storage, the data transmission blocks include sending FIFO (data buffer area that FIFO refers to first in first out), data transmission deposit
Device carries out the transmission and control of data using the dma controller inside MPU in the data transmission.Receive FIFO and data receiver
Register electrical connection sends FIFO and is electrically connected with data transmitter register, and serial ports configuration module is electrically connected with Baud rate generator,
Serial ports configuration module and Baud rate generator are electrically connected with data reception module and data transmission blocks respectively.FPGA is set with serial ports
Connection is realized by TX, RX between standby.TX, RX are that the standard serial port of Transistor-Transistor Logic level sends data line, receives data line.
Data transmission blocks, the main MPU that completes send the caching of data and the framing of data and are sent to serial equipment；
Data reception module, main completion receives data from serial equipment and frame decoding is buffered in and receives FIFO.
The accuracy for meeting addition timestamp in the side FGPA needs that a clock counter (meter is arranged in FPGA
One number time determines according to practical application), it is electrically connected between this clock counter and MPU by a GPIO signal wire, it can be with
Clock synchronization is zeroed out by MPU.This clock counter is to add timestamp.Concrete operations are as follows: when FPGA receives FIFO deposit
When one frame data, FPGA takes Counter Value at this time and this value is scaled the time according to the precision of counter, and deposit receives
In FIFO.
In the side MPU, the transmitting-receiving of serial equipment data is controlled, the FPGA under can be regarded as several cell fifos, MPU
It is addressed to operate by the related register address that every road serial ports that FPGA extends defines.
MPU timing by way of interrupt inquiry operates related serial equipment, and specific query time can basis
The quantity of extended serial port and used baud rate determine.
MPU and PFGA can greatly liberate MPU using DMA technology, make system when carrying out related data transmitting-receiving transmission
Operational efficiency is higher.
FPGA Multipexer independence serial ports, FPGA work in fifo mode.FPGA is in sending and receiving data and to serial ports baud
When rate and even-odd check etc. are arranged, controlled according to the better address of corresponding serial ports related register；MPU processor passes through
Dma mode carries out the interaction of sending and receiving data using data line and address wire and FPGA.It is changed corresponding by parallel bus simultaneously
Serial ports configuration register parameter realizes configuration and control to corresponding serial ports；
It is unified to confirm that address code format is as follows in course of normal operation:
Address bus structure is as shown in table 1 below:
| A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 |
| X2 | X1 | X0 | D/K | Y4 | Y3 | Y2 | Y1 |
Table 1
Note: A5-A7 is used to determine serial port；A4 is used to determine that address field is serial ports configuring area or data transmit-receive area；A0-
A3 is concrete function area.
When system worked well, the side FPGA serial ports address code format related to the unified confirmation in the side MPU and related serial ports
Base address is controlled, FPGA extends correspondence base address such as the following table 2 of 8 road serial ports:
| Serial port | Address range offset | Explanation |
| 1 | 0x00000000 | 1 corresponding address of serial ports |
| 2 | 0x00000020 | 2 corresponding address of serial ports |
| 3 | 0x00000040 | 3 corresponding address of serial ports |
| 4 | 0x00000060 | 4 corresponding address of serial ports |
| 5 | 0x00000080 | 5 corresponding address of serial ports |
| 6 | 0x000000A0 | 6 corresponding address of serial ports |
| 7 | 0x000000C0 | 7 corresponding address of serial ports |
| 8 | 0x000000E0 | 8 corresponding address of serial ports |
Table 2
As can be seen from the above table, the selection of serial ports base address mostlys come from the A5-A7 in table 1.
As shown in Figure 1, the end FPGA includes data reception module, data transmission blocks, serial ports configuration module, each module
There is its corresponding address space, the distribution of address space is as shown in table 1.
Data transmission blocks also include: sending marker bit detected register, whether serial ports is available (to detect for detecting
0x00 is the free time, and 0xaa then indicates that FPGA is busy)；Send data length register, for FPGA it is specified to send data and
The verification of all frame data and the length of the two；First and check register, the school of data is sent for storing the side MPU to FPGA
Test and.Specifically by taking serial ports 2 as an example, it see the table below 3:
Table 3
Data reception module also includes: receiving marker bit detected register, receives whether buffer area has data for detecting
(0xaa has new data, and 0x00 is without new data)；Reception data length register is used to receive data to the end MPU is specified and own
The verification of frame data and the length of the two；Frame end register, indicating this time to receive to FPGA for the end MPU terminates, write operation
0x5a indicates that MPU runs through data；It removes and receives buffer area data register, be used to reception FIFO null clear operation.Specifically with string
For mouth 2, it see the table below 4:
Table 4
Serial ports configuration module includes: Configuration of baud rate register, for the baud rate of corresponding serial ports is arranged；Data bit setting
Register, for the data bit of corresponding serial ports is arranged；Register is arranged in parity bit, for the odd even inspection of corresponding serial ports is arranged
Test position；Register is arranged in stop position, for the stopping check bit of corresponding serial ports is arranged；Second and check register, it is used for the end MPU
It reads that FPGA receives configuration information and verification, verifying and assigns the correctness of configuration；Download configuration end register is used for MPU
It holds to the end FPGA and sends configuration end order, MPU operates continuously this address twice, first writes 00, then write 01.Specifically it is with serial ports 2
Example, see the table below 5:
Table 5
The side MPU is addressed to operate by the way of interrupt inquiry to corresponding serial ports related register, so that control is more
Serial ports uniform operational.Interrupt inquiry can be by being arranged tick timer interrupt, periodically to each serial ports poll one time, and inquiry is each
The transmitting-receiving marker bit (being specifically shown in Table 3 and table 4) of marker bit detected register, can be determined by the inquiry of marker bit in serial ports
Some timeslice operates serial ports, and poll time can be carried out according to the serial ports number of extension and the baud rate used etc.
Adjustment.
In data transmission procedure, the transmission and control of data are carried out using MPU internal DMA controller, can solve releasing
MPU carries out other work.MPU of the present invention is to the mode that the operation of serial ports is using interrupt inquiry, that is to say, that during MPU passes through
The disconnected each serial ports transmitting-receiving of inquiry mode poll marks whether effectively, to trigger DMA data transfer.Before starting DMA data transfer
The value that MPU data transmit-receive caches first address, FPGA transmitting-receiving FIFO first address and transmitted data amount is assigned to control accordingly respectively
In register, start dma operation.After completing related data transmission, then give data/address bus and address bus to MPU.Such as
It is the data transmission stream journey block diagram of the invention based on DMA technology shown in Fig. 2, the specific steps are as follows:
Dma controller is posted according to the detection of the marker bit of FPGA side data receiving module, data transmission blocks in step 1, MPU
Storage determines whether to trigger effective DMA request；
Step 2 judges whether MPU replys, if it is, turn in next step, if not, go to step 1；
(every road serial ports needs transmission, received data length, receives and sends to dma controller relevant parameter by step 3, MPU
Storage address etc.) it is set；
Step 4 sends storage address (source address and destination address)；
Step 5 sends data；
Step 6, judge transmission whether complete, if it is, turn in next step, if not, modification storage address, go to step 4；
Step 7, DMA transmission terminate.
As shown in Figure 1, adding timestamp in the reception FIFO of the side FPGA, need that a clock count is arranged in FPGA
Device, the counting interval is as unit of ms (depending on added timestamp precision).This clock counter resets clock synchronization by MPU integral point,
MPU stores the time at this time after resetting, and the specific data-frame times that receive can be stabbed by receiving this frame data final time in FIFO
It counts and calculates gained with MPU the deposited time.
Timestamp specific logging mode in the reception FIFO of FPGA are as follows: after being stored in a frame byte, receive FIFO herein
The first two address filling 90,90 is made in a address of continuous 2+X (X number depends on the interval that MPU resets clock synchronization) after frame data
For the beginning label of timestamp, timestamp is added out of third address X address.
Such as the following table 6 example, 1ms is divided between the counter designed in FPGA, and the 1 minute clock synchronization in the interval MPU is primary, then counting
The countable value of number device should just be not less than 60,000.The MPU first time clock synchronization time (is labeled as time A, is deposited as shown in table 6
Enter in the address a of MPU), FPGA, which is counted, at this time resets.If FPGA counter counts are to 5000, a frame data are had received, then
The time (being labeled as time B) of this frame number play is exactly: B=*0 divides 5 seconds when a+5000ms, i.e. 10 days 10 October in 2018；
| Time | Year | Month | Day | When | Point | Second | Millisecond | FPGA count value |
| MPU first time clock synchronization | 2018 | 10 | 10 | 10 | 00 | 00 | 000 | 0 |
| FPGA count value | 5000 | |||||||
| Second of clock synchronization of MPU | 2018 | 10 | 10 | 10 | 01 | 00 | 000 | 0 |
Table 6
Embodiment of above is merely illustrative of the technical solution of the present invention rather than is limited, wherein not retouching in detail
The content stated belongs to the well-known technique of those skilled in the art.
Claims (10)
1. the implementation method of a kind of MPU and FPGA expanding multiple serial ports, FPGA and MPU carry out data using 8 channel parallel data buses
Interaction realizes addressing operation using 8 road address bus；One clock counter is set for adding timestamp, often in the side FPGA
Independent asynchronous serial port unit respectively includes a data reception module, data transmission blocks, serial ports configuration module and wave all the way
Special rate generator, the data reception module include receiving FIFO, data receiver register, the data transmission blocks packet
It includes and sends FIFO, data transmitter register, the serial ports configuration module is provided with for saving data transmission and control parameter
Register, which is characterized in that the transmission and control of data are carried out using the dma controller inside MPU in the data transmission；
In the side FPGA, when serial ports detects commencing signal, FPGA is by the parameter of the register in serial ports configuration module to reception
The data arrived carry out frame decoding, storage, after being stored in a frame byte, receive FIFO and add timestamp after this frame data；Send number
According to when, related serial ports carries out group to the data sent in FIFO according to the parameter of the register in its corresponding serial ports configuration module
Then frame is sent by serial ports；
In the side MPU, the transmitting-receiving of serial data is controlled, the FPGA under is regarded as several cell fifos, MPU is extended by FPGA
The related register address that defines of every road serial ports be addressed to operate, MPU is by way of interrupt inquiry periodically to correlation
Serial ports is polled operation.
2. the implementation method of a kind of MPU and FPGA expanding multiple serial ports according to claim 1, which is characterized in that described
Data reception module further include: send marker bit detected register, send data length register, first and check register；
The data reception module further include: receive marker bit detected register, reception data length register, frame end and post
Storage removes reception buffer area data register；
The serial ports configuration module includes: Configuration of baud rate register, register is arranged in data bit, parity bit setting is posted
Storage, stop position setting register, second and check register, download configuration end register.
3. the implementation method of a kind of MPU and FPGA expanding multiple serial ports according to claim 1 or 2, which is characterized in that described
Using inside MPU dma controller carry out data transmission with control specific steps include:
Dma controller is detected according to the marker bit of FPGA side data receiving module, data transmission blocks and is deposited in step 1, MPU
Device determines whether to trigger effective DMA request；
Step 2 judges whether MPU replys, if it is, turn in next step, if not, go to step 1；
Step 3, MPU set dma controller relevant parameter；
Step 4 sends storage address；
Step 5 sends data；
Step 6, judge transmission whether complete, if it is, turn in next step, if not, modification storage address, go to step 4；
Step 7, DMA transmission terminate.
4. the implementation method of a kind of MPU and FPGA expanding multiple serial ports according to claim 3, which is characterized in that step 3 institute
The dma controller relevant parameter stated includes: that every road serial ports needs transmission, received data length, is received, with sending memory
Location；
Transmission storage address described in step 4 includes source address and destination address.
5. the implementation method of a kind of MPU and FPGA expanding multiple serial ports according to claim 4, which is characterized in that the side FPGA
Address code format and related serial ports control base address are uniformly confirmed to the side MPU.
6. the implementation method of a kind of MPU and FPGA expanding multiple serial ports according to claim 5, which is characterized in that interruption is looked into
It askes through setting tick timer interrupt, periodically to each serial ports poll one time, inquiry serial ports marker bit detected register is to really
It is scheduled on the operation that some timeslice carries out serial ports, poll time can be according to the serial ports number of extension and the baud rate used
It is adjusted.
7. the implementation method of a kind of MPU and FPGA expanding multiple serial ports according to claim 6, which is characterized in that clock meter
It is electrically connected between number device and MPU by a GPIO signal wire, clock synchronization is reset by MPU integral point.
8. the implementation method of a kind of MPU and FPGA expanding multiple serial ports according to claim 7, which is characterized in that clock meter
The concrete operations of number device addition timestamp are as follows: when FPGA, which receives FIFO, is stored in a frame data, FPGA takes clock count at this time
This value is simultaneously scaled the time according to the precision of clock counter by device value, and deposit receives in FIFO.
9. the implementation method of a kind of MPU and FPGA expanding multiple serial ports according to claim 8, which is characterized in that timestamp
Receiving the logging mode in FIFO are as follows: after being stored in a frame byte, receive the continuous 2+X address after this frame data FIFO
90,90 beginning label as timestamp is inserted in middle the first two address, adds timestamp out of third address X address.
10. the implementation method of a kind of MPU and FPGA expanding multiple serial ports according to claim 9, which is characterized in that PFGA makes
With Xilinx Spartan-6 series of products XC6SLX9.
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