CN112667423A - Method, device and system for diagnosing program running time abnormity - Google Patents
Method, device and system for diagnosing program running time abnormity Download PDFInfo
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Abstract
The invention discloses a method, a device and a system for diagnosing program running time abnormity, wherein the method comprises the following steps: acquiring preset type data by using an MCU (microprogrammed control Unit), and comparing the acquired preset type data with a preset threshold value of a corresponding type, wherein the preset type data comprises the running time of a target code and/or the count value of an FPGA (field programmable gate array); the FPGA is connected with the MCU through an external pin, and the FPGA provides timing for the MCU through a counter; the MCU controls the start and the pause of the timing of the FPGA; and if the comparison difference is larger than the preset difference, outputting a diagnosis result representing the abnormity. The invention can improve the efficiency of diagnosing the time problem, shorten the method flow of diagnosing the time problem and provide a convenient and reliable diagnosis means for the phenomena of resetting and the like caused by the accidental time problem.
Description
Technical Field
The invention relates to a method, a device and a system for diagnosing program running time abnormity.
Background
With the iterative development of the software function of the chip, the time resource in the chip is more and more tense, and under the circumstance, some hidden troubles caused by manual misoperation exist in the process of iterating the software by designers.
For example, codes that can increase run time, which can only occur under certain conditions, are prone to escape testing, and when conditions are met, the program runs beyond the expected time, causing various problems, and in the severe cases, causing a chip reset.
Currently, developers generally add a pin change instruction before and after a certain program starts to finish to investigate reasons such as reset, and observe the time length of pin change by means of an oscilloscope or a logic analyzer to investigate time problems. The above method generally only checks the running time of one code at a time, and if the number of checks is increased, a plurality of pin resources and oscilloscope interfaces are occupied, so that the diagnosis is difficult.
Disclosure of Invention
The invention provides a method, a device and a system for diagnosing program running time abnormity, aiming at the problem that the existing reason for resetting a chip is difficult to diagnose.
The technical scheme provided by the invention for the technical problem is as follows:
in a first aspect, the present invention provides a method for diagnosing a runtime exception for a program, the method comprising:
acquiring preset type data by using an MCU (microprogrammed control Unit), and comparing the acquired preset type data with a preset threshold value of a corresponding type, wherein the preset type data comprises the running time of a target code and/or the count value of an FPGA (field programmable gate array); the FPGA is connected with the MCU through an external pin, and the FPGA provides timing for the MCU through a counter; the MCU controls the start and the pause of the timing of the FPGA;
and if the comparison difference is larger than the preset difference, outputting a diagnosis result representing the abnormity.
According to the method for diagnosing the program running time abnormality, the acquiring the preset type data by using the MCU and comparing the acquired preset type data with the preset threshold value of the corresponding type includes:
when the FPGA is powered on and reset, the FPGA automatically suspends the counting of the counter;
after power-on reset, the MCU acquires the running time of the monitored target code from the FPGA, wherein the running time comprises the interruption running time or the task running time;
and comparing the running time with a preset running time threshold.
According to the method for diagnosing the program running time abnormality, the acquiring preset type data by using the MCU and comparing the acquired data with the corresponding preset type data includes:
when the FPGA is powered on and reset, the FPGA automatically suspends the counting of the counter;
after power-on reset, the MCU acquires a count value of reset time;
and comparing the counting value with a preset counting threshold value.
According to the method for diagnosing the program running time abnormity, the controlling the starting and the pausing of the FPGA timing by the MCU comprises the following steps:
when the MCU executes an interrupt task function and a preset task enters a task interrupt state, stopping counting of the counter corresponding to the preset task;
if the preset task is in a recovery running state, recovering the counting of the corresponding counter, otherwise, not recovering the counting of the corresponding counter;
the preset task refers to a task which needs a counter to perform running counting and is run by the MCU.
According to the method for diagnosing the program running time abnormality, if the preset task is identified to restore the running state, the counting of the corresponding counter is restored, otherwise, the counting of the corresponding counter is not restored, and the method comprises the following steps:
when the MCU executes an interrupt task function, the nesting value is changed, wherein the nesting value is a preset variable for representing a nesting level; the change processing rule is that the nesting value is increased when the MCU executes an interrupt task function, and the nesting value is reduced when the MCU finishes executing the interrupt task function;
when the MCU finishes executing an interrupt task function, judging whether an interrupt task function nest exists according to the current nesting value;
if the current nesting value is larger than a preset value, recognizing that the interrupt task function nesting exists, and if the preset task does not recover the running state, not recovering the counting of the corresponding counter.
According to the method for diagnosing the program running time abnormity, the controlling the starting and the pausing of the FPGA timing by the MCU comprises the following steps:
if the MCU enters a high-priority task and a preset task enters a task interrupt state, stopping counting of the counter corresponding to the preset task;
if the preset task is recovered to the running state, the counting of the corresponding counter is recovered, otherwise, the counting of the corresponding counter is not recovered;
the preset task refers to a task which needs a counter to perform running counting and is run by the MCU.
According to the method for diagnosing the program running time abnormality, if the preset task is restored to the running state, the counting of the corresponding counter is restored, otherwise, the counting of the corresponding counter is not restored, and the method comprises the following steps:
when the MCU executes a high-priority task function, the nesting value is changed, wherein the nesting value is a preset variable for representing a nesting level; the change processing rule is that the nesting value is increased when the MCU executes a high-priority task function, and the nesting value is reduced when the MCU finishes executing the high-priority task function;
when the MCU finishes executing a high-priority task function, judging whether high-priority task function nesting exists according to the current nesting value;
if the current nesting value is larger than a preset value, recognizing that high-priority task function nesting exists, and if the preset task does not restore the running state, not restoring the counting of the corresponding counter.
In a second aspect, the present invention provides a diagnostic apparatus for diagnosing a runtime exception of a program, the apparatus comprising:
the comparison module is used for acquiring preset type data by using the MCU, and comparing the acquired preset type data with a preset threshold value of a corresponding type, wherein the preset type data comprises the running time of a target code and/or the count value of the FPGA; the FPGA is connected with the MCU through an external pin, and the FPGA provides timing for the MCU through a counter; the MCU controls the start and the pause of the timing of the FPGA;
and the diagnosis output module is used for outputting a diagnosis result representing the abnormity when the comparison difference is larger than the preset difference.
The diagnosis apparatus for diagnosing a program runtime abnormality according to the above, said apparatus further comprising:
and the identification module is used for identifying whether the preset task is recovered to the running state, wherein the preset task refers to a task which needs the running counting of the counter and is run by the MCU.
In a third aspect, the present invention also provides a diagnostic system for diagnosing a program runtime abnormality, which includes the diagnostic apparatus for diagnosing a program runtime abnormality as described above.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
by utilizing the counting and data interaction functions provided by the MCU and the FPGA, a maintenance or development personnel can monitor a plurality of codes at a time, and after the monitored codes are determined, the MCU time abnormity diagnostic program can be switched from an idle mode (the diagnostic codes do not run in the mode) to a diagnostic mode. And the MCU controls a corresponding control register in the FPGA to start, stop and clear a corresponding counter through an external pin. The MCU judges time abnormity after acquiring time data of the target code from the FPGA, and can upload the time data to an upper computer or display the time data to a maintenance or development staff for observation by other methods.
Compared with the traditional diagnosis mode: firstly selecting a monitoring target code, finding a reserved available pin, observing a result by using an oscilloscope, reducing a problem range, then reselecting the monitoring target code, and then observing the result, wherein the method is troublesome and has a limited applicable scene to position a time problem. The invention improves the efficiency of diagnosing the time problem, shortens the method flow of diagnosing the time problem, and provides a convenient and reliable diagnosis means for the phenomena of resetting and the like caused by the sporadic time problem.
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In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic flow chart diagram of a method for diagnosing run-time anomalies in a program according to the present invention;
FIG. 2 is a schematic diagram of the connection relationship between the MCU and the FPGA of the present invention;
FIG. 3 is a specific flowchart of a method for diagnosing run-time exceptions of a program according to the present invention;
FIG. 4 is a flow chart of task nesting identification provided by the present invention;
fig. 5 is a block diagram of a diagnostic apparatus for diagnosing an abnormal running time of a program according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The invention provides a method, a device and a system for diagnosing program running time abnormity, which are convenient for maintenance or developers to learn the abnormal conditions of the MCU program running time.
Referring to fig. 1, a flow chart of a method for diagnosing a runtime exception of a program according to the present invention is provided. The method for diagnosing the program running time abnormity is mainly applied to a diagnosis system, wherein the diagnosis system at least comprises an MCU (micro controller Unit) and an FPGA (Field Programmable Gate Array), and the MCU and the FPGA are electrically connected through an external pin.
As shown in fig. 1, the method for diagnosing a runtime exception of a program may include the steps of:
s101: acquiring preset type data by using an MCU (microprogrammed control Unit), and comparing the acquired preset type data with a preset threshold value of a corresponding type, wherein the preset type data comprises the running time of a target code and/or the count value of an FPGA (field programmable gate array); the FPGA is connected with the MCU through an external pin, and the FPGA provides timing for the MCU through a counter; and the MCU controls the start and the pause of the timing of the FPGA.
In this step, the FPGA provides timing for the MCU through the counter, and the MCU controls a control register (an area for receiving MCU commands in the FPGA, that is, a parallel bus transmits data control) in the FPGA through an external pin, thereby controlling the corresponding counter.
It is understood that after the count value of the corresponding counter is obtained, unit conversion may be performed and the maximum value, the minimum value, and the average value may be calculated. And then, storing the data or directly uploading the data to an upper computer according to actual needs for maintenance or observation of developers.
In this step, the preset type data may be an operation duration of the target code in the MCU, and the operation duration may include an interrupt operation duration or a task operation duration. Of course, the preset type data can also be the count value of a counter in the FPGA. Corresponding to the interruption operation time length, wherein the preset threshold is an interruption operation time length threshold; corresponding to the task running time, wherein the preset threshold is a task running time threshold; and corresponding to the counting value, the preset threshold is a counting threshold.
In this step, in some embodiments, the controlling, by the MCU, the start and the pause of the timing of the FPGA may specifically include the following sub-steps: when the MCU executes an interrupt task function and a preset task enters a task interrupt state, stopping counting of the counter corresponding to the preset task, wherein the preset task refers to a task which is running and needs the running counting of the counter; and if the preset task is in a recovery running state, recovering the counting of the corresponding counter, otherwise, not recovering the counting of the corresponding counter.
Here, if the preset task is resumed in the running state, resuming the count of the counter may specifically include: 1) when the MCU executes an interrupt task function, the nesting value is changed, wherein the nesting value is a preset variable for representing a nesting level; the change processing rule is that the nesting value is increased when the MCU executes an interrupt task function, and the nesting value is reduced when the MCU finishes executing the interrupt task function; 2) when the MCU finishes executing an interrupt task function, judging whether interrupt task function nesting exists according to the current nesting value, namely whether the preset task is recovered to the running state or not; 3) and if the current nesting value is larger than a preset value (namely the initial value of the nesting value), identifying that the interrupt task function nesting exists, and determining that the preset task does not recover the running state, so that the counting of the corresponding counter is not recovered. Of course, when it is determined that the preset task is restored to the running state, the counting of the counter is restored.
In other embodiments, the controlling the start and the pause of the timing of the FPGA by the MCU may further specifically include the following sub-steps: if the MCU enters a high-priority task and a preset task enters a task interrupt state, stopping counting of the counter corresponding to the preset task, and the preset task is a task which needs the counter to perform running counting and is run by the MCU in the same way as the previous embodiment; and if the preset task is recovered to the running state, recovering the counting of the corresponding counter, otherwise, not recovering the counting of the corresponding counter.
Here, if the preset task is resumed in the running state, resuming the count of the counter may specifically include: 1) when the MCU executes a high-priority task function, the nesting value is subjected to change processing, wherein the nesting value is a preset variable for representing a nesting level; the change processing rule is that the nesting value is increased when the MCU executes a high-priority task function, and the nesting value is reduced when the MCU finishes executing the high-priority task function; 2) and when the MCU finishes executing a high-priority task function, judging whether the high-priority task function nesting exists according to the current nesting value, namely whether the preset task is recovered to the running state. 3) And if the current nesting value is larger than a preset value, identifying that high-priority task function nesting exists, and judging that the preset task does not restore the running state, so that the counting of the corresponding counter is not restored. Of course, when it is determined that the preset task is restored to the running state, the counting of the counter is restored.
S102: and if the comparison difference is larger than the preset difference, outputting a diagnosis result representing the abnormity.
In this step, the diagnosis result representing the abnormality may be data reflecting the abnormality information, or may be the determination result itself. The preset difference value may preferably be zero, that is, when the acquired preset type data is greater than the preset threshold value of the corresponding type, it is determined to be abnormal, and a diagnosis result representing the abnormality is output.
With reference to step S101, in some embodiments, when the preset type data is run-time long, the acquiring, by the MCU, the preset type data specifically includes: and monitoring the running of the target code by using the MCU, and acquiring the running time length or the interruption running time length of the target code. At this time, the comparing the acquired preset type data with the preset threshold of the corresponding type specifically includes: and comparing the acquired running time with a running time threshold, and comparing the acquired interrupted running time with an interrupted running time threshold. Here, if the preset type data is an interrupt operation duration, the output of the diagnosis result representing the abnormality may be: the interrupt runs out of time. If the preset type data is the task running time, outputting a diagnosis result representing the abnormality as follows: the task runs out of time.
In some other embodiments, when the preset type data is a count value, the acquiring, by the MCU, the preset type data specifically includes: and the MCU acquires the count value of the counter from the FPGA. At this time, the comparing the acquired preset type data with the preset threshold of the corresponding type specifically includes: the count value is compared to a count threshold. Here, the output of the diagnosis result representing the abnormality may be: the timeout causes a reset.
In the invention, by utilizing the counting and interactive data functions provided by the MCU and the FPGA, a maintenance or development personnel can monitor a plurality of codes at one time, and after the monitored codes are determined, the MCU time abnormity diagnostic program can be switched from an idle mode (the diagnostic codes do not run in the mode) to a diagnostic mode. And the MCU controls a corresponding control register in the FPGA to start, stop and clear a corresponding counter through an external pin. The MCU judges time abnormity after acquiring time data of the target code from the FPGA, and can upload the time data to an upper computer or display the time data to a maintenance or development staff for observation by other methods.
Compared with the traditional diagnosis mode: firstly selecting a monitoring target code, finding a reserved available pin (needing to look at a schematic diagram), observing a result by using an oscilloscope, reducing a problem range, then reselecting the monitoring target code, and then observing the result, wherein the method is troublesome and has a limited applicable scene to position a time problem. The invention improves the efficiency of diagnosing the time problem, shortens the method flow of diagnosing the time problem, and provides a convenient and reliable diagnosis means for the phenomena of resetting and the like caused by the sporadic time problem.
Referring to fig. 2, a schematic diagram of a connection relationship between the MCU and the FPGA of the present invention is shown. The MCU controls a control register in the FPGA (an area for receiving MCU commands in the FPGA, namely parallel bus data transmission control) through an external pin to control the corresponding counter to start counting. The mapping relationship between the register and the counter can be as follows: bit 0: counter 0, Bit 1: counter 1.. Bit 15: a counter 15. And after the diagnostic program obtains the value of the corresponding counter, the unit is converted into us, the maximum value, the minimum value and the average value are calculated, and then the data are stored or directly uploaded to an upper computer to be observed by a maintenance or development worker according to actual needs.
Referring to fig. 3 and 4, fig. 3 is a specific flowchart of a method for diagnosing a runtime exception of a program according to the present invention; FIG. 4 is a flowchart of task nesting identification provided by the present invention. With reference to fig. 1 and 2, in the case of power-on reset, the FPGA automatically detects the reset and suspends all counters. And after power-on reset, the MCU acquires the running time length of the target code during reset from the FPGA, and compares the running time length with a preset running time length threshold value to judge whether the time is abnormal. If the comparison difference is greater than the preset running time threshold, judging that the time is abnormal, and outputting a diagnosis result representing the abnormality: and prompting that the reset is prompt information caused by overtime. If the comparison difference is smaller than or equal to the preset running time threshold, the judgment result is normal, at the moment, the MCU enters an idle mode, and the diagnostic code is not run in the idle mode, and only the cycle is carried out to start the diagnostic function.
If the diagnostic function is enabled, there are:
for a running task: and acquiring the running time of the target code from the FPGA (which can support the monitoring of the target code at 16 positions), judging whether the running time of the target code is abnormal or not if the running of the target code is finished, and if the running time of the target code is abnormal, calculating the maximum value, the minimum value and the average value of abnormal data, uploading the data to an upper computer for maintenance or observation of developers, and naturally, storing corresponding data locally. And if the target code is not finished or is judged to be normal, continuing to monitor the target code.
It can be understood that, when the MCU enters a high priority task, i.e. executes a high priority task function, the predetermined task enters a task interrupt state, thereby suspending the counting of the counter (currently in use) corresponding to the predetermined task and resuming the counting of the corresponding counter when the MCU leaves the task. For the nesting of the high-priority tasks, that is, the high-priority tasks have higher priority tasks, the counting control of the counter is performed according to the rule, which may cause the problem of removing the abnormal time length of the high-priority tasks. When the high-priority tasks are in a nested state, the counting of each high-priority task is recovered when the high-priority task leaves, and if the high-priority tasks are nested at the moment, namely the low-priority tasks are still in a waiting state, but the counting is recovered, the problem that the time length occupied by all the high-priority tasks in the low-priority tasks is removed does not exist. Therefore, for the problem of causing the exception of the time length of the task with high priority, before judging whether to recover the count, whether the task with high priority is in the nested state needs to be determined, so the following procedures are provided:
for high priority tasks or task interrupts (here, task interrupts are also considered high priority tasks, the same process applies): firstly, whether the occupied time of the high-priority task is removed is judged, and when the judgment result is yes, the execution of the high-priority task is started, the register which is counted by the FPGA at the moment is paused, and the state of the register is saved. And when the judgment result is negative, the high-priority task execution can be judged to be finished, namely the MCU executes a high-priority task function. And then, judging whether the high-priority tasks are nested or not, specifically judging whether the high-priority task function nesting exists in the current preset task or not according to the current nesting value, and if not, recovering the counting state of the FPGA, and starting counting until the execution of the high-priority tasks is finished. And when the high-priority nesting is judged to be in the high-priority nesting, the counting of the corresponding counter is not recovered until the execution of the high-priority task is finished. As shown in fig. 4, a flag may be set to indicate the task level a, and then, if a high priority task is entered, i.e. a high priority task function is executed, the change processing is performed: an A addition or other form of change is employed as a nesting value for nesting identification. And then judging the level of the task level A, if the task level A is judged to be the first level, adopting the reduction or other changes of the A as another variable value for nesting identification, and then returning to the nesting state. And if the task level A is judged not to be the first level, judging that the current task is in a nested state.
More specifically, in a specific application example, when the preset task executes the high-priority task function each time, one is added to the nesting value determined when the high-priority task function was executed last time, and one is subtracted when the preset task leaves the execution of the high-priority task function. Therefore, if the variable is greater than 1 before leaving, nesting of the high-priority task exists, and at the moment, counting is not recovered when leaving the state of the high-priority task; if the variable is equal to 1, it indicates that there is no high priority task nesting and the count is restored upon exit.
Referring to fig. 5, a block diagram of a diagnostic apparatus for diagnosing a program running time abnormality according to the present invention is provided, where the diagnostic apparatus 1 for diagnosing a program running time abnormality includes a comparison module 11, a diagnostic output module 12, and an identification module 13, where:
the comparison module 11 is configured to acquire preset type data by using the MCU, and compare the acquired preset type data with a preset threshold of a corresponding type, where the preset type data includes an operation duration of a target code and/or a count value of the FPGA; the FPGA is connected with the MCU through an external pin, and the FPGA provides timing for the MCU through a counter; and the MCU controls the start and the pause of the timing of the FPGA.
And the diagnosis output module 12 is used for outputting a diagnosis result representing the abnormity when the comparison difference is larger than the preset difference.
The identification module 13 is configured to identify whether a preset task is resumed in an operating state, where the preset task is a task that the MCU is operating and needs the counter to perform operation counting.
When running, the diagnostic device 1 for diagnosing the running time abnormity of the program can utilize the counting and interactive data functions provided by the MCU and the FPGA, a maintenance or development personnel can monitor a plurality of codes at a time, and after the monitored codes are determined, the MCU time abnormity diagnostic program can be switched from an idle mode (in which the diagnostic codes are not running) to a diagnostic mode. And the MCU controls a corresponding control register in the FPGA to start, stop and clear a corresponding counter through an external pin. The MCU judges time abnormity after acquiring time data of the target code from the FPGA, and can upload the time data to an upper computer or display the time data to a maintenance or development staff for observation by other methods.
The invention also provides a diagnosis system for diagnosing the running time abnormity of the program, which can comprise the diagnosis device for diagnosing the running time abnormity of the program, and when in application, a maintenance or development personnel can monitor a plurality of codes at a time by using the counting and interactive data functions provided by the MCU and the FPGA, and after the monitored codes are determined, the MCU time abnormity diagnosis program can be switched from an idle mode (in which the diagnosis codes are not run) to a diagnosis mode. And the MCU controls a corresponding control register in the FPGA to start, stop and clear a corresponding counter through an external pin. The MCU judges time abnormity after acquiring time data of the target code from the FPGA, and can upload the time data to an upper computer or display the time data to a maintenance or development staff for observation by other methods.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A method for diagnosing a program runtime exception, the method comprising:
acquiring preset type data by using an MCU (microprogrammed control Unit), and comparing the acquired preset type data with a preset threshold value of a corresponding type, wherein the preset type data comprises the running time of a target code and/or the count value of an FPGA (field programmable gate array); the FPGA is connected with the MCU through an external pin, and the FPGA provides timing for the MCU through a counter; the MCU controls the start and the pause of the timing of the FPGA;
and if the comparison difference is larger than the preset difference, outputting a diagnosis result representing the abnormity.
2. The method according to claim 1, wherein the acquiring preset type data by the MCU and comparing the acquired preset type data with a preset threshold of a corresponding type comprises:
when the FPGA is powered on and reset, the FPGA automatically suspends the counting of the counter;
after power-on reset, the MCU acquires the running time of the monitored target code from the FPGA;
and comparing the running time with a preset running time threshold.
3. The method according to claim 1, wherein the acquiring preset type data by the MCU and comparing the acquired preset type data with the preset threshold value of the corresponding type comprises:
when the FPGA is powered on and reset, the FPGA automatically suspends the counting of the counter;
after power-on reset, the MCU acquires a count value of reset time;
and comparing the counting value with a preset counting threshold value.
4. The method for diagnosing program runtime anomalies as recited in claim 1, wherein said controlling with said MCU the start and pause of the timing of said FPGA comprises:
when the MCU executes an interrupt task function and a preset task enters a task interrupt state, stopping counting of the counter corresponding to the preset task;
if the preset task is in a recovery running state, recovering the counting of the corresponding counter, otherwise, not recovering the counting of the corresponding counter;
the preset task refers to a task which needs a counter to perform running counting and is run by the MCU.
5. The method of claim 4, wherein the step of restoring the count of the counter if the default task resuming operation state is identified, and not restoring the count of the counter if the default task resuming operation state is not identified comprises:
when the MCU executes an interrupt task function, the nesting value is changed, wherein the nesting value is a preset variable for representing a nesting level; the change processing rule is that the nesting value is increased when the MCU executes an interrupt task function, and the nesting value is reduced when the MCU finishes executing the interrupt task function;
when the MCU finishes executing an interrupt task function, judging whether an interrupt task function nest exists according to the current nesting value;
if the current nesting value is larger than a preset value, recognizing that the interrupt task function nesting exists, and if the preset task does not recover the running state, not recovering the counting of the corresponding counter.
6. The method for diagnosing program runtime anomalies as recited in claim 1, wherein said controlling with said MCU the start and pause of the timing of said FPGA comprises:
if the MCU enters a high-priority task and a preset task enters a task interrupt state, stopping counting of the counter corresponding to the preset task;
if the preset task is recovered to the running state, the counting of the corresponding counter is recovered, otherwise, the counting of the corresponding counter is not recovered;
the preset task refers to a task which needs a counter to perform running counting and is run by the MCU.
7. The method of claim 6, wherein the step of recovering the count corresponding to the counter if the preset task recovers the running state, and not recovering the count corresponding to the counter if the preset task does not recover the running state comprises:
when the MCU executes a high-priority task function, the nesting value is changed, wherein the nesting value is a preset variable for representing a nesting level; the change processing rule is that the nesting value is increased when the MCU executes a high-priority task function, and the nesting value is reduced when the MCU finishes executing the high-priority task function;
when the MCU finishes executing a high-priority task function, judging whether high-priority task function nesting exists according to the current nesting value;
if the current nesting value is larger than a preset value, recognizing that high-priority task function nesting exists, and if the preset task does not restore the running state, not restoring the counting of the corresponding counter.
8. A diagnostic apparatus for diagnosing a program runtime abnormality, the apparatus comprising:
the comparison module is used for acquiring preset type data by using the MCU, and comparing the acquired preset type data with a preset threshold value of a corresponding type, wherein the preset type data comprises the running time of a target code and/or the count value of the FPGA; the FPGA is connected with the MCU through an external pin, and the FPGA provides timing for the MCU through a counter; the MCU controls the start and the pause of the timing of the FPGA;
and the diagnosis output module is used for outputting a diagnosis result representing the abnormity when the comparison difference is larger than the preset difference.
9. The diagnostic apparatus for diagnosing a program runtime abnormality according to claim 8, said apparatus further comprising:
the identification module is used for identifying whether the preset task is recovered to the running state;
the preset task refers to a task which needs a counter to perform running counting and is run by the MCU.
10. A diagnostic system for diagnosing a program run-time abnormality, comprising the diagnostic apparatus for diagnosing a program run-time abnormality according to any one of claims 8 to 9.
Priority Applications (1)
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