CN102541799A - Method for realizing multi-serial-port extension by using FPGA (field programmable gate array) - Google Patents
Method for realizing multi-serial-port extension by using FPGA (field programmable gate array) Download PDFInfo
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Abstract
A method for realizing multi-serial-port extension by using an FPGA (field programmable gate array) includes the steps: connecting a processor with the FPGA through a parallel bus, a DSP (digital signal processor) data line and an address line; constructing a serial port top control module and defining registers for configuring working modes of serial ports, wherein the serial port top control module comprises nine registers for being configured by a DSP, five status registers for returning to current operating conditions of the serial ports and registers for configuring Baud rate; and completing operation of the registers by means of coordination of the processor and the FPGA and through the parallel bus, the DSP data line and the address line, so that a serial port extension function is realized. The method is capable of realizing UART (universal asynchronous receiver/transmitter) interface extension based on the parallel bus and has the advantages of small size, low power consumption, high reliability, high safety, low systematic cost and the like, and all functions of a special serial-port extension chip are achieved.
Description
Technical field
The invention belongs to the serial port communication technology field, use on-site programmable device FPGA to communicate by letter with external asynchronous communication interface UART as interface realization digital signal processor DSP.Be specifically related to a kind of method of utilizing the VHDL language programming to realize many serial ports expansion.
Background technology
On-site programmable device FPGA is the device of widespread use in recent years; It has that integrated level height, volume are little, low in energy consumption, high reliability, high security, system cost are low, dirigibility is convenient to characteristics such as connection well, thereby is used widely in the electronic technology in modern times.In the FPGA sheet rich in natural resources is arranged, its numerous input/output port can directly be linked to each other with processor data line address wire by the free definition of data width of user, does not even need level conversion.The supplier of chip also provides abundant integrated base resource to supply the user to call, and therefore makes that the application of FPGA is very convenient.Utilize the VHDL programming technique can in the FPGA sheet, realize the function of digital signal circuit easily.
In current many serial ports expansion technology, except using special-purpose serial ports expansion chip, widespread usage FPGA is as the serial ports expansion device.Present known function is to utilize FPGA to realize the function of special-purpose serial ports expansion chip, how to realize but rare document is mentioned to, and it can not satisfy the diversity of user data, thereby can not under various applied environments, bring into play the usefulness of maximum.
Summary of the invention
The object of the present invention is to provide a kind of FPGA of utilization to realize the method for many serial ports expansion; It has solved in the background technology can't realize many serial ports expansion; The diversity of user data can not be satisfied, thereby the technical matters of maximum usefulness can not be under various applied environments, brought into play.
The processor model TMS320C6713 that the present invention uses, FPGA model X3CS400.It can link to each other with DSP data line, address wire through parallel bus, also can be through changing with SPI mode continuous (the present invention does not do and tells about).Change configuration register through DSP and change the serial ports working method, reach the serial ports expansion purpose and satisfy users on diversity.
Technical solution of the present invention is:
A kind of FPGA of utilization realizes the method for many serial ports expansion, and its special character is that this method comprises: processor and FPGA, and it links to each other with DSP data line, address wire through parallel bus;
Make up serial ports top layer control module, definition register is used to dispose the serial ports working method;
(1) said serial ports top layer control module comprises 9 registers that supply the DSP configuration;
Definition is as follows respectively:
Register BR10, BR32, BR54 and the BR76 of 4 configurations of ■ baud rate;
■ S_CHANNEL is a port select register;
■ S_INT_DEPTH interrupts depth register;
■ INT_MASK is an IMR;
■ PARITY_ENABLE check bit enable register;
■ PARITY_SELECT check bit mask register;
(2) said serial ports top layer control module also comprises 5 status registers, is used to return current serial ports duty;
Definition is as follows respectively:
■ UARTINT is an interrupt status register;
■ EMPTY receives the FIFO dummy register;
■ FULL sends the full register of FIFO;
■ PARITY_ENABLE check bit enable register;
■ PARITY_SELECT check bit mask register;
(3) register of configuration baud rate; Referring to table 1
(4) cooperate through processor and FPGA, it is accomplished above-mentioned operation registers through parallel bus and DSP data line, address wire, realizes the serial ports expansion function.
Above-mentioned interrupt status register: bit [7:0] is the interruption status of respective channel 7～0 respectively, and corresponding positions is that 5-1 representes that respective channel produces interruption, is that 0 expression nothing is interrupted; 8 serial ports can concurrent working, and the 8 road FIFOs corresponding with it are arranged among FPGA, and when taking place to interrupt, DSP need know what which road sent, so interrupt status register is just arranged.
Above-mentioned interruption depth register: the programmable interruption degree of depth, as: write 128 expression passages and receive 128 bytes generation interruptions; UART becomes parallel data to be placed among the FIFO data conversion that receives, and how many bytes just can produce interruption as, and gives DSP with data transfer, and how many byte numbers DSP will once get from FIFO, so IMR is just arranged.
Full register: the bit [7:0] of above-mentioned FIFO is the transmission fifo status of respective channel 7～0 respectively, is that the corresponding FIFO of 1 expression is full, is that the corresponding FIFO of 0 expression is discontented.
Above-mentioned FIFO dummy register: bit [7:0] is the reception fifo status of respective channel 7～0 respectively, is that the corresponding FIFO of 1 expression is empty, is that the corresponding FIFO of 0 expression is not empty.
Above-mentioned IMR: bit [7:0] is respective channel 7～0 respectively, and corresponding positions is the interruption that 1 expression enables respective channel, is that 0 expression forbids that respective channel produces interruption; The DSP data line is handled interrupting, and thinks that this segment data is inessential but work as DSP, perhaps can abandon, and it can use IMR that the interrupt mask on this road is fallen so.
Above-mentioned check bit enable register: bit [7:0] is respective channel 7～0 respectively, and corresponding positions is the check bit that 1 expression enables respective channel, is 0 expression no parity check.
Above-mentioned check bit mask register: bit [7:0] is respective channel 7～0 respectively, and corresponding positions is the odd parity bit of 1 expression respective channel, is 0 expression even parity check.
Above-mentioned wherein passage 0-5 is RS422, and passage 6 and 7 is RS232.
Above-mentioned processor model TMS320C6713, said FPGA model X3CS400.
The invention has the advantages that:
1. can realize UART interface expansion based on parallel bus;
2. easy to connect flexibly with the DSP data line, have that volume is little, low in energy consumption, high reliability, high security, system cost are low etc.;
3. kernel is independent, does not receive the ppu temporal constraint, can be transplanted to other type processor interface easily;
4. all functions that have special-purpose serial ports expansion chip.The baud rate that for example can be provided with etc.;
5. but the interrupt mode that exclusive any time is provided with, interrupt levels, the interruption degree of depth, interruption times etc.;
6. can conveniently extend to multi-channel serial port, the code revision amount is little, transplanting is convenient.
Description of drawings
Fig. 1 is the interrupt mask synoptic diagram;
Fig. 2 is a single channel serial port module synoptic diagram;
Fig. 3 is a serial ports top layer control module synoptic diagram;
The interface synoptic diagram that Fig. 4 uses in designing for fifo module.
Embodiment
According to the address assignment of register and register in the last table 1, we are presented in the mutual process in detail below, and the effect of these registers realizes with concrete.
1) interruption status of interrupt status register (UARTINT): bit [7:0] difference respective channel 7～0, corresponding positions are that 5-1 representes that respective channel produces interruption, are that 0 expression does not have interruption.8 serial ports can concurrent working, and the 8 road FIFOs corresponding with it are arranged among FPGA, and when taking place to interrupt, DSP need know what which road sent, so interrupt status register is just arranged.
2) interrupt depth register (S_INT_DEPTH): the programmable interruption degree of depth, for example: write 128 expression passages and receive 128 bytes generation interruptions.UART becomes parallel data to be placed among the FIFO data conversion that receives, and how many bytes just can produce interruption as, and gives DSP with data transfer, and how many byte numbers DSP will once get from FIFO, so IMR is just arranged.
3) the transmission fifo status of full register (FULL): bit [7:0] difference of FIFO respective channel 7～0 is that the corresponding FIFO of 1 expression is full, is that the corresponding FIFO of 0 expression is discontented.
4) the reception fifo status of FIFO dummy register (EMPTY): bit [7:0] difference respective channel 7～0 is that the corresponding FIFO of 1 expression is empty, is that the corresponding FIFO of 0 expression is not empty.
5) IMR (INT_MASK): bit [7:0] difference respective channel 7～0, corresponding positions is the interruption that 1 expression enables respective channel, is that 0 expression forbids that respective channel produces interruption.The DSP data line is handled interrupting, but thinks that when the DSP data line this segment data is inessential, perhaps can abandon, and it can use IMR that the interrupt mask on this road is fallen so.
6) check bit enable register (PARITY_ENABLE): bit [7:0] difference respective channel 7～0, corresponding positions is the check bit that 1 expression enables respective channel, is 0 expression no parity check.
7) check bit mask register (PARITY_SELECT): bit [7:0] difference respective channel 7～0, corresponding positions is the odd parity bit of 1 expression respective channel, is 0 expression even parity check.
8) wherein passage 0-5 is RS422, and passage 6 and 7 is RS232.
1 other realization of down trigger level
The rising edge of each FPGA clock compares the existing byte number among the FIFO with interrupting the depth register data, when more than or equal to the time, with interrupt status register correspondence position 1.Interrupt status register promptly is INT5 (serial ports interruption) at each FPGA rising edge clock with each phase or result, exports the DSP data line to, realizes interrupting output.Interruption can be seen off with level or edge mode, depends on the register setting.Both can once export a pulse and wait the sky that continues then, also can receive whether data determine whether to send out consecutive pulses greater than zero among the FIFO through continuous interpretation.Perhaps receive and just produce interruption when data satisfy certain value.
The realization of 2 interrupt mask
If will shield the interruption of corresponding serial ports passage, need relevant position 0 with IMR, at each rising edge of FPGA clock, IMR is with interrupt status register step-by-step and, the result interrupt status register of restoring.The corresponding positions of conductively-closed is 0 like this, can not produce to interrupt output.
Interrupt mask synoptic diagram: referring to Fig. 1.
The configurable realization of 3 baud rates
FPGA is provided with register through reading baud rate, distributes the divide ratio of each serial ports channel clock, thereby produces the work clock of each serial port module.
4 serial port module RS232_1 (other each road is together):
Functional block diagram is referring to Fig. 2; Serial ports top layer control module synoptic diagram is referring to Fig. 3.
sends Logic control module: if it is not empty to send FIFO; And transmission is not in a hurry, and then produces signal UART_RD_FIFO and from send FIFO, reads a byte data entering serial port protocol module and transmission; If send busy or the FIFO sky, then wait for.
serial port protocol module: the parallel data that will send; According to the working method of DSP data line configuration, send through the TX port.Data with the RX port receives transfer parallel data to according to serial port protocol and deposit FIFO in.
The metadata cache that
reception/transmission FIFO:FIFO need send primary processor supplies serial port protocol module reading and sending.The metadata cache that perhaps the serial port protocol module is received supplies the DSP data line to read.
Fifo module is to call the IPCORE that XILINX ISE 9.2i carries.
The interface of using in the design is referring to Fig. 4:
DIN [7:0]: FIFO input data line;
DOUT [7:0]: FIFO output data line;
The WR_EN:FIFO write signal;
The RD_EN:FIFO read signal;
CLK: connect the 14.7456MHZ clock;
When 1024 bytes were arranged among the FULL:FIFO, this signal was effective;
When EMPTY:FIFO was empty, signal was effective;
PROG_FULL: full signal able to programme;
DATA_COUNT [9:0]: write down the byte number among the current FIFO;
Table 2FIFO work truth table
Some important parameters of FIFO
The width of
FIFO: the data bit that is a read-write operation of FIFO; The width of FIFO is fixed in monolithic finished product IC; Also have selectable; If realize a FIFO with FPGA oneself, its data bit, just width can oneself define.
The degree of depth of
FIFO: be the data (if width is N) what N positions FIFO can store.Like one 8 FIFO, for example the FIFO degree of depth is 1024 in the native system, and it can store 1024 8 data.
The signal that
full scale will: FIFO is full to be seen off by the status circuit of FIFO maybe will expire the time continues write data in FIFO and causes and overflow (overflow) with the write operation that stops FIFO.
reads clock: the clock that read operation is followed, come interim read data on each clock edge.
The read-write pointer is exactly the address of read-write in fact, and only this address can not be selected arbitrarily, but continuous.
Claims (10)
1. a method of utilizing FPGA to realize many serial ports expansion is characterized in that, this method comprises: processor and FPGA, and it links to each other with DSP data line, address wire through parallel bus;
Make up serial ports top layer control module, definition register is used to dispose the serial ports working method;
(1) said serial ports top layer control module comprises 9 registers that supply the DSP configuration;
Definition is as follows respectively:
Register BR10, BR32, BR54 and the BR76 of 4 configurations of ■ baud rate;
■ S_CHANNEL is a port select register;
■ S_INT_DEPTH interrupts depth register;
■ INT_MASK is an IMR;
■ PARITY_ENABLE check bit enable register;
■ PARITY_SELECT check bit mask register;
(2) said serial ports top layer control module also comprises 5 status registers, is used to return current serial ports duty;
Definition is as follows respectively:
■ UARTINT is an interrupt status register;
■ EMPTY receives the FIFO dummy register;
■ FULL sends the full register of FIFO;
■ PARITY_ENABLE check bit enable register;
■ PARITY_SELECT check bit mask register;
(3) register of configuration baud rate; Referring to table 1
(4) cooperate through processor and FPGA, it is accomplished above-mentioned operation registers through parallel bus and DSP data line, address wire, realizes the serial ports expansion function.
2. realize the method for many serial ports expansion according to the said FPGA of utilization of claim 1; It is characterized in that; Said interrupt status register: bit [7:0] is the interruption status of respective channel 7～0 respectively, and corresponding positions is that 5-1 representes that respective channel produces interruption, is that 0 expression nothing is interrupted; 8 serial ports can concurrent working, and the 8 road FIFOs corresponding with it are arranged among FPGA, and when taking place to interrupt, DSP need know what which road sent, so interrupt status register is just arranged.
3. realize the method for many serial ports expansion according to the said FPGA of utilization of claim 1, it is characterized in that said interruption depth register: the programmable interruption degree of depth, as: write 128 expression passages and receive 128 bytes generation interruptions; UART becomes parallel data to be placed among the FIFO data conversion that receives, and how many bytes just can produce interruption as, and gives DSP with data transfer, and how many byte numbers DSP will once get from FIFO, so IMR is just arranged.
4. realizing the method for many serial ports expansion according to the said FPGA of utilization of claim 1, it is characterized in that full register: the bit [7:0] of said FIFO is the transmission fifo status of respective channel 7～0 respectively, is that the corresponding FIFO of 1 expression is full, is that the corresponding FIFO of 0 expression is discontented.
5. realizing the method for many serial ports expansion according to the said FPGA of utilization of claim 1, it is characterized in that said FIFO dummy register: bit [7:0] is the reception fifo status of respective channel 7～0 respectively, is that the corresponding FIFO of 1 expression is empty, is that the corresponding FIFO of 0 expression is not empty.
6. realize the method for many serial ports expansion according to the said FPGA of utilization of claim 1; It is characterized in that; Said IMR: bit [7:0] is respective channel 7～0 respectively, and corresponding positions is the interruption that 1 expression enables respective channel, is that 0 expression forbids that respective channel produces interruption; The DSP data line is handled interrupting, and thinks that this segment data is inessential but work as DSP, perhaps can abandon, and it can use IMR that the interrupt mask on this road is fallen so.
7. realize the method for many serial ports expansion according to the said FPGA of utilization of claim 1, it is characterized in that said check bit enable register: bit [7:0] is respective channel 7～0 respectively, corresponding positions is the check bit that 1 expression enables respective channel, is 0 expression no parity check.
8. realize the method for many serial ports expansion according to the said FPGA of utilization of claim 1, it is characterized in that said check bit mask register: bit [7:0] is respective channel 7～0 respectively, corresponding positions is the odd parity bit of 1 expression respective channel, is 0 expression even parity check.
9. realize the method for many serial ports expansion according to the said FPGA of utilization of claim 1, it is characterized in that said wherein passage 0-5 is RS422, passage 6 and 7 is RS232.
10. realize the method for many serial ports expansion according to the arbitrary said FPGA of utilization of claim 1～9, it is characterized in that: said processor model TMS320C6713, said FPGA model X3CS400.
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| CN103473192A (en) * | 2013-09-18 | 2013-12-25 | 浪潮电子信息产业股份有限公司 | Field programmable gate array and soft-core processor core-based multi-UART (universal asynchronous receiver transmitter) interface extension system |
| CN103714024A (en) * | 2013-12-18 | 2014-04-09 | 国核自仪系统工程有限公司 | Multi-serial port parallel processing framework based on SoC (System on a Chip) FPGA (Field Programmable Gata Array) |
| CN103885843A (en) * | 2013-03-01 | 2014-06-25 | 上海富欣智能交通控制有限公司 | Method for processing safety parallel buses between DSP (digital signal processor) and CPLD (complex programmable logic device) |
| CN104503934A (en) * | 2014-12-02 | 2015-04-08 | 天津国芯科技有限公司 | Extendable serial transmission device |
| CN104866452A (en) * | 2015-05-19 | 2015-08-26 | 哈尔滨工业大学(鞍山)工业技术研究院 | Multi-serial port extension method based on FPGA and TL16C554A |
| CN105426562A (en) * | 2015-08-18 | 2016-03-23 | 杭州优稳自动化系统有限公司 | UART communication method and apparatus between multiple IO modules and multiple communication modules |
| CN106933772A (en) * | 2017-02-17 | 2017-07-07 | 西安航空制动科技有限公司 | The SCI means of communication based on UART IP kernels |
| CN108228513A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of intelligent serial communication module and control method based on FPGA architecture |
| CN109857685A (en) * | 2018-12-06 | 2019-06-07 | 积成电子股份有限公司 | A kind of implementation method of MPU and FPGA expanding multiple serial ports |
| CN116991223A (en) * | 2023-09-26 | 2023-11-03 | 深圳市天龙世纪科技发展有限公司 | Low-power-consumption serial port expansion method, system and storage medium based on mobile equipment |
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| CN103885843A (en) * | 2013-03-01 | 2014-06-25 | 上海富欣智能交通控制有限公司 | Method for processing safety parallel buses between DSP (digital signal processor) and CPLD (complex programmable logic device) |
| CN103473192A (en) * | 2013-09-18 | 2013-12-25 | 浪潮电子信息产业股份有限公司 | Field programmable gate array and soft-core processor core-based multi-UART (universal asynchronous receiver transmitter) interface extension system |
| CN103714024A (en) * | 2013-12-18 | 2014-04-09 | 国核自仪系统工程有限公司 | Multi-serial port parallel processing framework based on SoC (System on a Chip) FPGA (Field Programmable Gata Array) |
| CN104503934A (en) * | 2014-12-02 | 2015-04-08 | 天津国芯科技有限公司 | Extendable serial transmission device |
| CN104503934B (en) * | 2014-12-02 | 2017-10-24 | 天津国芯科技有限公司 | A kind of expansible serial transmission device |
| CN104866452A (en) * | 2015-05-19 | 2015-08-26 | 哈尔滨工业大学(鞍山)工业技术研究院 | Multi-serial port extension method based on FPGA and TL16C554A |
| CN104866452B (en) * | 2015-05-19 | 2017-09-26 | 哈尔滨工业大学(鞍山)工业技术研究院 | Multi-serial extension method based on FPGA and TL16C554A |
| CN105426562A (en) * | 2015-08-18 | 2016-03-23 | 杭州优稳自动化系统有限公司 | UART communication method and apparatus between multiple IO modules and multiple communication modules |
| CN105426562B (en) * | 2015-08-18 | 2019-02-05 | 杭州优稳自动化系统有限公司 | The UART means of communication and device between a kind of more I/O modules and more communication modules |
| CN108228513A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of intelligent serial communication module and control method based on FPGA architecture |
| CN108228513B (en) * | 2016-12-14 | 2021-03-26 | 中国航空工业集团公司西安航空计算技术研究所 | Intelligent serial port communication device based on FPGA framework |
| CN106933772A (en) * | 2017-02-17 | 2017-07-07 | 西安航空制动科技有限公司 | The SCI means of communication based on UART IP kernels |
| CN109857685A (en) * | 2018-12-06 | 2019-06-07 | 积成电子股份有限公司 | A kind of implementation method of MPU and FPGA expanding multiple serial ports |
| CN116991223A (en) * | 2023-09-26 | 2023-11-03 | 深圳市天龙世纪科技发展有限公司 | Low-power-consumption serial port expansion method, system and storage medium based on mobile equipment |
| CN116991223B (en) * | 2023-09-26 | 2024-01-05 | 深圳市天龙世纪科技发展有限公司 | Low-power-consumption serial port expansion method, system and storage medium based on mobile equipment |
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Application publication date: 20120704 |