CN103473192A - Field programmable gate array and soft-core processor core-based multi-UART (universal asynchronous receiver transmitter) interface extension system - Google Patents
Field programmable gate array and soft-core processor core-based multi-UART (universal asynchronous receiver transmitter) interface extension system Download PDFInfo
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Abstract
The invention mainly provides an interface extension system, and relates to the field of electronic information, in particular to a field programmable gate array and soft-core processor core-based multi-UART (universal asynchronous receiver transmitter) interface extension system. A NiosII soft-core processor is adopted as a control core of the whole field programmable gate array, and 8 paths of UART interfaces are implemented by controlling 8 paths of UART controller cores. Therefore, the requirements of a great number of pieces of serial interface equipment can be met.
Description
Technical field
The present invention relates to electronic information field, mainly be to provide a kind of Interface Expanding system, particularly a kind of many UART Universal Asynchronous Receiver Transmitter Interface Expanding system based on field programmable gate array and soft-core processor kernel.
Background technology
Embedded system is more prevalent, take 51, ARM, DSP etc. remain the main flow of low-end market as main processor, that many UART Universal Asynchronous Receiver Transmitter (UART) interface has is simple to operate, reliable operation, antijamming capability is strong, transmission range is far away characteristics, is widely used in devices communicating.In embedded system, sometimes printer, GPS, GPRS, shooting is first-class need to be connected on the UART interface simultaneously.And existing processor only provides limited UART interface, can not meet the requirement of a large amount of serial interface devices, therefore greatly limited the performance expansion of system.
Summary of the invention
In order to solve the problem of prior art, the invention provides a kind of many UART Universal Asynchronous Receiver Transmitter Interface Expanding system based on field programmable gate array and soft-core processor kernel, it adopts the control core of Nios II soft-core processor as whole field programmable gate array (FPGA), realize 8 road UART interfaces by controlling 8 road UART controller kernels, can meet the requirement of a large amount of serial interface devices.
The technical solution adopted in the present invention is as follows:
A kind of many UART Universal Asynchronous Receiver Transmitter Interface Expanding system based on field programmable gate array and soft-core processor kernel comprises:
Nios II soft-core processor, as the key control unit of whole field programmable gate array;
The sdram controller kernel, realize the interface of outside SDRAM chip;
Serial memory controller kernel, realize the interface of field programmable gate array configuring chip;
Support the kernel of JTAG agreement, realize the debugging of the JTGA interface of field programmable gate array;
The universal asynchronous receiving-transmitting transmitter kernel, realize the universal asynchronous receiving-transmitting transmitter interface;
Avalon inner exchanging bus, for being connected of Nios II soft-core processor and each On-Chip peripheral interface kernel.
Adopt 8 universal asynchronous receiving-transmitting transmitter kernels, realized 8 road universal asynchronous receiving-transmitting transmitter interfaces.
The function of its each ingredient of the present invention is as follows:
1. Nios II soft-core processor: adopt the highest Nios II/f kernel of Altera performance, comprise the following functions module: 32 general-purpose registers and 6 control registers, arithmetic logic unit, user logic interface, abnormal controller, interruptable controller, data bus and instruction bus, Data Cache and Instruction Cache, JTAG debugging module and tightly coupled data, instruction memory interface.Above resource can meet designing requirement of the present invention, each functional module can be according to demand Quartus II software by Altera carry out cutting;
2. sdram controller kernel: the sdram controller kernel provides the Avalon interface of the outer SDRAM chip of a brace, and processes all SDRAM protocol requirements.Sdram controller has the settings such as different pieces of information width (8,16,32 or 64), different memory size and multi-disc selection, and can select and the outer Avalon three state device shared address of other sheet and data bus.The effect of SDRAM chip is the software code of operation Nios II system;
3. serial memory controller (EPCS) controller kernel: EPCS controller kernel allows Nios II system access Altera EPCS series arrangement device.Therefore the EPCS controller carries the Boot-Loader code, allows the user can be program code stored in the EPCS device.The EPCS device can be stored the configuration data of FPGA, and automatically completes the configuration to FPGA when powering on;
4. support the kernel of JTAG agreement: realize the serial communication between PC and Nios II system with the JTAG kernel of Avalon interface, for the debugging to the FPGA program;
5. UART kernel: the UART interface is a character type peripherals commonly used, and its data are carried out with form and the external world of RS-232 agreement alternately.Provide the communication mode of serial character stream with the UART kernel of Avalon interface for the embedded system on FPGA and external unit.Kernel is carried out RS-232 agreement sequential, and adjustable baud rate is provided.The user configures parity check bit, position of rest and data bit voluntarily.The UART kernel provides a simple Avalon from control unit interface, and this interface allows Nios II processor to communicate by read-write register and UART kernel;
6. Avalon inner exchanging bus: the Avalon switching bus is a kind of interconnection mechanism that connects on-chip processor and various peripheral hardwares in programmable system on chip.It has defined signal type and the sequential relationship of communicating by letter between main and subordinate node, and the peripheral module that makes the user to select oneself or design easily is connected on Nios II system by the Avalon bus.
The beneficial effect that technical scheme provided by the invention is brought is:
The present invention adopts FPGA to be expanded the UART interface, can effectively address the above problem.FPGA, as a kind of high speed, flexible, reliable programming device, has not only improved integrated level, dirigibility, the reliability of short run system, and has reduced construction cycle and the cost of product.A kind of many UART Interface Expanding method based on FPGA Nios II kernel of the present invention, adopted the SOPC(programmable system on chip) method for designing developed Nios II system, can be transplanted to easily in the fpga chip of different model.In addition, if carry out more UART Interface Expanding, only need do a small amount of change to Nios II system and get final product.
The accompanying drawing explanation
The system architecture figure that Fig. 1 is a kind of many UART Universal Asynchronous Receiver Transmitter Interface Expanding system based on field programmable gate array and soft-core processor kernel of the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
Embodiment mono-
Accompanying drawing is the Nios II system architecture diagram of a kind of many UART Interface Expanding method based on FPGA Nios II kernel of the present invention, comprising: Nios II soft-core processor, sdram controller kernel, EPCS controller kernel, JTAG kernel, 8 UART kernels, Avalon inner exchanging bus.
As accompanying drawing 1, a kind of many UART Universal Asynchronous Receiver Transmitter Interface Expanding system based on field programmable gate array and soft-core processor kernel of the present embodiment comprises:
Nios II soft-core processor, as the key control unit of whole field programmable gate array;
The sdram controller kernel, realize the interface of outside SDRAM chip;
Serial memory controller kernel, realize the interface of field programmable gate array configuring chip;
Support the kernel of JTAG agreement, realize the debugging of the JTGA interface of field programmable gate array;
The universal asynchronous receiving-transmitting transmitter kernel, realize the universal asynchronous receiving-transmitting transmitter interface;
Avalon inner exchanging bus, for being connected of Nios II soft-core processor and each On-Chip peripheral interface kernel.
In the present embodiment, adopt 8 universal asynchronous receiving-transmitting transmitter kernels, realized 8 road universal asynchronous receiving-transmitting transmitter interfaces.
Concrete configuration, connected mode and the development process of this each kernel module of Nios II system is as follows:
1. Nios II kernel: select the kernel of Nios II/f type, reseting vector is set and is arranged in the EPCS device, exception vector is arranged in the SDRAM device; The size of Instruction Cache and Data Cache respectively is set to the 4K byte;
2. sdram controller kernel: the data width that sdram controller is set is 16, can external a slice sdram controller, and row address line is set to 12, and column address conductor is set to 8.Sdram controller is connected to command port and the FPDP of Nios II kernel by the Avalon bus;
3. EPCS controller kernel: this kernel is connected to command port and the FPDP of Nios II kernel by the Avalon bus;
4. JTAG kernel: the degree of depth that the read-write FIFO of this kernel is set is all 64 bytes, and the JTAG kernel is connected to the FPDP of Nios II kernel by the Avalon bus;
5. UART kernel: set gradually 8 UART kernels according to concrete serial device, each UART kernel sets gradually the parameters such as check bit, data bit, position of rest, baud rate.Each UART kernel is connected to the FPDP of Nios II kernel by the Avalon bus;
6. next each kernel module carries out the distribution of interrupt priority level after connecting, and is specially: the JTAG kernel is set to 0 grade of interruption (priority is the highest), and EPCS controller kernel is set to 1 grade of interruption, and it is 2-9 grades of interruptions that 8 UART kernels set gradually;
7. next distribute the offset address of peripheral hardware kernel in Nios II system in each sheet, this process is distributed automatically by Altera software;
8. carry out the setting of Nios II system clock, the clock that Nios II system is set is 100MHz;
9. after all kernel module settings connecting, by Altera software, compiled, thereby generated a Nios II system.
So far complete the exploitation of Nios II system of the present invention, realized 8 road UART interfaces.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (2)
1. the many UART Universal Asynchronous Receiver Transmitter Interface Expanding system based on field programmable gate array and soft-core processor kernel comprises:
Nios II soft-core processor, as the key control unit of whole field programmable gate array;
The sdram controller kernel, realize the interface of outside SDRAM chip;
Serial memory controller kernel, realize the interface of field programmable gate array configuring chip;
Support the kernel of JTAG agreement, realize the debugging of the JTGA interface of field programmable gate array;
The universal asynchronous receiving-transmitting transmitter kernel, realize the universal asynchronous receiving-transmitting transmitter interface;
Avalon inner exchanging bus, for being connected of Nios II soft-core processor and each On-Chip peripheral interface kernel.
2. a kind of many UART Universal Asynchronous Receiver Transmitter Interface Expanding system based on field programmable gate array and soft-core processor kernel according to claim 1, it is characterized in that, it has adopted 8 universal asynchronous receiving-transmitting transmitter kernels, has realized 8 road universal asynchronous receiving-transmitting transmitter interfaces.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110377548A (en) * | 2019-06-28 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of address space multiplexing method, device and multiplexer |
| CN112395230A (en) * | 2020-12-21 | 2021-02-23 | 太原智林信息技术股份有限公司 | UART interface extension circuit based on programmable logic device |
| CN112965689A (en) * | 2021-02-26 | 2021-06-15 | 西安微电子技术研究所 | Distributed asynchronous FIFO data interaction method based on source synchronization and FIFO structure |
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| CN102331733A (en) * | 2010-07-14 | 2012-01-25 | 中国科学院沈阳计算技术研究所有限公司 | Numerical control system logic controller on basis of system on programmable chip and implementing method thereof |
| CN102541799A (en) * | 2010-12-17 | 2012-07-04 | 西安奇维测控科技有限公司 | Method for realizing multi-serial-port extension by using FPGA (field programmable gate array) |
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| CN101135889A (en) * | 2007-09-30 | 2008-03-05 | 重庆邮电大学 | EPA on-site controller based on SOPC |
| CN102331733A (en) * | 2010-07-14 | 2012-01-25 | 中国科学院沈阳计算技术研究所有限公司 | Numerical control system logic controller on basis of system on programmable chip and implementing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110377548A (en) * | 2019-06-28 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of address space multiplexing method, device and multiplexer |
| CN112395230A (en) * | 2020-12-21 | 2021-02-23 | 太原智林信息技术股份有限公司 | UART interface extension circuit based on programmable logic device |
| CN112965689A (en) * | 2021-02-26 | 2021-06-15 | 西安微电子技术研究所 | Distributed asynchronous FIFO data interaction method based on source synchronization and FIFO structure |
| CN112965689B (en) * | 2021-02-26 | 2023-05-09 | 西安微电子技术研究所 | Distributed asynchronous FIFO data interaction method and FIFO structure based on source synchronization |
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