CN102567280B - Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array) - Google Patents
Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array) Download PDFInfo
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Abstract
A computer hardware platform design method based on a DSP (digital signal processor) and an FPGA (field programmable gate array) includes the steps: utilizing the DSP and the FPGA as a core to expand a program load module, a data storage module, an analog input module, an analog output module, a switching value input module, a switching value output module, a serial port communication module, a 1553B communication module, a reset circuit and a power circuit, so that an embedded computer hardware platform is built; and acquiring the analog quantity and the switching value, realizing high-capacity program and data storage and a complicated algorithm, realizing communication of the embedded computer hardware platform with peripherals, and controlling the embedded computer hardware platform. By the aid of the method, automatic switching of analog signal input and output is realized, switching value signal input and output are freely expanded, operating efficiency of a processor is greatly improved, systematic resources are saved, development cycle is shortened, and development cost is reduced. Another novel hardware design platform can be completed only by changing codes of the FPGA.
Description
Technical field
The invention belongs to embedded computer Hardware platform design field, be specifically related to the calculation machine Hardware platform design method that one is core based on DSP (digital signal processor) and FPGA (programmable logic device (PLD)).
Background technology
The TMS320C6713 of TI company is a high performance 32 floating type high-performance digital signal processors (DSP), its travelling speed is fast, instruction cycle reaches as high as 3.3ns, peak value arithmetic capability is 2400/1800MIPS/MFLOPS, the Embedded multiplier of 32 × 32bit.Chip internal storer adopts two levels of cache structure, and 8 stage pipeline structure, internal bus includes the program address bus of a 32bit and the program data bus of a 256bit.Outbound data bus 32bit, address bus 20bit, external address selects space CE0 ~ CE3, has 4 kinds of program load modes and EMIF expansion interface flexibly.Due to its outstanding arithmetic capability, efficiently instruction set, ip intelligent peripherals, jumbo on-chip memory and large-scale addressing capability, it is made to be particularly suitable for having arithmetic capability and memory space the application scenario of high request.
Platform commonly used by current Embedded computing machine two kinds: the first utilizes single-chip microcomputer, and the second is the DSP utilizing the models such as TMS320C24X.The first platform present circuit is complicated, and poor reliability, need the multiple element of peripheral expansion, and data-handling capacity is low, can not completes large-scale data operation, can only carry out simple algorithm; Although second method is also use DSP, hardware speed and resource are all better than the first, accurately control occasion still inadequate due to this platform speed, be still difficult to complicated algorithm and high-precision requirement at needs.When current require harsh and performance requirement to have to roll up to volume and weight, these two kinds of platforms have been difficult to the requirement adapting to the new period.
Summary of the invention
The object of the present invention is to provide a kind of computer hardware platforms method for designing based on DSP and FPGA, it is solve existing platform arithmetic speed not, is difficult to realize accurately control and volume weight to peripheral hardware and is difficult to greatly reduce satisfactory problem.
Technical solution of the present invention is:
Based on a computer hardware platforms method for designing of DSP and FPGA, its special character is, the method is:
With DSP and FPGA for core, by their extender load-on modules, data memory module, Analog input mModule, analog output module, switching input module, switching value output module, serial communication modular, 1553B communication module and reset circuit and power circuit, build embedded computer hardware platform; Realize the collection to analog quantity and switching value, realize Large Copacity program and data storage, realize complicated algorithm, realize carrying out communicating and controlling with peripheral hardware.
The above-mentioned computer hardware platforms method for designing based on DSP and FPGA, its special character is, the method specifically:
1] provide DSP and FPGA as platform core processor;
2] extender load-on module, specifically the data line of program storage FLASH, address wire are connected with the interface circuit of DSP respectively with control line; Described program storage FLASH is used for depositing user program and setting value, carries out selection capacity according to user's request, maximumly deposits 1Mword;
3] growth data memory module, specifically the data line of data-carrier store SDRAM, address wire are connected with the interface circuit of DSP respectively with control line; This module deposits the intermediate data of as many as 32Mword, in order to meet the space requirement needed for complicated algorithm;
4] expanded mode analog quantity load module, specifically described Analog input mModule comprises the logic control circuit in data line, address wire, signal conditioning circuit, analog to digital conversion circuit and FPGA sheet; DSP only need send startup acquisition, and the simulating signal of each passage input will be automatically converted into digital signal, and reads with interrupt mode notice DSP;
5] expanded mode analog quantity output module, specifically described analog output module comprises the logic control circuit in digital to analog converter, impedance inverter circuit and FPGA sheet; As long as the digital quantity exported writes DSP data bus, all the other work are completed automatically by FPGA, no longer need DSP to participate in;
6] expansion switch amount load module, specifically comprises the data line of processor, address wire, control line, the register of FPGA internal custom and photoelectric isolating circuit.In a register external input switches amount information is spliced into 16bit data-bus width, processor only need read the on-off state that this register can obtain input.
7] expansion switch amount output module, specifically comprises the data line of processor, address wire, control line, the register of FPGA internal custom, photoelectric isolating circuit and enhancing driving circuit.Use the corresponding switching value of the most-significant byte of register enable during expansion, the state of the corresponding switching value of least-significant byte, processor only need write this register and controllable switch amount output state.
8] extended serial port communication module, specifically comprises the serial ports controller UART0 ~ UART7 in FPGA sheet, clock circuit 2, photoelectric isolating circuit and level translator;
9] expand 1553B communication module, specifically comprise logic control circuit in 1553B module, coupling transformer, clock circuit 1, the data line of DSP, RT address input circuit and FPGA sheet;
The wherein completely compatible domestic and international same brand of 1553B modular design sequential, without the need to doing any hardware modifications;
10] expansion of power supply and reset circuit, specifically adopts TI company special chip TPS70445.
Above-mentioned serial ports controller UART0 ~ UART7 is built by certain mode by the inner macroelement of FPGA.Specifically, at FPGA internal needle, corresponding configuration register and status register are defined to each serial ports exactly, distribute the address determined to each register, by completing transceiving data to the read-write operation of register.
The code VHDL hardware description language of above-mentioned FPGA, compiles in the FLASH downloading to successfully and carry in FPGA sheet, without the need to Add-In storer ROM again.
The data line D [0..15] of above-mentioned DSP receives the DQ [0..15] of FLASH, and A [2..21] receives A [0..19], and AOE, AWE, CE1 receive OE, WE, CE respectively.
The data line D [0..31] of above-mentioned DSP receives the DQ [0..31] of data-carrier store SDRAM, and A [2..13] receives A [0..11], and AOE, ARE, AWE, CE0, BE0 ~ BE3 receives RAS, WE, CAS, CS, DQM0 ~ 3 respectively.
The control signal DG0 that above-mentioned FPGA sends ~ DG3 receives the control end A0 ~ A3 of MUX, and the data line D [0..11] of analog to digital converter AD receives on the fixing input signal pin IO of FPGA.
Above-mentioned the data line D [0..31] of DSP, address wire A [2..21], control signal CE0 ~ CE3, ARE, AOE, INT4 ~ 7 signals all to be introduced in FPGA as input/output signal; When extended serial port, different register addresss is specified for each serial ports, deposit communication baud rate, interrupt the degree of depth, storage depth, parity check bit and interrupt mode information; The read-write of these registers has been come by DSP.
The data line D [0..15] of above-mentioned DSP receives the data line D0 ~ D15 of 1553 modules, the input 0 ~ 4 of RT address is by delivering to the RTAD [0..4] of 1553 modules after Phototube Coupling, 1553_CS, 1553_RW, 1553_RST, 1553_ST in FPGA sheet receive on CS, RW, RST, ST respectively.
The output pin of above-mentioned power supply and reset chip TPS70445 directly receives the corresponding power end of DSP and reset terminal.
Advantage of the present invention is as follows:
(1) the present invention is based on 32 floating point number signal processors of high speed as data processing and control center, and with scale programmable logic device FPGA as assistance expansion peripheral interface circuit, interface is convenient, and expansion flexibly.Achieve the automatic conversion of simulating signal input and output, the spread of on-off model input and output.
(2) utilize VHDL language to be programmed in FPGA inside and generate serial ports controller flexibly, and the circuit decreasing peripheral use special serial ports controller, program storage and random access memory can be expanded to.Serial ports controller makes peripheral communications circuit greatly simplify, and only need write data to transmission FIFO, can automatically send during transmission.Can determine as required during reception to interrupt the degree of depth, receive FIFO size, interrupt mode etc., alleviate software work amount, greatly improve the work efficiency of processor, save system resource, shorten the construction cycle, reduce cost of development.
(3) without the need to making any amendment to hardware, only need change the code of FPGA, to system performance cutting, such as can change analog quantity and switching value number of channels, serial ports transmitting-receiving mode etc., just completing the hardware design platform that another money is brand-new.This is also an important feature of the present invention.
Accompanying drawing explanation
Fig. 1 is hardware platform block diagram of the present invention.
Embodiment
This platform have employed with DSP and FPGA as core, by extender load-on module, data memory module, Analog input mModule, analog output module, switching input module, switching value output module, serial communication modular, 1553B communication module and reset circuit and power circuit etc., realize the collection to analog quantity and switching value, realize Large Copacity program and data storage, realize complicated algorithm, to realize and peripheral hardware carries out communicating and control etc.
Design frame chart of the present invention is as shown in Figure 1:
(1) program load-on module is connected to form with the interface circuit of digital signal processor DSP respectively by the data line of figure Program storer FLASH, address wire and control line.FLASH is used for depositing user program and setting value, carries out selection capacity according to user's request, maximumly can deposit 1Mword; (2) data memory module is made up of the interface circuit of data-carrier store SDRAM and digital signal processor DSP.Data line, the address wire of SDRAM are connected with the interface circuit of digital signal processor DSP respectively with control line.This module can deposit the intermediate data of as many as 32Mword, in order to meet the space requirement needed for complicated algorithm; (3) Analog input mModule is made up of the logic control circuit in data line, address wire, signal conditioning circuit, analog to digital conversion circuit and FPGA sheet in figure.DSP only need send startup acquisition, and the simulating signal of each passage input will be automatically converted into digital signal, and reads with interrupt mode notice DSP; (4) analog output module is made up of the logic control circuit in digital to analog converter, impedance inverter circuit and FPGA sheet.As long as the digital quantity exported writes DSP data bus, all the other work are completed automatically by FPGA, no longer need DSP to participate in; (5) serial communication modular is made up of the serial ports controller UART0 ~ UART7 in FPGA sheet, clock circuit 2, photoelectric isolating circuit and level translator etc.Wherein serial ports controller UART0 ~ UART7 is built by certain mode by the inner macroelement of FPGA.The code VHDL hardware description language of FPGA, compiles in the FLASH downloading to successfully and carry in FPGA sheet, without the need to Add-In storer ROM again.The serial ports adopting VHDL to generate have can flexibly selector channel, communication baud rate, the interruption degree of depth, storage depth, parity check bit etc. are set.Both can adopt inquiry that interrupt mode also can be adopted to give DSP after external serial port data input; (6) 1553B communication module is made up of logic control circuit etc. in the data line of 1553B module, coupling transformer, clock circuit 1, DSP, RT address input circuit and FPGA sheet.The wherein completely compatible domestic and international same brand of 1553B modular design sequential, without the need to doing any hardware modifications; (7) power supply and reset circuit adopt TI company special chip TPS70445, and it has reset and power output function concurrently.
Specific works process of the present invention is:
(1) program load-on module is made up of interface circuit D [0..15], the A [2..21] of figure Program storer FLASH and digital signal processor DSP, AOE, AWE, CE1.Wherein the data line D [0..15] of DSP receives the DQ [0..15] of FLASH, and A [2..21] receives A [0..19], and AOE, AWE, CE1 receive OE, WE, CE respectively.
(2) the data line D [0..31] of DSP receives the DQ [0..31] of data-carrier store SDRAM, and A [2..13] receives A [0..11], and AOE, ARE, AWE, CE0, BE0 ~ BE3 receives RAS, WE, CAS, CS, DQM0 ~ 3 respectively.
(3) control signal DG0 ~ DG3 that FPGA sends receives the control end A0 ~ A3 of MUX, and the data line D [0..11] of analog to digital converter AD receives on the fixing input signal pin IO of FPGA.External input signal enters the input end of MUX after conditioning, is realized the channel selecting of specifying after DSP sends control signal by FPGA, and DG0 ~ DG3 is exported between 0x00 ~ 0x0f, and change just can dedicated tunnel 0 ~ 15.Passage sends sheet and selects AD_CS signal after specifying, and start analog to digital conversion signal AD_RC, the result at every turn converted is judged by the change of AD_BUSY signal.This signal is converted to look-at-me INT5 by FPGA internal logic and exports to DSP, and analog-digital conversion result is saved in corresponding registers, for knowing DSP to read.In whole process, DSP only need send enabling signal, without the need to participating in pilot process, just can realize automatic conversion.
(4) DA_CLK, DA_SDI, DA_RST, DA_CS, DA_LOADCS composition in FPGA sheet.As long as the digital quantity exported is sent by DSP data bus, all the other work are completed by FPGA.In FPGA, register interface is set, is used for depositing the value of DSP data bus.During conversion, first send chip selection signal DA_CS, under the effect of clock DA_CLK, give digital to analog converter DA by DA_SDI after the parallel signal of DSP being transformed into serial signal by FPGA and complete output.Export and after impedance transformation, give external unit, in order to strengthen driving force;
(5) signals such as the data line D [0..31] of DSP, address wire A [2..21], control signal CE0 ~ CE3, ARE, AOE, INT4 ~ 7 are all introduced in FPGA as input/output signal.When extended serial port, different register addresss is specified for each serial ports, deposit communication baud rate, interrupt the information such as the degree of depth, storage depth, parity check bit, interrupt mode.The read-write of these registers has been come by DSP.The code VHDL hardware description language of FPGA, compiles in the FLASH downloading to successfully and carry in FPGA sheet, without the need to Add-In storer ROM again.Both can adopt inquiry that interrupt mode also can be adopted to give DSP after external serial port data input;
(6) the data line D [0..15] of DSP receives the data line D0 ~ D15 of 1553 modules, the input 0 ~ 4 of RT address is by delivering to the RTAD [0..4] of 1553 modules after Phototube Coupling, 1553_CS, 1553_RW, 1553_RST, 1553_ST in FPGA sheet receive on CS, RW, RST, ST respectively.The work schedule of RW, RST, ST and CS chip selection signal during work is produced by FPGA, is completed by DSP the configuration of 1553 inside modules corresponding registers.
(7) output pin of power supply and reset chip TPS70445 directly receives the corresponding power end of DSP and reset terminal.Will according to the filter capacitor of the different choice different size of load at power end.
Claims (9)
1., based on a computer hardware platforms method for designing of DSP and FPGA, it is characterized in that, the method is:
With DSP and FPGA for core, by their extender load-on modules, data memory module, Analog input mModule, analog output module, switching input module, switching value output module, serial communication modular, 1553B communication module and reset circuit and power circuit, build embedded computer hardware platform; Realize the collection to analog quantity and switching value, realize Large Copacity program and data storage, realize complicated algorithm, realize carrying out communicating and controlling with peripheral hardware;
The method is specifically:
1] provide DSP and FPGA as platform core processor;
2] extender load-on module, specifically the data line of program storage FLASH, address wire are connected with the interface circuit of DSP respectively with control line; Described program storage FLASH is used for depositing user program and setting value, carries out selection capacity according to user's request, maximumly deposits 2Mbit;
3] growth data memory module, specifically the data line of data-carrier store SDRAM, address wire are connected with the interface circuit of DSP respectively with control line; This module deposits the intermediate data of as many as 64Mbit, in order to meet the space requirement needed for complicated algorithm;
4] expanded mode analog quantity load module, specifically described Analog input mModule comprises the logic control circuit in data line, address wire, signal conditioning circuit, analog to digital conversion circuit and FPGA sheet; DSP only need send startup acquisition, and the simulating signal of each passage input will be automatically converted into digital signal, and reads with interrupt mode notice DSP;
5] expanded mode analog quantity output module, specifically described analog output module comprises the logic control circuit in digital to analog converter, impedance inverter circuit and FPGA sheet; As long as the digital quantity exported writes DSP data bus, all the other work are completed automatically by FPGA, no longer need DSP to participate in;
6] expansion switch amount load module, specifically comprises the data line of DSP, address wire, control line, the register of FPGA internal custom and photoelectric isolating circuit; In a register external input switches amount information is spliced into 16bit data-bus width, DSP only need read the on-off state that this register can obtain input;
7] expansion switch amount output module, specifically comprises the data line of DSP, address wire, control line, the register of FPGA internal custom, photoelectric isolating circuit and enhancing driving circuit; Use the corresponding switching value of the most-significant byte of register enable during expansion, the state of the corresponding switching value of least-significant byte, DSP only need write this register and controllable switch amount output state;
8] extended serial port communication module, specifically comprises the serial ports controller UART0 ~ UART7 in FPGA sheet, clock circuit 2, photoelectric isolating circuit and level translator;
9] expand 1553B communication module, specifically comprise logic control circuit in 1553B module, coupling transformer, clock circuit 1, the data line of DSP, RT address input circuit and FPGA sheet;
The wherein completely compatible domestic and international same brand of 1553B modular design sequential, without the need to doing any hardware modifications;
10] expansion of power supply and reset circuit, specifically adopts TI company special chip TPS70445.
2. according to claim 1 based on the computer hardware platforms method for designing of DSP and FPGA, it is characterized in that: described serial ports controller UART0 ~ UART7 is built by certain mode by the inner macroelement of FPGA, specifically, at FPGA internal needle, corresponding configuration register and status register are defined to each serial ports exactly, the address determined is distributed, by completing transceiving data to the read-write operation of register to each register.
3. according to claim 2 based on the computer hardware platforms method for designing of DSP and FPGA, it is characterized in that: the code VHDL hardware description language of described FPGA, compile in the FLASH downloading to successfully and carry in FPGA sheet, without the need to Add-In storer ROM again.
4. according to the arbitrary described computer hardware platforms method for designing based on DSP and FPGA of claim 2 ~ 3, it is characterized in that: the data line D [0..15] of described DSP receives the DQ [0..15] of FLASH, A [2..21] receives A [0..19], and AOE, AWE, CE1 receive OE, WE, CE respectively.
5. according to claim 4 based on the computer hardware platforms method for designing of DSP and FPGA, it is characterized in that: the data line D [0..31] of described DSP receives the DQ [0..31] of data-carrier store SDRAM, A [2..13] receives A [0..11], and AOE, ARE, AWE, CE0, BE0 ~ BE3 receives RAS, WE, CAS, CS, DQM0 ~ 3 respectively.
6. according to claim 5 based on the computer hardware platforms method for designing of DSP and FPGA, it is characterized in that: the control signal DG0 that described FPGA sends ~ DG3 receives the control end A0 ~ A3 of MUX, the data line D [0..11] of analog to digital converter AD receives on the fixing input signal pin IO of FPGA.
7. according to claim 6 based on the computer hardware platforms method for designing of DSP and FPGA, it is characterized in that: the data line D [0..31] of described DSP, address wire A [2..21], control signal CE0 ~ CE3, ARE, AOE, INT4 ~ 7 signals are all introduced in FPGA as input/output signal; When extended serial port, different register addresss is specified for each serial ports, deposit communication baud rate, interrupt the degree of depth, storage depth, parity check bit and interrupt mode information; The read-write of these registers has been come by DSP.
8. according to claim 7 based on the computer hardware platforms method for designing of DSP and FPGA, it is characterized in that: the data line D [0..15] of described DSP receives the data line D0 ~ D15 of 1553 modules, the input 0 ~ 4 of RT address is by delivering to the RTAD [0..4] of 1553 modules after Phototube Coupling, 1553_CS, 1553_RW, 1553_RST, 1553_ST in FPGA sheet receive on CS, RW, RST, ST respectively.
9. according to claim 8 based on the computer hardware platforms method for designing of DSP and FPGA, it is characterized in that: the output pin of described power supply and reset chip TPS70445 directly receives the corresponding power end of DSP and reset terminal.
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103591961B (en) * | 2013-11-26 | 2016-07-06 | 北京航空航天大学 | A kind of strapdown compass navigational computer based on DSP and FPGA |
| CN106773981A (en) * | 2016-12-29 | 2017-05-31 | 贵州航天控制技术有限公司 | A kind of intelligent electric servo controller based on high speed 1553B communication interfaces |
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| CN107970031B (en) * | 2017-07-24 | 2024-03-29 | 重庆博泰医疗科技有限公司 | High-flux multichannel electrophysiological signal recording and stimulating system |
| CN109445855B (en) * | 2018-10-30 | 2021-11-16 | 天津津航计算技术研究所 | Bridging device for multi-path low-speed peripheral integration |
| CN110427634B (en) * | 2019-05-17 | 2022-08-02 | 西南交通大学 | Communication system for realizing reaction system based on FPGA and construction method thereof |
| CN110865912B (en) * | 2019-10-31 | 2024-01-16 | 天津市英贝特航天科技有限公司 | System and method for detecting serial port communication reliability of DSP (digital Signal processor) |
| CN111679995B (en) * | 2020-06-19 | 2021-09-28 | 西安微电子技术研究所 | Embedded management execution unit of space computer based on 1553B bus |
| CN112230578B (en) * | 2020-10-14 | 2022-04-19 | 西安微电子技术研究所 | Standard comprehensive control unit of dual-core multi-peripheral SoC |
| CN112505420A (en) * | 2020-11-13 | 2021-03-16 | 武汉瑞莱保科技有限公司 | Intelligent test analysis system for distribution board |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956540A (en) * | 2006-09-28 | 2007-05-02 | 北京航空航天大学 | Control system of audio-video transmission based on optical fibre transmission |
| CN101196213A (en) * | 2007-12-26 | 2008-06-11 | 北京航空航天大学 | Integrated digital control system for high temperature superconducting magnetic suspension energy accumulation flywheel magnetic bearing |
| CN101261129A (en) * | 2008-02-22 | 2008-09-10 | 北京航空航天大学 | Integrated navigation computer based on DSP and FPGA |
| CN101478670A (en) * | 2008-12-30 | 2009-07-08 | 西安交通大学 | Network real-time video collecting apparatus developed based on FPGA chip and DSP chip |
-
2010
- 2010-12-17 CN CN201010600285.4A patent/CN102567280B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956540A (en) * | 2006-09-28 | 2007-05-02 | 北京航空航天大学 | Control system of audio-video transmission based on optical fibre transmission |
| CN101196213A (en) * | 2007-12-26 | 2008-06-11 | 北京航空航天大学 | Integrated digital control system for high temperature superconducting magnetic suspension energy accumulation flywheel magnetic bearing |
| CN101261129A (en) * | 2008-02-22 | 2008-09-10 | 北京航空航天大学 | Integrated navigation computer based on DSP and FPGA |
| CN101478670A (en) * | 2008-12-30 | 2009-07-08 | 西安交通大学 | Network real-time video collecting apparatus developed based on FPGA chip and DSP chip |
Non-Patent Citations (2)
| Title |
|---|
| 基于DSP和1553B总线的嵌入式系统的设计和实现;吴迪;《万方学位论文全文数据库》;20090609;正文第9-10页，附图2.4 * |
| 基于DSP和FPGA的机载导航计算机设计;李玉寰;《万方学位论文全文数据库》;20101029;正文第2.1节 * |
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