CN110427634B - Communication system for realizing reaction system based on FPGA and construction method thereof - Google Patents
Communication system for realizing reaction system based on FPGA and construction method thereof Download PDFInfo
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Abstract
The invention discloses a communication system for realizing a reaction system based on an FPGA (field programmable gate array) and a construction method thereof, wherein the communication system comprises a computer and an FPGA board, and a receiver R1, a register, a transmitter T1, the reaction system, a transmitter T2 and frequency division modules 1-5 are integrated on the FPGA board; the construction method of the communication system comprises the following steps: step 1, designing a reaction system to realize the function of a binary adder; step 2, logically realizing a reaction system on the FPGA board, converting the logic into an algorithm code and writing the algorithm code into the FPGA board; step 3, connecting the FPGA board with a computer, a receiver and a transmitter to form a communication system; the communication system constructed by the invention can realize the communication between the reaction system on the FPGA board and other equipment, can be applied to other equipment to improve the calculation speed of additional equipment, has simple construction process and provides a new idea for the FPGA to realize the communication between the reaction system, the reaction system and the external equipment.
Description
Technical Field
The invention belongs to the technical field of hardware realization of calculation and communication, and particularly relates to a communication system for realizing a reaction system based on an FPGA (field programmable gate array) and a construction method thereof.
Background
The function of biological cells is determined by a large number of interacting biochemical reactions that are regulated by "promoting/accelerating" and "inhibiting/retarding" mechanisms, whose interactions occur through interactions that likewise occur through "promoting and inhibiting" mechanisms, the reaction system being a qualitative biological computational model, distinct from a quantitative model, that considers only a collection of elements, not a multiple collection.
Two software-based reaction system simulators, namely brsim/webrmim and HERESY, exist at present, the brsim/webrmim simulator is software designed by adopting Haskell language, and depends on a CPU to complete calculation, so that the system has a user-friendly web interface, and also provides some simple model checking and analyzing options, and the brsim/webrmim is the fastest available Central Processing Unit (CPU) -based simulator at present; the HERESY simulator runs in a Graphic Processing Unit (GPU) with a Compute Unified Device Architecture (CUDA), the GPU is not limited to image processing any more due to the introduction of the CUDA, has general processing capability and becomes a general processor similar to the CPU, and the GPU has large-scale parallel threads, is higher in operation speed by 1-2 orders of magnitude than the CPU, is particularly suitable for large-scale reaction systems with hundreds of reactions and has a slower version running in the CPU; since the program runs on the CPU/CUDA-GPU, the software program may be referred to as a "CPU/CUDA-GPU based implementation".
The appearance of the FPGA makes 'algorithm hardware' become a reality, the model function described in the FPGA is finally hardened into a digital circuit, the model function can correspond to a special digital circuit, and the model design based on the FPGA is called 'hardware realization of the model' so as to be distinguished from software realization based on a CPU/CUDA-GPU; the outstanding advantage of FPGA realization is that the operation speed is extremely high and can reach 10 8 Step/second, the acceleration ratio of CPU/CUDA-GPU is 10 5 On the left and right sides, the CPU/CUDA-GPU-based reaction system simulation tool is low in operation speed and difficult to cope with simulation of a large-scale reaction system, the FPGA has parallel processing capacity, the reaction system is developed on the FPGA, the calculation speed of the reaction system can be greatly accelerated, and the simulation tool has important significance for simulation and realization of a large-scale reaction system.
The invention adopts UART as the communication protocol of the reaction system, develops a corresponding communication device and realizes the communication between the FPGA reaction system and a computer.
Disclosure of Invention
The invention aims to provide a communication system for realizing a reaction system based on an FPGA (field programmable gate array), so as to realize the hardware realization of the reaction system on the FPGA, improve the calculation speed of the reaction system, establish communication between the reaction system realized by the hardware and external equipment and lay a foundation for the practical application of the reaction system realized by the hardware.
The invention also aims to provide a communication system construction method for realizing the reaction system based on the FPGA, which can simply realize the function of the reaction system on an FPGA board, and the FPGA board can establish communication with the outside, thereby realizing other reaction systems for the FPGA board and providing a new idea for practical application.
The technical scheme adopted by the invention is that the communication system for realizing the reaction system based on the FPGA comprises a computer and an FPGA board which are in signal connection, wherein a receiver R1, a register, a transmitter T1, the reaction system, a transmitter T2 and frequency division modules 1-5 are arranged on the FPGA board;
an rx port of the receiver R1 is connected with a computer signal, an rx _ data port of the receiver R1 is respectively connected with input ends of a plurality of registers, and a clock _ re end of the receiver R1 is connected with an edge detection port of the frequency division module 1;
the output ends of the plurality of registers are connected with a tx _ data [7.0] end of a transmitter T1, a clock _ tr end of the transmitter T1 is connected with an edge detection port of a frequency dividing module 2, a tx _ en port of a transmitter T1 is connected with an edge detection port of a frequency dividing module 3, and a tx end of a transmitter T1 is connected with an input port e0in of the reaction system;
a clock port clk of the reaction system is connected with an edge detection port of the frequency division module 4, and an output port E of the reaction system is connected with a tx _ data port of the transmitter T2;
a tx _ en port of the transmitter T2 is connected with an edge detection port of the frequency division module 5, a clock _ tr port of the transmitter T2 is connected with an edge detection port of the frequency division module 1, and a tx port of the transmitter T2 is connected with a computer;
the state signal state is respectively connected with a state port tr _ state of the transmitter T1, a state port tr _ state of the transmitter T2 and a state port of the reaction system, and besides the clk port of the reaction system, the clk ports of the other modules are connected with the FPGA on-board crystal oscillator clock.
Furthermore, when the frequency of the computer sending data is v, the frequency division module 2 adjusts the frequency of the data sent by the transmitter T1 to be v
The frequency division module 4 adjusts the calculation frequency of the reaction system to
The frequency division block 5 adjusts the frequency at which the transmitter T2 transmits data to v.
The communication system construction method for realizing the reaction system based on the FPGA comprises the following steps:
setting a reaction system R ═ S n ,B n ) Satisfies B n ＝{a ij |0≤j＜i≤n}∪{b i I is more than or equal to 1 and less than or equal to n, and a reaction set B n Has a limited range of action S n ；
Using a finite set S n ＝{e n ,…,e m ,…,e 1 ,e 0 The subset of the n-bit binary numbers represents n-bit binary numbers, m is a variable representing the number of the binary numbers, m is more than or equal to 1 and less than or equal to n, and e is used when the m-th bit value of the n-bit binary numbers is 1 m Meaning that the value 0 is expressed without using any symbol, e 0 Is a successor function representing the add 1 operation;
reaction a ij ＝({e i },{e j },{e k H) where the integers i, j satisfy 0. ltoreq. j < i. ltoreq. n, reaction a ij In the expression of (1) { e } i Denotes reaction a ij The i-th bit of the n-bit binary number of { e } an inhibitor j Denotes the j-th bit of an n-bit binary number, the product { e } k Represents the k-th bit of an n-bit binary number; reaction a ij Description of the function ofComprises the following steps: if the ith bit value of the n-bit binary number is 1 and the j bit value lower than the ith bit is 0, the ith bit can keep the value of 1 no matter whether the subsequent 1 adding operation is carried out or not;
reaction b i ＝({e 0 ,…,e i-1 },{e j },{e i H) where the integer i satisfies 1. ltoreq. i.ltoreq.n, reaction b) i In the expression of (1) { e } 0 ,…,e i-1 Denotes reaction b i 0 th to i-1 th bits of the n-bit binary number, inhibitor { e } j Denotes the j-th bit of an n-bit binary number, the product { e } i Denotes the ith bit of an n-bit binary number; reaction b i The function of (a) is described as: when the bit values from 1 st bit to i-1 st bit of the n-bit binary number are all 1, the bit value of the ith bit is 0, and the 1 adding operation exists, the value of the ith bit is changed into 1 after the 1 adding operation, and the values of the rest bits are changed into 0;
setting an updating process of a new value of a register on the FPGA, setting a code according to the updating process, creating a reaction system, and sequentially connecting a receiver R1, the register, a transmitter T1 and the reaction system to realize the realization of the reaction system on an FPGA board;
and 3, connecting the input end of the receiver R1 with a computer, and setting a transmitter T2 to return the calculation result of the reaction system to the computer, so that the communication between the reaction system and the computer is realized by FPGA hardware, and the construction of a communication system is completed.
Further, the updating process of the new value of the register in step 2 is as follows:
(1) for the first bit E [ 0] of the register]Is prepared from E [0]And the old value of (d) and the output signal e of the receiver R1 0 After XOR calculation, assign value to E [0]；
(2) For the second bit E [1 ] of the register]Output signal e of receiver R1 0 And E [ 0]]And the old value of (d) to obtain a new input signal e 0 new Then e is added 0 new And E [1 ]]XOR the old value to E [1 ]]；
(3) For the nth bit E [ n-1 ] of the register]First, a new value e of the nth bit input signal is calculated 0 new (n-1) Then e is added 0 new (n-1) And E [ n-1 ]]XOR the old values to E [ n-1 ]]。
Further, the time when the receiver R1 receives data is the midpoint of the data maintaining period when the computer sends data.
Further, the working process of the receiver R1 is divided into 4 states of idle, start, sampling and stop, wherein the idle state waits for and detects a data transmission signal, the start state processes a start bit, the sampling state processes an n-bit data bit, and the stop state processes an end bit.
Further, the start bit and the end bit of the transmitter T1 are both 0.
The invention has the beneficial effects that: 1. the FPGA implementation method of the reaction system is provided, a way of implementing the reaction system by adopting hardware is developed, and the parallel computing speed of the reaction system is improved; 2. the hardware-implemented reaction system can communicate with other devices, and provides communication conditions for practical application of the reaction system.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a state transition diagram of receiver R1.
FIG. 2 is a state transition diagram for transmitter T1 and transmitter T2.
Fig. 3 is a connection diagram of modules on the FPGA board.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The communication system for realizing the reaction system based on the FPGA comprises a computer and an FPGA board which are in signal connection, wherein the FPGA board is provided with a receiver R1, a register, a transmitter T1, the reaction system, a transmitter T2 and frequency division modules 1-5; the rx port of the receiver R1 is connected with a computer signal to receive data sent by the computer, the rx _ data port of the receiver R1 is connected with the input ends of a plurality of registers, the clock _ re end of the receiver R1 is connected with the edge detection port of the frequency division module 1, and the frequency signal generated by the frequency division module 1 is used as the working frequency of the receiver R1; the output ends of the plurality of registers are connected with a tx _ data [7.0] end of a transmitter T1, a clock _ tr end of the transmitter T1 is connected with an edge detection port of a frequency division module 2, a tx _ en port of a transmitter T1 is connected with an edge detection port of a frequency division module 3, a frequency signal generated by the frequency division module 2 serves as the working frequency of the transmitter T1, a frequency signal generated by the frequency division module 3 serves as an instruction signal for the transmitter T1 to transmit data, a tx end of a transmitter T1 is connected with an input port e0in of the reaction system, the data in the registers are transmitted to the reaction system in time sequence, and the reaction system executes the function of a binary adder according to an input data value; a clock port clk of the reaction system is connected with an edge detection port of the frequency division module 4, a frequency signal generated by the frequency division module 4 is used as a working clock of the binary adder, and an output port E of the reaction system is connected with a tx _ data port of the transmitter T2; the tx _ en port of the transmitter T2 is connected to the edge detection port of the frequency dividing module 5, the clock _ tr port of the transmitter T2 is connected to the edge detection port of the frequency dividing module 1, the frequency signal generated by the frequency dividing module 1 is used as the operating frequency of the transmitter T2, the frequency signal generated by the frequency dividing module 5 is used as the instruction signal for the transmitter T2 to transmit data, and the tx port of the transmitter T2 is connected to the computer to complete the return transmission of the calculation result; the state signal state is connected to the state port tr _ state of the transmitter T1, the state port tr _ state of the transmitter T2, and the state port of the reaction system, respectively, and the clk ports of the other modules, except the clk port of the reaction system, are connected to the crystal oscillator clock loaded on the FPGA board.
The communication system construction method for realizing the reaction system based on the FPGA comprises the following steps:
setting a reaction system R ═ S n ,B n ) In which S is n ＝{e n ,…,e m ,…,e 1 ,e 0 Is a finite set, S n Is a subset of n-bit binary numbers, the m-th bit value of the n-bit binary number being 1, e m Meaning that the value 0 is expressed without using any symbol, e 0 To represent the successor function of the add 1 operation, when e 0 Is contained in the set S n When a certain subset is selected, the binary number corresponding to the subset needs to be added with 1, otherwise, the operation of adding 1 is not needed; e.g. when n is 3, set { e 3 ,e 1 Denotes that the rightmost bit of the binary number is 1, the leftmost bit is 1, and the middle bit is 0, i.e. the binary number 101;
B n ＝{a ij |0≤j＜i≤n}∪{b i i is more than or equal to 1 and less than or equal to n is reaction a ij With reaction b i Union of (A) and (B) n Has an action range of S n Reaction a ij ＝({e i },{e j },{e k H) where the integers i, j satisfy 0. ltoreq. j < i. ltoreq. n, reaction a ij In the expression of (1) { e } i Denotes reaction a ij The i-th bit of the n-bit binary number of { e } an inhibitor j Denotes the j-th bit of an n-bit binary number, the product { e } k Represents the k-th bit of an n-bit binary number; reaction a ij The function of (a) is described as: if the ith bit value of the n-bit binary number is 1 and the j bit value lower than the ith bit is 0, the ith bit can keep the value of 1 no matter whether the subsequent 1 adding operation is carried out or not;
reaction b i ＝({e 0 ,…,e i-1 },{e j },{e i H) where the integer i satisfies 1. ltoreq. i.ltoreq.n, reaction b) i In the expression of (1) { e } 0 ,…,e i-1 Denotes reaction b i Of a binary number of n bits0 th to i-1 th position, inhibitor { e j Denotes the j-th bit of an n-bit binary number, the product { e } i Represents the ith bit of an n-bit binary number; reaction b i The function of (a) is described as: when the bit values from 1 st bit to i-1 st bit of the n-bit binary number are all 1, the bit value of the ith bit is 0, and the 1 adding operation exists, the value of the ith bit is changed into 1 after the 1 adding operation, and the values of the rest bits are changed into 0;
setting an updating process of a new value of a register on the FPGA, setting a code according to the updating process, creating a reaction system, and sequentially connecting a receiver R1, the register, a transmitter T1 and the reaction system to realize the realization of the reaction system on an FPGA board; when the new value of a certain bit of the register is 1, triggering the reaction system to perform the operation of adding 1, otherwise, not performing the operation of adding 1;
the reaction system functions are described as follows: when there is e 0 Adding 1 to the reaction system, otherwise, keeping the numerical value of the reaction system unchanged, and using e to adapt to the realization of FPGA 0 1 denotes e 0 Exist of e 0 0 represents e 0 Absent, the function of the reaction system is described as: when e is 0 When 1 is added to the binary adder, when e 0 The binary adder holds the value when 0, and for each bit of the n-bit binary number, the value is 1 if the bit is present and 0 if the bit is not present, i.e., in the reaction system, the presence of a bit is represented by the value 1 and the absence of a bit is represented by the value 0.
Designing a logic trigger response system in FPGA to add 1 operation, using an n-bit register with an initial value of 0 to store an input value of the response system, and using a 1-bit variable e 0 As input signal for the reaction system, if e 0 1 for 1 binary adder plus 1, if e 0 The binary adder keeps its value unchanged 0.
The new value of the register is obtained by operating each bit of the register, and the specific operation process is as follows:
(1) to pairIn the first bit E [ 0] of the register]Is prepared from E [0]And the old value of (d) and the output signal e of the receiver R1 0 After XOR calculation, assign value to E [0]；
(2) For bit 2E [1 ] of register E]Existence of a bit E [1 ]]Low bit E [0]At this time, the input signal e of the receiver R1 is firstly 0 And E [ 0]] Old age Then, after the addition with E [1 ]]The exclusive or is calculated,
E[1]the variation of the value depends on E [ 0]]And e 0 Value of (A), if E [ 0]]And e 0 Is 1 at the same time, then E [1 ]]Is changed, otherwise E [1 ]]The value of (d) remains unchanged;
(3) for the nth bit E [ n-1 ] of register E]Calculate e 0 new 1 ＝e Old 0 &E[0] Old age ，…，e 0 new (n-1) ＝e 0 new (n-2) &E[n-2] Old age Then, then
The operation of each bit of the register can be realized by an algorithm, and the pseudo code of the algorithm is as follows:
step 3, connecting the output end of the computer with the input end of the receiver R1 on the FPGA board, and connecting the output end of the transmitter T2 with the computer, so that the internal data of the computer is input into the FPGA board for calculation, and the FPGA board sends the calculation result back to the communication process of the computer, thereby realizing the communication between the reaction system hardware and the external equipment, and laying a foundation for the practical application of the reaction system hardware; meanwhile, after the reaction system is calculated, the calculation result is returned to the computer for displaying, so that the calculation result can be conveniently and visually observed, and the observation result in a complicated FPGA hardware debugging process is avoided.
The operations of receiving data by a receiver R1, sending data by a sender T1, adding 1 to a reaction system, sending a counting result of the reaction system back to a computer and the like are triggered at the rising edge of an FPGA on-board crystal oscillator clock.
The data frames transmitted by the receiver R1 and the transmitter T1 have n +2 bits, including n bit data bits, 1 start bit and 1 end bit, wherein n is more than or equal to 5 and less than or equal to 8, the receiver R1 is a serial-in and parallel-out device, and the transmitter T1 is a serial-in and serial-out device.
The computer sends the data frame to the receiver R1 bit by bit, when transmitting the start bit and the end bit, the receiver R1 does not receive, when the start bit and the end bit flow, the receiver R1 receives the n-bit data bits of the data frame in series, and then outputs the data frame in parallel to the corresponding register, and the number of the data frame is equal to the number of the register; the register sends the stored data to the reaction system through the transmitter T1, the reaction system calculates the received data frame, and the calculation result is sent back to the computer for display through the transmitter T2 after the calculation is completed.
Each time the receiver R1 receives a data frame sent by a computer, it generates a waveform, and counts the waveform with the counter 1, when the value of the counter 1 is 0, it stores the 1 st frame data into the 1 st register, when the value of the counter 1 is 1, it stores the 2 nd frame data into the 2 nd register, and so on, and uses 1 receiver R1 to receive all data frames sequentially.
The time for the receiver R1 to receive data is the midpoint of a data maintaining period when the computer sends data, the data is most stable at the moment, and the sampled data is most accurate; the baud rate of data sent by a computer is set as v, a clock with the frequency of 16v is generated on a receiver R1 through a frequency division module 1, namely, 16 cycles of 16v clocks exist in one cycle of the v clock, an edge detection signal waveform is generated at the upper edge of the 16v clock, the edge detection signal waveform is counted by a counter 2, data are collected when the count reaches 7, and after the collection of n-bit data bits of a data frame is completed, the data are sequentially stored in corresponding registers.
The register generates a waveform signal fs with the width of one crystal oscillator clock period at the rising edge of a clock waveform corresponding to the sending frequency of the register through edge detection, wherein fs is the same as the frequency of data sent by the register, a counter fs _ cnt is used for counting the waveform signal fs, when fs is 1 and fs _ cnt is 0, data stored in the first register is input to the input end of a transmitter T1, and when the count of the counter fs _ cnt is increased, data frames in the rest registers are sequentially output to a transmitter T1 in series, and so on until the serial output of all data is completed.
The transmitter T1 inputs n-bit data of 1 register at a time and outputs n-bit data in serial, the result of calculation by the reaction system is also n-bit data, the frequency of data transmission by the computer is v, so the frequency of transmission of the calculation result back to the computer must also be v, and the calculation frequency of the reaction system is v
In order to enable the reaction system to accurately receive data, the transmitter T1 needs to add a start bit and an end bit to the data input to the reaction system, and the transmitter T1 transmits the data at a frequency of
The operation process of the receiver R1 is divided into 4 states of idle, start, sample and stop, the state transition diagram of the receiver R1 is shown in fig. 1, the initial state of the receiver R1 is idle, when receiving data 0, it is converted into the start state, it is sampled in the middle of the data transmission period, if the data jump is 1, it is only disturbance, the receiver R1 returns to the idle state, otherwise, it is the data start bit, the receiver R1 keeps the start state, when the clock rising edge counter of the receiver R1 counts to 15, the data start bit transmission ends, the bit counter of the receiver R1 is increased by 1, the receiver R1 is converted into the sampling state, when the clock rising edge counter of the receiver R1 counts to 7, the bit counter is increased by 1, the exponential data bit transmission is completed, the receiver R1 is converted into the stop state, when the clock rising edge counter of the receiver R1 counts to 15, receiver R1 transitions to the leisure state; the receiver R1 is idle waiting and detecting data transfer signals, starting state processing start bit, sampling state processing n-bit data, stopping state processing stop bit.
The invention uses a finite state machine to realize the state transition of a receiver R1, when the receiver R1 receives n-bit data, the flag signal rf of the finite state machine is set to 1, the rf is 1 and can maintain 1 crystal oscillator clock cycle, when the rf is 1 and the counter rf _ cnt of the rf is 0, the receiver R1 stores the received n-bit data in a first register, when the rf is 1 and the counter rf _ cnt of the rf is 1, the receiver R1 stores the received n-bit data in a second register, and so on, the received data are respectively stored in the registers, the rf is given to the rf _ R to lead the waveform of the rf _ R to lag behind the waveform of the rf waveform by 1 main clock cycle, when the rf _ R is 1, the 1 st data is already stored in the 1 st register, and the 2 nd data is not completely received.
When rf _ r is 1, the frequency cannot be generated starting from the time when rf _ r is 1
So that the register cannot be switched into the input of transmitter T1; assuming that x data are in total, after 1 data are received, the rf 1 maintains 1 master clock period and then returns to 0, after the next data are received, the rf 1 maintains 1 master clock period and then returns to 0 again, and the steps are repeated; the value of rf toggles between 0 and 1, and rf _ r toggles between 0 and 1, just lagging the rf by 1 master clock cycle.
When rf _ r is 1, the operating state of the transmitter T1 can be switched from idle to transmission because the register already stores the 1 st data, and when rf _ r is 1 and rf _ cnt is 1, the transmitter T1 enters the transmission state, but the transmitter T1 does not start transmitting data, and it is necessary to wait for the transmission signal transmitted by the frequency dividing module 3 to arrive before starting transmitting data; when the transmitter T1 receives the transmission signal, it transmits data in the order of the start bit, n-bit data, and end bit, and when the clock rising edge counter of the transmitter T1 counts to 15, the transmission of 1-bit data is completed, the bit counter increments by 1, transmission of the next bit is started until the transmission of the end bit is completed, and the transmitter T1 goes to an idle state to wait for the next transmission signal.
The transmission process cannot be started after the transmission signal arrives because the transmission signal is divided by the main clock, the transmission signal is infinite, the counter of the transmission signal is continuously increased by 1 until the signal overflows, and then the next cycle is started; however, the data input by transmitter T1 is limited, the value of rf _ cnt does not loop, and the transmitter T1 can be enabled to perform only 1 transmit task by associating a transmit signal with the input data, so transmitter T1 enters the transmit state when rf _ r is 1 and rf _ cnt is 1, rather than switching state when fs is 1 and fs _ cnt is 0.
Fs is given to fs _ r so that fs _ r lags fs by one main clock cycle, when fs _ r is equal to 1, fs _ r _ cnt of a counter of fs _ r is added with 1, at the moment, the input end of a transmitter T1 is loaded with a 1 st register and maintains one crystal oscillator clock cycle, the invention starts to send data to a reaction system when rf _ r is equal to 1 and rf _ cnt is equal to 1, and stops sending when fs _ r is equal to 1 and fs _ r _ cnt is equal to x, the condition of stopping sending data appears circularly, but the condition of starting sending data appears only 1 time, so that the sending process is executed only 1 time and is not executed repeatedly.
According to the UART communication protocol, the transmitter T1 adds the start bit 0 and the end bit 1 to each frame of data, the response system cannot distinguish 1 in the data bits from the end bit 1, and after receiving the end bit 1, the system also performs an add-1 operation, which may cause an error in the calculation result.
The reaction system calculates the received data and stores the calculation result in an n-bit variable, sends the calculation result back to the computer through a transmitter T2, the sending frequency of the transmitter T2 is equal to the baud rate v of the computer sending data, the transmitter is switched from an idle state to an operating state when rf _ r is 1 and rf _ cnt is 1, and is switched back to the idle state when fs is 1 and fs _ r _ cnt is x + 1; the processes of receiving data by the receiver R1, transmitting data by the transmitters T1 and T2 and the like are all triggered at the rising edge of the crystal clock, and the state transition of the transmitters T1 and T2 is shown in FIG. 2.
Examples
In the implementation process, the FPGA board shown in fig. 3 is set, the FPGA board is connected with a computer to realize communication, the number n of binary digits is 8, one frame of data consists of 10 data bits, the transmission rate between the computer and the receiver R1 is 921600Baud, that is, the frequency of receiving data by the receiver R1 is 921600Hz, and the frequency of the data transmitted by the transmitter T1 is
The calculated frequency of the reaction system is
The transmitter T2 sends the calculation result back to the computer with the frequency of 921600Hz, the adopted hardware description language is Verilog, the used FPGA is Xilinx ARTIX-7xc7a35T-1cpg236c, the FPGA development board is DIGILENT BASYS 3, and the development software is Xilinx Vivado 18.2.
As can be seen from the above, 4 clocks are required in addition to the master clock, each being a 16 times transmission frequency 921600 × 16Hz clock for receiver R1, denoted as clock _ re, 11520Hz clock for transmitter T1, denoted as clock _ tr1, a computing frequency 92160Hz clock for the reactive system, denoted as clock _ com, and a transmission frequency 921600Hz clock for transmitter T2, denoted as clock _ tr 2.
1. Realizing frequency division clock setting:
a clock frequency division module clock _ frequency _ split is created in the Xilinx Vivado 18.2, the frequency of an edge _ detection port is consistent with a frequency division clock, the frequency of the edge _ detection port is only maintained for 1 main clock period as the frequency of the edge _ clock is 1, the use is more convenient, and the frequency f is required o Calculating the required frequency control word
Taking N as 32, FPGA main clock frequency fc as 100MHz as 10 8 Hz, adopting a clock rising edge triggering mode, setting a 32-bit counter to divi _ cnt, and calculating the divi _ cnt New ＝divi_cnt Old age + K when
When the signal is applied, the variable cnt _ l is set to 0, otherwise, the variable cnt _ l is set to 1, so that the frequency f of cnt _ l is between 0 and 1 o And (3) alternately changing to obtain the required clock frequency, assigning cnt _ l to divide _ clk, carrying out rising edge detection on cnt _ l, assigning the result to divide _ clken, carrying out behavior-level simulation, and storing the design after the result is confirmed to be correct.
2. Creation of receiver R1:
the receiver R1 is operative to receive data from a computer, which is used as an input value of the reaction system in subsequent operations, and since the receiver is a "serial-in parallel-out" device, its 8-bit output cannot be directly inputted to the 1-bit input terminal of the reaction system, the received data needs to be stored in a corresponding register for subsequent processing.
A receiver R1 module is created in Xilinx Vivado 18.2, named R1_ receiver, the clock _ re frequency of the receiver R1 is 16 times of the data transmission frequency 921600Hz of the computer, and the duration of each bit of data from the computer is a period corresponding to 921600Hz, namely, in the period corresponding to 921600Hz
In addition, the 1-bit data output by the computer keeps the value of 0 or 1 unchanged, thereby facilitating the receiving. The clock _ re has 16 cycles, at the starting time/ending time of the clock _ re cycle, the flag signal clock _ re _ pe is set to 1, and is maintained for 1 main clock cycle, namely 10ns, and then the clock _ re _ pe is set to 0 until the starting time/ending time of the next clock _ re cycle; the initial value of the counter 16x _ cnt is 0, and the counter 16x _ cnt is incremented by 1 after 1 clock _ re cycle. When 16x _ cnt is equal to 7 or 8, the value is most stable at the middle position of the bit width at this time, which is the best time for receiving data, because the two ends of the bit width are positions where the value varies, the value is unstable, and erroneous data may be received. When 16x _ cnt is 15, it indicates that 16 clock _ re cycles, i.e. 1 bit wide time, have elapsed, the computer has finished sending 1 bit of data, the bit counter bit _ cnt is incremented by 1, the initial value of the counter bit _ cnt is 0, and when bit _ cnt is 9, it indicates that 10 bits (1 frame) of data have been sent, where the 1 st bit is the start bit 0 and the last 1 bit is the end bit 1.
The initial state of the receiver R1 is idle, 16x _ cnt and bit _ cnt are set to 0, and when a start bit (value 0) is received, the receiver goes to the start state, and when clock _ re _ pe is 1 (1 clock _ re clock cycle is elapsed), 16x _ cnt is increased by 1; to cope with the interference, when 16x _ cnt is 7 or 8 (bit width middle position), it is checked again whether the data from the computer is 0, if not 0, it is interference and not true start bit, and the receiver R1 goes to idle state; if still 0, it indicates that it is indeed the start bit of the data frame, the receiver R1 remains in the start state, waits for 16x _ cnt to be 15, does not receive data, waits for the header of the data frame to flow, indicates that 1 frame of data arrives, and is not any bit of the 8-bit data bits, when 16x _ cnt is 15, the bit counter bit _ cnt is 0+1 to 1, the receiver R1 goes to the receive state, and similarly, when clock _ re _ pe is 1 (after 1 clock _ re clock cycle), the 16x _ cnt is incremented by 1; when 16x _ cnt is equal to 15, judging whether the value of the bit counter bit _ cnt is smaller than 8, if the bit _ cnt is smaller than 8, indicating that 8-bit data is not received, and needing to keep a receiving state; when bit _ cnt is 9, the receiver R1 goes to a stop state where data transmitted by the computer is a stop bit and is not received, and when 16x _ cnt is 15, the stop bit "flows through" and the receiver R1 goes to an idle state.
When the receiver R1 receives 8-bit data, 1-bit variable receive _ flag is set to 1, and the 1 st register a 0 The data is stored, and the receive _ flag can be used as a control signal for starting transmission of the transmitter, namely when the receive _ flag is 1, the transmitter is switched to a transmission state. The time interval between two receive _ flag-1 waveforms is 10 bits wide for the computer to transmit data, i.e., the frequency of the receive _ flag waveform is 92160 Hz. Delaying the receive _ flag by half of the corresponding period of 92160Hz, and assigning a variable receive _ flag _ r, when the receive _ flag _ r is 1, the register a 0 The data is obtained before half of 92160Hz period, so that the design can ensure that the register a is in the register 0 After the data is complete, the subsequent operation is performed to avoid data instability. The initial value of the receive _ flag signal counter receive _ flag _ cnt is 0, and when the receive _ flag is 1, 1 is added to the receive _ flag signal counter receive _ flag _ cnt. When the receive _ flag _ r is 1 and the receive _ flag _ cnt is 1, the transmitter T1 and the state control signal state of the reaction system are set to 1, and at this time, the transmitter T1 starts to transmit data to the reaction system and the reaction system starts to calculate.
3. Building a sender T1 Module
A transmitter T1 module is created in Xilinx Vivado 18.2, named T1_ transmitter, and a transmitter T1 is responsible for transmitting data in a register to a reaction system, wherein the transmission frequency is 92160Hz, which is one tenth of the data transmission frequency; the transmitter T1 always transmits 1 in an idle state, and needs to stop its operation after data transmission is completed, so a state port tr _ state is designed for the transmitter T1, and the state is accessed to the tr _ state port, when tr _ state is 1(state is 1), the transmitter T1 transmits data, when tr _ state is 0(state is 0), transmission is stopped, the receive _ flag of the receiver R1 is accessed to the transmission control terminal tx _ en of the transmitter T1, the initial state of the transmitter T1 is idle, 16x _ cnt and bit _ cnt are set to 0, when state is 1 and tx _ en is 1(receive _ flag is 1), the transmitter T1 goes to a transmission state, and when clock _ re _ pe 1 (1 clock _ re _ clock cycle is passed), 16x _ cn _ 1 is added; when 16x _ cnt is equal to 15, if bit _ cnt <9, it indicates that 10 bits of data have not been transmitted, bit _ cnt is increased by 1, and transmitter T1 remains in a transmission state; otherwise, the data transmission is completed, and the transmitter T1 goes to the idle state.
If the termination bit of the transmitter T1 is 1, after the output end of the transmitter T1 is connected to the input end of the reaction system, the reaction system cannot distinguish 1 and the termination bit in the data bits, and will regard the termination bit as input as well, and perform an operation of adding 1; to avoid this, the termination bit of the transmitter T1 was set to 0, which did not cause the reaction system to perform an add-1 operation; the transmission of transmitter T1 in the present invention does not conform to the UART protocol and is not the standard transmitter T1.
4. Setting up a reaction system
A reaction system module, named BCounterPar, is created in Xilinx Vivado 18.2 with input ports for the module: clock port clk, 1-bit data port e0in, status port state; and the output port is an 8-bit counter and E, the pseudo code of the algorithm 1 is converted into a Verilog code in a BCounterPar module, behavior simulation is carried out, and the design is saved after the result is confirmed to be correct.
5. Construct sender T2:
the task of the transmitter T2 is to send the calculation result of the reaction system back to the computer, the sending frequency is equal to the frequency 921600Hz of the data sent by the computer; a sender T2 module, named T2_ transmitter, is created in Xilinx Vivado 18.2, sender T2 being substantially identical to sender T1 with two differences: the termination bit sent by T2 is 1, and the termination bit sent by T1 is 0; the transmission frequency of the T2 is 921600Hz, the transmission frequency of the T1 is 92160Hz, which is one tenth of the transmission frequency of the T2, the T2 is a standard transmitter T1, and the realization method is the same as the T1.
6. Creating an FPGA of a reaction system with a UART function;
creating all modules instantiating 1-5 of a top-level module UART _ binarycounter of the reaction system with the UART function, connecting input and output ports among the modules according to functional requirements, completing system design, and obtaining a register transmission level model of the whole system.
7. The implementation process of the FPGA of the reaction system with the UART function comprises the following steps:
behavior simulation: inputting an analog value to a FPGA board of a reaction system with a UART function, verifying whether the output of the FPGA board meets the expectation of the reaction system and whether the function is correctly realized;
secondly, comprehensive: compiling the register transfer level model into a gate level circuit;
designing constraints: setting the frequency of a crystal oscillator clock on an FPGA board as the frequency 100MHz required by a master clock, distributing physical pins for master clock signals and distributing physical pins for data input and output ports;
and fourthly, implementation: carrying out layout and wiring according to the gate-level circuit and design constraints;
generating a bit stream file and programming devices: after the realization is finished, a bit stream (bitstream) can be generated, a bit stream file contains all design information, the bit stream file is downloaded to the FPGA for programming, actual logic connection is obtained, and the realization process is finished.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (5)
1. The communication system construction method for realizing the reaction system based on the FPGA is characterized by comprising the following steps of:
step 1, setting a reaction system, wherein the reaction system can realize the function of a binary adder;
setting a reaction system R ═ S n ,B n ) Satisfies B n ＝{a ij |0≤j＜i≤n}∪{b i I is more than or equal to 1 and less than or equal to n, and a reaction set B n Has a limited range of action S n ；
Using a finite set S n ＝{e n ,…,e m ,…,e 1 ,e 0 The subset of the n-bit binary numbers represents n-bit binary numbers, m is a variable representing the number of the binary numbers, m is more than or equal to 1 and less than or equal to n, and e is used when the m-th bit value of the n-bit binary numbers is 1 m Meaning that the value 0 is expressed without using any symbol, e 0 Is a successor function representing the add 1 operation;
reaction a ij ＝({e i },{e j },{e k H) where the integers i, j satisfy 0. ltoreq. j < i. ltoreq. n, reaction a ij In the expression of (1) { e } i Denotes reaction a ij The i-th bit of the n-bit binary number of { e } an inhibitor j Denotes the j-th bit of an n-bit binary number, the product { e } k Represents the k-th bit of an n-bit binary number; reaction a ij The function of (a) is described as: if the ith bit value of the n-bit binary number is 1 and the j bit value lower than the ith bit is 0, the ith bit can keep the value of 1 no matter whether the subsequent 1 adding operation is carried out or not;
reaction b i ＝({e 0 ,…,e i-1 },{e j },{e i H) where the integer i satisfies 1. ltoreq. i.ltoreq.n, reaction b) i In the expression of (1) { e } 0 ,…,e i-1 Denotes reaction b i 0 th to i-1 th bits of the n-bit binary number, inhibitor { e } j Denotes the j-th bit of an n-bit binary number, the product { e } i Denotes n bitsThe ith bit of the binary number; reaction b i The function of (a) is described as: when the bit values from 1 st bit to i-1 st bit of the n-bit binary number are all 1, the bit value of the ith bit is 0, and the 1 adding operation exists, the value of the ith bit is changed into 1 after the 1 adding operation, and the values of the rest bits are changed into 0;
step 2, setting a plurality of registers on the FPGA board, connecting the input ends of the registers in parallel to the output end of the receiver R1, connecting the output ends of the registers in parallel to the input end of the transmitter T1, and connecting the output of the transmitter T1 with the input end of the reaction system;
setting an updating process of a new value of a register on the FPGA, setting a code according to the updating process, creating a reaction system, and sequentially connecting a receiver R1, the register, a transmitter T1 and the reaction system to realize the realization of the reaction system on an FPGA board;
and 3, connecting the input end of the receiver R1 with a computer, and setting a transmitter T2 to return the calculation result of the reaction system to the computer, so that the communication between the reaction system and the computer is realized by FPGA hardware, and the construction of a communication system is completed.
2. The method for constructing a communication system based on an FPGA-implemented reaction system according to claim 1, wherein the updating process of the new value of the register in the step 2 is as follows:
(1) for the first bit E [ 0] of the register]Is prepared from E [0]And the old value of (d) and the output signal e of the receiver R1 0 After XOR calculation, assign value to E [0]；
(2) For the second bit E [1 ] of the register]Output signal e of receiver R1 0 And E [ 0]]And the old value of (d) to obtain a new input signal e 0 new Then e is added 0 new And E [1 ]]XOR the old value to E [1 ]]；
(3) For the nth bit E [ n-1 ] of the register]First, a new value e of the nth bit input signal is calculated 0 new (n-1) Then e is added 0 new (n-1) And E [ n-1 ]]XOR the old values to E [ n-1 ]]。
3. The communication system construction method based on the FPGA realization reaction system as recited in claim 1, wherein the time for the receiver R1 to receive the data is the midpoint of a data maintaining period when the computer sends the data.
4. The method as claimed in claim 1, wherein the receiver R1 is divided into 4 states of idle, start, sample and stop, wherein the idle state waits for and detects data transmission signal, the start state processes start bit, the sample state processes n-bit data bit, and the stop state processes end bit.
5. The communication system construction method based on the FPGA realized reaction system as recited in claim 1, wherein the start bit and the end bit of the transmitter T1 are both 0.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2017535A1 (en) * | 1969-04-17 | 1970-12-23 | The Cincinnati Milling Machine Company, Cincinnati, Ohio (V.St.A,) | Model stylus control for copy machine tools |
| EP0316036A2 (en) * | 1987-11-09 | 1989-05-17 | Lsi Logic Corporation | Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults |
| EP0320843A1 (en) * | 1987-12-17 | 1989-06-21 | Alcatel Cit | Method of and device for transmitting a digital service channel by way of the parity channel of a parity check coded digital data stream |
| JP2005159532A (en) * | 2003-11-21 | 2005-06-16 | Kitakyushu Foundation For The Advancement Of Industry Science & Technology | Communication module and communication method of wireless sensor network system |
| WO2008125670A1 (en) * | 2007-04-17 | 2008-10-23 | Xmos Ltd | Timed ports |
| CN102567280A (en) * | 2010-12-17 | 2012-07-11 | 西安奇维测控科技有限公司 | Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array) |
| CN104050390A (en) * | 2014-06-30 | 2014-09-17 | 西南交通大学 | Mobile robot path planning method based on variable-dimension particle swarm membrane algorithm |
| CN104463114A (en) * | 2014-11-28 | 2015-03-25 | 清华大学 | Method for catching images and quickly recognizing targets and embedded device |
| DE102014101754A1 (en) * | 2014-02-12 | 2015-08-13 | Infineon Technologies Ag | A SENSOR COMPONENT AND METHOD FOR SENDING A DATA SIGNAL |
| CN205811530U (en) * | 2016-07-06 | 2016-12-14 | 西南交通大学 | Route protection measure and control device based on GOOSE signal |
| CN107766286A (en) * | 2017-09-28 | 2018-03-06 | 浙江大学 | A kind of Systemon-board implementation method based on FPGA |
| CN108845537A (en) * | 2018-06-08 | 2018-11-20 | 山东超越数控电子股份有限公司 | The communication means of CPU and digital logic module in PLC system based on SOC FPGA |
| CN109164812A (en) * | 2018-10-23 | 2019-01-08 | 西南交通大学 | Mobile robot multirow is fusion enzyme numerical value film control method under a kind of circumstances not known |
| CN109614367A (en) * | 2018-11-22 | 2019-04-12 | 西南交通大学 | A kind of improved DND algorithm and its implementation method based on FPGA |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004005340A1 (en) * | 2004-02-04 | 2005-09-01 | Atmel Germany Gmbh | Method for obtaining time information, receiver circuit and radio clock |
-
2019
- 2019-05-17 CN CN201910413101.4A patent/CN110427634B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2017535A1 (en) * | 1969-04-17 | 1970-12-23 | The Cincinnati Milling Machine Company, Cincinnati, Ohio (V.St.A,) | Model stylus control for copy machine tools |
| EP0316036A2 (en) * | 1987-11-09 | 1989-05-17 | Lsi Logic Corporation | Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults |
| EP0320843A1 (en) * | 1987-12-17 | 1989-06-21 | Alcatel Cit | Method of and device for transmitting a digital service channel by way of the parity channel of a parity check coded digital data stream |
| JP2005159532A (en) * | 2003-11-21 | 2005-06-16 | Kitakyushu Foundation For The Advancement Of Industry Science & Technology | Communication module and communication method of wireless sensor network system |
| WO2008125670A1 (en) * | 2007-04-17 | 2008-10-23 | Xmos Ltd | Timed ports |
| CN102567280A (en) * | 2010-12-17 | 2012-07-11 | 西安奇维测控科技有限公司 | Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array) |
| DE102014101754A1 (en) * | 2014-02-12 | 2015-08-13 | Infineon Technologies Ag | A SENSOR COMPONENT AND METHOD FOR SENDING A DATA SIGNAL |
| CN104050390A (en) * | 2014-06-30 | 2014-09-17 | 西南交通大学 | Mobile robot path planning method based on variable-dimension particle swarm membrane algorithm |
| CN104463114A (en) * | 2014-11-28 | 2015-03-25 | 清华大学 | Method for catching images and quickly recognizing targets and embedded device |
| CN205811530U (en) * | 2016-07-06 | 2016-12-14 | 西南交通大学 | Route protection measure and control device based on GOOSE signal |
| CN107766286A (en) * | 2017-09-28 | 2018-03-06 | 浙江大学 | A kind of Systemon-board implementation method based on FPGA |
| CN108845537A (en) * | 2018-06-08 | 2018-11-20 | 山东超越数控电子股份有限公司 | The communication means of CPU and digital logic module in PLC system based on SOC FPGA |
| CN109164812A (en) * | 2018-10-23 | 2019-01-08 | 西南交通大学 | Mobile robot multirow is fusion enzyme numerical value film control method under a kind of circumstances not known |
| CN109614367A (en) * | 2018-11-22 | 2019-04-12 | 西南交通大学 | A kind of improved DND algorithm and its implementation method based on FPGA |
Non-Patent Citations (7)
| Title |
|---|
| "A particle swarm optimization based on P systems";Fen Zhou 等;《2010 Sixth International Conference on Natural Computation》;20101231;全文 * |
| "fpga实现uart串口通信";倩倩;《https://www.elecfans.com/tongxin/119/20171109577345.html》;20171231;全文 * |
| "Reconfigurable edge detection processor using Xilinx Platform Studio";B. Muralikrishna 等;《2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)》;20141231;全文 * |
| 一种内置FIFO全双工UART的设计与实现;段素蓉等;《通信技术》;20100210(第02期);全文 * |
| 基于FPGA的串口通讯设计;郭树涛等;《北京电子科技学院学报》;20061230(第04期);全文 * |
| 基于FPGA的多点温度无线采集系统;林思苗等;《电子测量技术》;20171015(第10期);全文 * |
| 基于FPGA的高速数据采集系统设计;代耀东等;《四川兵工学报》;20120625(第06期);全文 * |
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