CN110427634A - The communication system and its construction method of reaction system are realized based on FPGA - Google Patents
The communication system and its construction method of reaction system are realized based on FPGA Download PDFInfo
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Abstract
The invention discloses communication systems and its construction method that reaction system is realized based on FPGA, the communication system includes computer and FPGA plate, and receiver R1, register, transmitter T1, reaction system, transmitter T2 and frequency division module 1~5 are integrated on FPGA plate；The construction method of the communication system includes: step 1, and design reaction system realizes binary adder function；Step 2, logic realizes reaction system on FPGA plate, and is that FPGA plate is written in algorithmic code by the logical transition；Step 3, FPGA plate and computer, receiver, transmitter are connected and composed into communication system；The communication system that the present invention constructs can be realized the communication of reaction system and other equipment on FPGA plate, other equipment be can be applied to improve the calculating speed of additional equipment, building process of the invention is simple, realizes that reaction system, reaction system communicate with external equipment and provide new thinking for FPGA.
Description
Technical field
The realization technology field that the invention belongs to calculate with communicate is realized instead more particularly to one kind based on FPGA
Answer the communication system and its construction method of system.
Background technique
The function of biological cell determines by the biochemical reaction largely to interact, biochemical reaction by " promote/
The regulation of acceleration " and " inhibit/delay " mechanism, interaction are occurred by mutual influence, and this influence equally passes through
" promote and inhibit " mechanism occurs, and reaction system is a kind of qualitative biological computation model, is different from quantitative model, it only considers member
The set of element, rather than multiset.
Presently, there are brsim/WEBRSIM and HERESY two software-based reaction system emulators, brsim/
WEBRSIM simulator is the software using Haskell language design, completes to calculate by CPU, have user-friendly
Web interface, additionally provides some simple pattern checking analysis options, and brsim/WEBRSIM is most fast, available at present
Simulator based on central processing unit (CPU)；HERESY simulator is run on the figure for calculating Unified Device framework (CUDA)
Shape processing unit (GPU), the introducing of CUDA have general processing capabilities, become so that GPU is no longer limited to image procossing
A kind of general processor similar with CPU, since this kind of GPU has large-scale parallel thread, arithmetic speed ratio CPU fast 1~2
A order of magnitude is particularly suitable for the large-scale reaction system with hundreds of reactions, and there are one the slower versions for running on CPU for it
This；Since program is run on CPU/CUDA-GPU, software program can be referred to as " realization based on CPU/CUDA-GPU ".
The appearance of FPGA makes " hardware algorithm " to come true, and the model function described in FPGA is finally hardened to count
Word circuit, model function can be mapped with special digital circuit, by the modelling based on FPGA be known as " model it is hard
Part is realized ", to be different from the software realization based on CPU/CUDA-GPU；The outstanding advantages that FPGA is realized are arithmetic speed pole
Fastly, arithmetic speed can achieve 108Step/second, for CPU/CUDA-GPU speed-up ratio 105Left and right is based on CPU/CUDA-
The reaction system emulation tool arithmetic speed of GPU is slow, it is difficult to cope with the emulation of large-scale reaction system, FPGA has parallel processing energy
Power develops reaction system on FPGA, can greatly accelerate the calculating speed of reaction system, for extensive reaction system
Emulation is of great significance with realization.
Reaction system investment practical application is needed to solve communication issue, the present invention is using UART as the logical of reaction system
Believe agreement, develops corresponding communication device, realize the communication between FPGA reaction system and computer.
Summary of the invention
The purpose of the present invention is to provide a kind of communication systems that reaction system is realized based on FPGA, to realize reaction system
Hardware realization on FPGA, improves the calculating speed of reaction system, while by hard-wired reaction system and external equipment
Communication is established, is laid a good foundation for the practical application of hardware realization reaction system.
The object of the invention is also to provide a kind of communication system construction methods that reaction system is realized based on FPGA, can
Simply the function of reaction system is realized on FPGA plate, which can communicate with external world's foundation, realize it for FPGA plate
His reaction system, and be applied to actually provide new thinking.
The technical scheme adopted by the invention is that realizing the communication system of reaction system based on FPGA, including signal connection
Computer and FPGA plate, FPGA plate be equipped with receiver R1, register, transmitter T1, reaction system, transmitter T2 and
Frequency division module 1~5；
The port rx of the receiver R1 is connect with Computer signal, the port rx_data of receiver R1 respectively with it is several
The input terminal of register connects, and the end clock_re of receiver R1 is connect with the port edge detection of frequency division module 1；
The output end of several registers and the tx_data [7.0] of transmitter T1 hold and connect, the transmitter T1's
The end clock_tr is connect with the port edge detection of frequency division module 2, the port tx_en of transmitter T1 and frequency division module 3
The connection of the port edge detection, the end tx of transmitter T1 and the input port e0in connection of reaction system；
The clock port clk of the reaction system is connect with the port edge detection of frequency division module 4, reaction system
Output port E connect with the port tx_data of transmitter T2；
The port tx_en of the transmitter T2 is connect with the port edge detection of frequency division module 5, transmitter T2's
The port clock_tr is connect with the port edge detection of frequency division module 1, and the port tx of transmitter T2 is connect with computer；
The status signal state status port tr_ with the status port tr_state of transmitter T1, transmitter T2 respectively
The port the state connection of state, reaction system, other than the port clk of reaction system, the port clk of remaining module and FPGA
The connection of onboard crystal oscillator clock.
Further, when the frequency of the computer transmission data is v, transmitter T1 is sent data by frequency division module 2
Frequency is adjusted toThe calculating frequency of reaction system is adjusted to by frequency division module 4Frequency division module 5 sends out transmitter T2
The frequency of data is sent to be adjusted to v.
The communication system construction method of reaction system is realized based on FPGA, comprising the following steps:
Step 1, reaction system is set, which can be realized the function of binary adder；
Reaction system R=(S is setn,Bn) meet Bn={ aij0≤j < i≤n } ∪ { bi1≤i≤n }, react set Bn's
Sphere of action is finite aggregate Sn；
Use finite aggregate Sn={ en,L,em,L,e1,e0Subset indicate n bit, m be indicate binary number
The variable of digit, 1≤m≤n, the m place value of n bit use e when being 1mIndicate, be worth when being 0 without using any symbol into
Row expression, e0To indicate to add the successor function of 1 operation；
React aij=({ ei},{ej},{ek), wherein integer i, j meets 0≤j < i≤n, reacts aijExpression formula in it is anti-
Answer object { eiIndicate reaction aijN bit i-th bit, mortifier { ejIndicate n bit jth position, product
{ekIndicate n bit kth position；React aijFunction description are as follows: if the i-th bit value of n bit be 1, than i-th
The low j place value in position is 0, regardless of whether carry out subsequent plus 1 operation, i-th bit can retention value be 1；
React bi=({ e0,L,ei-1},{ej},{ei), wherein integer i meets 1≤i≤n, reacts biExpression formula in it is anti-
Answer object { e0,L,ei-1Indicate reaction bi0~i-1 of shown n bit, mortifier { ejIndicate n bit
Jth position, product { eiIndicate n bit i-th bit；React biFunction description are as follows: when the 1st of n bit
1 is all to the (i-1)-th place value, and i-th bit value is 0, and is existed plus when 1 operation, adds the value of i-th bit after 1 operation to become 1, remaining position
Value become 0；
Step 2, several registers are set on FPGA plate, the input terminal of register is connected in parallel on to the output of receiver R1
On end, the output end of register is connected in parallel on to the input terminal of transmitter T1, the output of transmitter T1 and reaction system input terminal connect
It connects；
The renewal process that register is newly worth is set on FPGA, code is arranged according to renewal process, creates reaction system, it will
Receiver R1, register, transmitter T1 and reaction system are sequentially connected, and realize reaction system in the realization of FPGA plate；
Step 3, the input terminal of receiver R1 is connect with computer, setting transmitter T2 returns reaction system calculated result
Computer is returned, realizes that FPGA hardware realizes the communication of reaction system and computer, completes the building of communication system.
Further, the renewal process that register is newly worth in the step 2 is as follows:
(1) for first E [0] of register, by the output signal e of the old value of E [0] and receiver R10After seeking exclusive or
It is assigned to E [0]；
(2) for the second E [1] of register, by the output signal e of receiver R10It asks with the old value of E [0] and is obtained with after
Obtain input signal e newly0 is new, then by e0 is newExclusive or is asked to be assigned to E [1] with the old value of E [1]；
(3) for n-th E [n-1] of register, the new value e of n-th input signal is first calculated0 new (n-1), then will
e0 new (n-1)Exclusive or is asked to be assigned to E [n-1] with the old value of E [n-1].
Further, the time of the receiver R1 reception data is that data maintained in the period when computer sends data
Point.
Further, the course of work of the receiver R1 is divided into idle, beginning, sampling and stops 4 kinds of states,
Middle idle state waits and detection data transmits signal, starts state processing start bit, and sample states handle n-bit data position, stop
Only state processing stop bit.
Further, the start bit of the transmitter T1 and stop bit are 0.
The beneficial effects of the present invention are: 1. propose the FPGA implementation method of reaction system, opens and employ hardware to reality
The approach of existing reaction system, improves the parallel speed of reaction system；2. hard-wired reaction system can be with other
Equipment communicates with each other, and provides communication condition for the practical application of reaction system.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is receiver R1 state transition graph.
Fig. 2 is transmitter T1 and transmitter T2 state transition graph.
Fig. 3 is the connection figure of each module on FPGA plate.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The communication system that reaction system is realized based on FPGA, computer and FPGA plate including signal connection, on FPGA plate
Equipped with receiver R1, register, transmitter T1, reaction system, transmitter T2 and frequency division module 1~5；The end rx of receiver R1
Mouthful connect with Computer signal, to receive the data that computer is sent, the port rx_data of receiver R1 respectively with several deposits
The input terminal of device connects, and the end clock_re of receiver R1 is connect with the port edge detection of frequency division module 1, divides
Working frequency of the frequency signal that module 1 generates as receiver R1；The output end of several registers and the tx_ of transmitter T1
The connection of the end data [7.0], the end clock_tr of the transmitter T1 are connect with the port edge detection of frequency division module 2,
The port tx_en of transmitter T1 is connect with the port edge detection of frequency division module 3, the frequency letter that frequency division module 2 generates
Working frequency number as transmitter T1, the frequency signal that frequency division module 3 generates are believed as the transmitter T1 instruction for sending data
Number, the end tx of transmitter T1 and the input port e0in connection of reaction system send the data in register in chronological order
To reaction system, reaction system is worth the function of executing binary adder according to the input data；The clock of the reaction system
Port clk is connect with the port edge detection of frequency division module 4, and the frequency signal that frequency division module 4 generates is as binary system
The port tx_data of the work clock of adder, the output port E and transmitter T2 of reaction system is connect；Transmitter T2's
The port tx_en is connect with the port edge detection of frequency division module 5, the port clock_tr of transmitter T2 and frequency dividing mould
The port edge detection of block 1 connects, working frequency of the frequency signal that frequency division module 1 generates as transmitter T2, point
The frequency signal that frequency module 5 generates sends the command signal of data, the port tx of transmitter T2 and computer as transmitter T2
Connection is sent with completing the return of calculated result；Status signal state respectively with the status port tr_state of transmitter T1,
The port the state connection of the status port tr_state, reaction system of transmitter T2, other than the port clk of reaction system,
The port clk of remaining module is connect with the crystal oscillator clock that FPGA plate loads.
Based on FPGA realize reaction system communication system construction method the following steps are included:
Step 1, reaction system is set, which can be realized the function of binary adder；
Reaction system R=(S is setn,Bn), wherein Sn={ en,L,em,L,e1,e0It is finite aggregate, finite aggregate Sn's
Subset indicates n bit, and the m place value of n bit uses e when being 1mIndicate, be worth when being 0 without using any symbol into
Row expression, e0To indicate to add the successor function of 1 operation, work as e0It is contained in set SnSome subset when, the subset corresponding two into
Number processed carry out plus 1 operation, on the contrary it is then without carry out plus 1 operate；Such as when taking n=3, gather { e3,e1Indicate the binary system
The position of several rightmosts is 1, and leftmost position is 1, interposition 0, i.e. binary number 101；
Bn={ aij0≤j < i≤n } ∪ { bi1≤i≤n } it is reaction aijWith react biUnion, BnSphere of action be
Sn, react aij=({ ei},{ej},{ek), wherein integer i, j meets 0≤j < i≤n, reacts aijExpression formula in reactant
{eiIndicate reaction aijN bit i-th bit, mortifier { ejIndicate n bit jth position, product { ekTable
Show the kth position of n bit；React aijFunction description are as follows: if the i-th bit value of n bit be 1, it is lower than i-th bit
J place value is 0, regardless of whether carrying out subsequent plus 1 operation, i-th bit meeting retention value is 1；
React bi=({ e0,L,ei-1},{ej},{ei), wherein integer i meets 1≤i≤n, reacts biExpression formula in it is anti-
Answer object { e0,L,ei-1Indicate reaction bi0~i-1 of shown n bit, mortifier { ejIndicate n bit
Jth position, product { eiIndicate n bit i-th bit；React biFunction description are as follows: when the 1st of n bit
1 is all to the (i-1)-th place value, and i-th bit value is 0, and is existed plus when 1 operation, adds the value of i-th bit after 1 operation to become 1, remaining position
Value become 0；
Step 2, several registers are set on FPGA plate, the input terminal of register is connected in parallel on to the output of receiver R1
On end, the output end of register is connected in parallel on to the input terminal of transmitter T1, the output of transmitter T1 and reaction system input terminal connect
It connects；
The renewal process that register is newly worth is set on FPGA, code is arranged according to renewal process, creates reaction system, it will
Receiver R1, register, transmitter T1 and reaction system are sequentially connected, and realize reaction system in the realization of FPGA plate；Work as deposit
The new value of a certain position of device be 1 when then trigger reaction system carry out plus 1 operation, it is on the contrary then without adding 1 operation；
Reaction system function is described as follows: when there are e0When reaction system carry out plus 1 operation, otherwise reaction system numerical value protect
Hold it is constant, for adapt to FPGA realization, use e0=1 indicates e0In the presence of e0=0 indicates e0It is not present, then the function of reaction system is retouched
It states are as follows: work as e0Binary adder adds 1 when=1, works as e0Binary adder retention value is constant when=0, for n bit
Each, if the position exist if value be 1, if the position there is no value be 0, i.e., in reaction system, certain position exist use 1 table of value
Show, there is no indicated with value 0 for certain position.
In FPGA design logic triggering reaction system plus 1 operation, stored using the n-bit register that initial value is 0 anti-
Answer the input value of system, 1 bit variable e0As the input signal of reaction system, if e0=1 binary adder adds 1, if e0=0
Binary adder keeps its value constant.
For the new value of register by being operated to obtain to each of register, specific operation process is as follows:
(1) for first E [0] of register, by the output signal e of the old value of E [0] and receiver R10After seeking exclusive or
It is assigned to E [0]；
(2) for the 2nd E [1] of register E, there is the position E [0] lower than position E [1], at this time first by the defeated of receiver R1
Enter signal e0With E [0]It is oldAsk with, then seeking exclusive or with E [1], E
[1] variation of value depends on E [0] and e0Value, if E [0] and e0It is all 1, then the value of E [1] changes, and otherwise the value of E [1] is kept
It is constant；
(3) for n-th E [n-1] of register E, e is calculated0 new 1=e0 is old&E[0]It is old..., e0 new (n-1)=e0 new (n-2)&E
[n-2]It is old, then
Each operation of register can realize that the pseudocode of algorithm is as follows by algorithm:
Step 3, the output end of computer is connect with the input terminal of the receiver R1 on FPGA plate, by the defeated of transmitter T2
Outlet is connect with computer, is realized and is calculated computer-internal data input FPGA plate, FPGA plate sends out calculated result
The communication process for returning to computer is sent, the communication of reaction system hardware realization and external equipment is realized, is reaction system hardware
The practical application of realization is laid a good foundation；Calculated result return computer is shown after the completion of simultaneous reactions system-computed,
Convenient for intuitively observing calculated result, cumbersome FPGA hardware debugging process observation result is avoided passing through.
Receiver R1 receives data in the present invention, transmitter T1 sends data, reaction system adds 1 operation, reaction system statistics
Number result sends back the operations such as computer and triggers at the rising edge of the onboard crystal oscillator clock of FPGA.
The data frame of receiver R1 and transmitter T1 transmission has n+2, including n-bit data position, 1 start bit and 1 end
Stop bit, wherein 5≤n≤8, receiver R1 is to seal in and go out device, and transmitter T1 is to be incorporated to go here and there out device.
Data frame is sent to receiver R1 by computer by turn, and when transmitting start bit and stop bit, receiver R1 is not connect
Receive, etc. start bits and stop bit flow through, behind the n-bit data position of receiver R1 serial received data frame, by data frame parallel output
It is stored in corresponding register, the quantity of data frame is equal to the quantity of register；The data that register is stored into pass through transmitter
T1 is sent to reaction system, and reaction system calculates received data frame, will be calculated after the completion of calculating by transmitter T2
As a result computer is sent back to be shown.
Receiver R1 it is every receive a computer send data frame, a waveform can be generated, with counter 1 to waveform into
Row counts, and when the value of counter 1 is 0, the 1st frame data are stored in the 1st register, when the value of counter 1 is 1, by the 2nd
Frame data are stored in the 2nd register, and so on, all data frames are received using 1 receiver R1 sequence.
The time that receiver R1 receives data is data maintain the period when computer sends data midpoint, and data are most at this time
Data for stabilization, sampling are the most accurate；If the baud rate that computer sends data is v, pass through frequency dividing mould on receiver R1
Block 1 generates the clock that frequency is 16v, i.e., has the period of 16 16v clocks in a cycle of v clock, in the upper of 16v clock
Edge check signal waveform is generated at, and edge detection signal waveform is counted using counter 2, is adopted when counting down to 7
Collect data, is sequentially stored into corresponding register after the completion of the n-bit data position of data frame acquires.
Register is sent at the corresponding clock waveform rising edge of frequency by Edge check at it, and generation width is a crystalline substance
Waveform signal fs, fs and register the transmission frequency of data of vibration clock cycle is identical, is believed using counter fs_cnt waveform
Number fs is counted, in fs=1 and fs_cnt=0 by the input of the data being stored in first register input transmitter T1
End, when counter fs_cnt, which is counted, to be increased, successively by the data frame Serial output in remaining register to transmitter T1, with this
Analogize until completing the Serial output of all data.
Transmitter T1 each input is the n-bit data of 1 register, is exported as the serial of n-bit data, by reaction system
Result after statistics is calculated is also n-bit data, since the frequency that computer sends data is v, so calculated result is sent back meter
The frequency of calculation machine also must be v, and the calculating frequency of reaction system isIn order to enable reaction system accurately to receive data, send out
It send device T1 to need and adds start bit and stop bit for the data of input reaction system, the frequency that transmitter T1 sends data is
The course of work of receiver R1 is divided into idle, beginning, sampling and stops 4 kinds of states, the state conversion of receiver R1
Figure as shown in Figure 1, receiver R1 original state be free time, beginning state is converted to when receiving data 0, data pass
Defeated period intermediate samples, illustrating the data only if data jump is 1 is disturbance, and receiver R1 returns idle state, is otherwise
For data start bit, receiver R1 keeps beginning state, and when receiver R1 rising edge clock counter is counted as 15, data are risen
The beginning position end of transmission, the digit counter of receiver R1 add 1, and receiver R1 is transformed into sample states, rise in receiver R1 clock
It is sampled when being counted as 7 along counter, while digit counter adds 1, exponent data position is transmitted, and receiver R1 switchs to stop
State, when receiver R1 rising edge clock counter is counted as 15, receiver R1 is changed into leisure state；Receiver R1 is empty
Not busy state waits and detection data transmits signal, starts state processing start bit, and sample states handle n-bit data, halted state
Handle stop bit.
The present invention realizes the transformation of receiver R1 state using finite state machine, when receiver R1 receives n-bit data
Afterwards, the marking signal rf of finite state machine is set into 1, rf=1 and is able to maintain that 1 crystal oscillator clock period, when the counting of rf=1 and rf
When device rf_cnt=0, the n-bit data received is stored in first register by receiver R1, when rf=1 and the counter of rf
When rf_cnt=1, the n received position data are stored in second register by receiver R1, and so on the data that will receive
It is stored in register respectively, rf is assigned to rf_r, the waveform of rf_r is made to lag 1 master clock cycle of rf waveform, work as rf_r=1
When rf=0, the 1st data have been stored in the 1st register at this time, and the 2nd data not yet receive.
It cannot be generated in rf_r=1 to be as starting point, frequency at the time of rf_r=1Transmission signal, therefore
Register cannot be accessed to the input terminal of transmitter T1；Assuming that sharing x data, after completing 1 data receiver, rf sets 1 maintenance 1
Return 0 after a master clock cycle, after next data receiver, rf is set again returns 0 after 1 maintenance, 1 master clock cycle, so
Back and forth；The value of rf jumps between 0 and 1, and rf_r is also jumped between 0 and 1, only lags 1 master clock cycle than rf.
It, can be by the working condition of transmitter T1 by sky in rf_r=1 since register has stored the 1st data
Spare time is converted to transmission, and in rf_r=1 and rf_cnt=1, transmitter T1 enters transmission state, but transmitter T1 does not start to send out
Send data, need to wait frequency division module 3 sends transmit a signal to come after could start to send data；When transmitter T1 is received
To after sending signal, data are sent according to the sequence of start bit, n-bit data and stop bit, in the rising edge clock of transmitter T1
When counter counts count to 15,1 data is sent completely, and digit counter adds 1, starts to send next bit, until stop bit has been sent
At transmitter T1 goes to idle state, waits next transmission signal.
Cannot transmit a signal to come after just start transmission process, this is because send signal be from master clock frequency dividing and
Come, send signal be it is unlimited, send signal counter constantly add 1 until overflow, then start next round circulation；However it sends out
The data for sending device T1 to input are limited, and the value of rf_cnt will not recycle appearance, will be sent signal and are connected with input data,
Transmitter T1 can be just set to only carry out 1 transmission task, so in rf—Transmitter T1 enters transmission shape when r=1 and rf_cnt=1
State, rather than in fs=1 and fs—Transition status when cnt=0.
Fs is assigned to fs-r and makes the stagnant the latter master clock cycle of fs-r ratio fs, as fs-r=1 by the counter of fs-r
Fs-r-cnt adds 1, and the input terminal of transmitter T1 has been already loaded into the 1st register and has maintained a crystal oscillator clock week at this time
Phase, the present invention is in rf—R=1 and rf—Start to send data to reaction system when cnt=1, in fs-r=1 and fs-r-cnt=x
When stop send, stop send data condition can recycle appearances, but start transmission data condition only will appear 1 time, make
Obtaining transmission process also can only execute 1 time, will not repeat.
According to UART communication protocol, transmitter T1 can add start bit 0 and stop bit 1 for every frame data, reaction system without
Method distinguishes 1 and the stop bit 1 in data bit, after receiving stop bit 1, can equally execute plus 1 operates, this meeting is so that calculated result is wrong
Accidentally, the start bit of transmitter T1 and stop bit are all set as 0 by the present invention, and avoiding stop bit is to calculate mistake caused by 1.
Reaction system calculate and calculated result is stored in n bit variable to received data, passes through transmitter T2
Calculated result is sent back into computer, the transmission frequency of transmitter T2 is equal to the baud rate v that computer sends data, and transmitter exists
rf—R=1 and rf—Working condition is gone to from idle state when cnt=1, and in fs=1 and fs—r—Cnt=x+1 goes back to idle shape
State；It is all at the rising edge of crystal oscillator clock that receiver R1, which receives data, transmitter T1 and transmitter T2 and sends the processes such as data,
The state conversion of triggering, transmitter T1 and transmitter T2 are as shown in Figure 2.
Embodiment
FPGA plate as shown in Figure 3 is set in implementation process, FPGA plate is connect with computer to realization communication, take two into
The digit n=8 of number processed, then by 10 data bit, the transmission rate between computer and receiver R1 is a frame data
The frequency that 921600Baud, i.e. receiver R1 receive data is 921600Hz, and the frequency that transmitter T1 sends data isThe calculating frequency of reaction system isCalculated result is sent back meter by transmitter T2
The frequency of calculation machine is 921600Hz, and for the hardware description language used for Verilog, the FPGA used is Xilinx ARTIX-7
Xc7a35t-1cpg236c, FPGA development board are DIGILENT BASYS 3, and exploitation software is Xilinx Vivado 18.2.
It is 16 times of transmission frequencies 921600 of receiver R1 respectively from the foregoing, it can be understood that also needing 4 clocks in addition to master clock
× 16Hz clock, is denoted as clock_re, and the 11520Hz clock of transmitter T1 is denoted as clock_tr1, the calculating frequency of reaction system
Rate 92160Hz clock is denoted as the transmission frequency 921600Hz clock of clock_com and transmitter T2, is denoted as clock_tr2.
1, frequency-dividing clock setting is realized:
Clock frequency division module clock_frequency_splitter, edge_ are created in Xilinx Vivado 18.2
The frequency of the port detection is consistent with frequency-dividing clock, since divide_clken=1 only maintains 1 master clock cycle, uses
More convenient, as needed frequency fo, calculate the frequency control word of needsTake N=32, FPGA master clock frequency
Fc=100MHz=108Hz, using rising edge clock triggering mode, 32 digit counters are divi-cnt, calculate divi-cntNewly=
divi-cntIt is old+ K, whenWhen, variable cnt-l sets 0, and otherwise cnt-l sets 1, so that cnt-l is between 0 and 1
According to frequency foAlternately change, the clock frequency needed, and cnt-l is assigned to divide_clk, cnt-l is carried out
It rises along detection, result is assigned to divide_clken, carry out behavioral scaling emulation, confirmation result correctly saves design afterwards.
2, the creation of receiver R1:
The work of receiver R1 is to receive the data from computer, these data can be used as reaction system in subsequent operation
The input value of system, since receiver is " seal in and go out " device, 8 export 1 input that cannot directly input reaction system
End, needs first by the data storage received in corresponding register, then do subsequent processing.
Create receiver R1 module in Xilinx Vivado 18.2, be named as R1_receiver, receiver R1 when
Clock clock_re frequency is 16 times of data transfer of computer frequency 921600Hz, the bits per inch evidence from computer it is lasting when
Between be the 921600Hz corresponding period, that is, existInterior, 1 data retention value 0 or 1 of computer output is not
Become, facilitates reception.Clock clock_re has 16 periods, in the initial time/finish time in clock clock_re period, will mark
Will signal clock_re_pe sets 1, and maintains 1 master clock cycle, i.e. 10ns, then clock_re_pe sets 0, until next
A clock_re period starting/finish time；Counter 16x_cnt initial value be 0, when pass through 1 clock clock_re period,
Counter 16x_cnt adds 1.As 16x_cnt=7 or 8, it is to connect that this moment, which is located at the middle position of bit wide, and numerical value is most stable
The Best Times of data are received, because the both ends of bit wide are the positions that numerical value changes, numerical value is unstable, is likely to be received the number of mistake
According to.As 16x_cnt=15, illustrate to have passed through 16 clock clock_re periods, i.e. 1 bit wide time, computer sends 1
Data finish, and digit counter bit_cnt adds 1, and the initial value of counter bit_cnt is 0, as bit_cnt=9, illustrate 10 (1
Frame) data are sent, wherein the 1st is start bit 0, last 1 is stop bit 1.
The original state of receiver R1 is the free time, and 16x_cnt and bit_cnt are set 0, after receiving start bit (value 0),
Beginning state is gone to, when clock_re_pe=1 (passing through 1 clock_re clock cycle), by 16x_cnt plus 1；In order to answer
To interference, as 16x_cnt=7 or 8 (bit wide middle position), examine whether the data from computer are 0 again, if not
0, it is not real start bit, receiver R1 goes to idle state that explanation, which is interference,；If remaining as 0, illustrate strictly data frame
Start bit, receiver R1 keeps beginning state, waits 16x_cnt=15, do not receive data, waits data frame head to flow through, table
Show the arrival of 1 frame data, is not any one in 8 data bit, as 16x_cnt=15, digit counter bit_cnt=0
+ 1=1, receiver R1 go to reception state, will equally when clock_re_pe=1 (passing through 1 clock_re clock cycle)
16x_cnt adds 1；As 16x_cnt=15, whether the value of digit counter bit_cnt is judged less than 8, if bit_cnt < 8, explanation
8 data have not been received, have needed to keep reception state；As bit_cnt=9, receiver R1 goes to halted state, at this time
The data that computer is sent are stop bits, are not received, as 16x_cnt=15, stop bit " flows through ", and receiver R1 goes to sky
Not busy state.
After receiver R1 receives 8 data, 1 bit variable receive_flag is set into the 1, the 1st register a0It is stored in number
It may be used as transmitter according to, receive_flag and start the control signal sent, is i.e. when receive_flag=1, transmitter turns
To the state of transmission.Time interval between two receive_flag=1 waveforms is the bit wide that 10 computers send data, i.e.,
The frequency of receive_flag waveform is 92160Hz.Receive_flag delay 92160Hz is corresponded into the half in period, and is assigned
Variable receive_flag_r is given, as receive_flag_r=1, register a0In half of 92160Hz corresponding period
Preceding acquisition data, in this way design may insure in register a0After complete data, subsequent operation is just carried out, in case data are unstable
It is fixed.Receive_flag event counter receive_flag_cnt initial value is 0, will as receive_flag=1
Receive_flag event counter receive_flag_cnt adds 1.As receive_flag_r=1 and receive_flag_
When cnt=1, the state control signal state of transmitter T1 and reaction system is set 1, transmitter T1 starts to send data at this time
To reaction system, reaction system starts to calculate.
3, transmitter T1 module is constructed
Transmitter T1 module is created in Xilinx Vivado 18.2, is named as T1_transmmitter, transmitter T1
Be responsible for sending reaction system for the data in register, transmissions frequency is 92160Hz, for data transmission frequencies ten/
One；Transmitter T1 always sends 1 in idle state, after data are sent completely, needs to stop its work, therefore be transmitter
T1 design point port tr_state, and state is accessed into the port tr_state, as tr_state=1 (state=1), hair
It send device T1 to send data, when tr_state=0 (state=0), stops sending, the receive_flag of receiver R1 accesses hair
It send the original state of transmission the control terminal tx_en, transmitter T1 of device T1 for the free time, 16x_cnt and bit_cnt is set 0, when
State=1 and when tx_en=1 (receive_flag=1), transmitter T1 goes to transmission state, works as clock_re_pe=1
When (passing through 1 clock_re clock cycle), by 16x_cnt plus 1；As 16x_cnt=15, if bit_cnt < 9, illustrate 10
Position data have not been sent, and bit_cnt adds 1, and transmitter T1 is maintained at transmission state；Otherwise, data are sent, transmitter
T1 goes to idle state.
If the stop bit of transmitter T1 is 1, after the input terminal of the output end access reaction system of transmitter T1, reaction system
Stop bit, can be equally considered as input by 1 and stop bit in indistinguishable data bit of uniting, carry out plus 1 operates；In order to avoid this
Situation sets 0 for the stop bit of transmitter T1, and stop bit will not cause reaction system to carry out adding 1 operation；It is sent in the present invention
The transmission of device T1 does not meet UART protocol, is not the transmitter T1 of standard.
4, reaction system is set
Reaction system module is created in Xilinx Vivado 18.2, is named as BCounterPar, the input of the module
Port is respectively as follows: clock port clk, 1 bit data end mouth e0in, status port state；Output port be 8 digit counters and E,
Verilog code is converted by the pseudocode of algorithm 1 in BCounterPar module, carries out behavior simulation, confirmation result is correct
Design is saved afterwards.
5, transmitter T2 is constructed:
The task of transmitter T2 is that the calculated result of reaction system is sent back to computer, sends frequency and computer is sent
The frequency 921600Hz of data is equal；Transmitter T2 module is created in Xilinx Vivado 18.2, is named as T2_
Transmmitter, transmitter T2 and transmitter T1 are essentially identical, and there are two differences: the stop bit that 1. T2 is sent is that 1, T1 is sent
Stop bit be 0；2. the transmission frequency of T2 is 921600Hz, the transmission frequency of T1 is 92160Hz, is that T2 sends frequency very
One of, T2 is the transmitter T1 of standard, and implementation method is identical as T1.
6, creation has the FPGA of the reaction system of UART function；
The reaction system top-level module uart_binarycounter with UART function is created, exampleization 1~5 owns
Module connects the input/output port of intermodule according to functional requirement, completes system design, obtains the register of whole system
Transmitting stage model.
7, the implementation process of the FPGA of the reaction system with UART function:
1. behavior simulation: inputting simulation value to the reaction system FPGA plate with UART function, whether verify its output
Meet the expection of reaction system, whether function is correctly realized；
2. integrating: register transfer level model is compiled as gate level circuit；
3. design constraint: crystal oscillator clock frequency is the frequency 100MHz that master clock needs on setting FPGA plate, is master clock
Signal distributes physical pin, distributes physical pin for data input output ports；
4. realizing: being laid out wiring according to gate level circuit and design constraint；
5. generating bit stream file and device programming: bit stream (bitstream), bit stream can be generated after the completion of realizing
File includes all design informations, by bit stream file download to FPGA, carries out device programming, obtains actual logic connection, complete
At the process of realization.
Each embodiment in this specification is all made of relevant mode and describes, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for system reality
For applying example, since it is substantially similar to the method embodiment, so being described relatively simple, related place is referring to embodiment of the method
Part explanation.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the scope of the present invention.It is all
Any modification, equivalent replacement, improvement and so within the spirit and principles in the present invention, are all contained in protection scope of the present invention
It is interior.
Claims (7)
1. realizing the communication system of reaction system based on FPGA, which is characterized in that the communication system includes the calculating of signal connection
Machine and FPGA plate, FPGA plate are equipped with receiver R1, register, transmitter T1, reaction system, transmitter T2 and frequency division module
1~5；
The port rx of the receiver R1 is connect with Computer signal, the port rx_data of receiver R1 respectively with several deposits
The input terminal of device connects, and the end clock_re of receiver R1 is connect with the port edge detection of frequency division module 1；
The output end of several registers and the tx_data [7.0] of transmitter T1 hold and connect, the clock_ of the transmitter T1
The end tr is connect with the port edge detection of frequency division module 2, the port tx_en of transmitter T1 and the edge of frequency division module 3
The connection of the port detection, the end tx of transmitter T1 and the input port e0in connection of reaction system；
The clock port clk of the reaction system is connect with the port edge detection of frequency division module 4, reaction system it is defeated
Exit port E is connect with the port tx_data of transmitter T2；
The port tx_en of the transmitter T2 is connect with the port edge detection of frequency division module 5, transmitter T2's
The port clock_tr is connect with the port edge detection of frequency division module 1, and the port tx of transmitter T2 is connect with computer；
Status signal state respectively with the status port tr_state of transmitter T1, transmitter T2 status port tr_state,
The port state of reaction system connects, other than the port clk of reaction system, the port clk of remaining module and the onboard crystalline substance of FPGA
The connection of vibration clock.
2. the communication system according to claim 1 for realizing reaction system based on FPGA, which is characterized in that the computer
When the frequency for sending data is v, the transmitter T1 frequency for sending data is adjusted to by frequency division module 2Frequency division module 4
The calculating frequency of reaction system is adjusted toThe transmitter T2 frequency for sending data is adjusted to v by frequency division module 5.
3. the communication system construction method of reaction system is realized based on FPGA as described in claim 1, which is characterized in that including
Following steps:
Step 1, reaction system is set, which can be realized the function of binary adder；
Reaction system R=(S is setn,Bn) meet Bn={ aij| 0≤j < i≤n } ∪ { bi| 1≤i≤n }, react set BnWork
It is finite aggregate S with rangen；
Use finite aggregate Sn={ en,L,em,L,e1,e0Subset indicate n bit, m be indicate binary number digit
Variable, 1≤m≤n, the m place value of n bit uses e when being 1mIt indicates, is worth when being 0 without using any symbol carry out table
Show, e0To indicate to add the successor function of 1 operation；
React aij=({ ei},{ej},{ek), wherein integer i, j meets 0≤j < i≤n, reacts aijExpression formula in reactant
{eiIndicate reaction aijN bit i-th bit, mortifier { ejIndicate n bit jth position, product { ekTable
Show the kth position of n bit；React aijFunction description are as follows: if the i-th bit value of n bit be 1, it is lower than i-th bit
J place value is 0, regardless of whether carrying out subsequent plus 1 operation, i-th bit meeting retention value is 1；
React bi=({ e0,L,ei-1},{ej},{ei), wherein integer i meets 1≤i≤n, reacts biExpression formula in reactant
{e0,L,ei-1Indicate reaction bi0~i-1 of shown n bit, mortifier { ejIndicate n bit jth
Position, product { eiIndicate n bit i-th bit；React biFunction description are as follows: when the 1st of n bit to the
I-1 place value is all 1, and i-th bit value is 0, and exists plus when 1 operation, adds the value of i-th bit after 1 operation to become 1, the value of remaining
Become 0；
Step 2, several registers are set on FPGA plate, the input terminal of several registers is connected in parallel on to the output end of receiver R1
On, the output end of register is connected in parallel on to the input terminal of transmitter T1, the output of transmitter T1 is connect with reaction system input terminal；
The renewal process that register is newly worth is set on FPGA, code is arranged according to renewal process, reaction system is created, will receive
Device R1, register, transmitter T1 and reaction system are sequentially connected, and realize reaction system in the realization of FPGA plate；
Step 3, the input terminal of receiver R1 is connect with computer, reaction system calculated result is returned and counted by setting transmitter T2
Calculation machine realizes that FPGA hardware realizes the communication of reaction system and computer, completes the building of communication system.
4. the communication system construction method according to claim 3 for realizing reaction system based on FPGA, which is characterized in that institute
It is as follows to state the renewal process that register in step 2 is newly worth:
(1) for first E [0] of register, by the output signal e of the old value of E [0] and receiver R10It is assigned to after seeking exclusive or
E[0]；
(2) for the second E [1] of register, by the output signal e of receiver R10It asks and is obtained afterwards newly with the old value of E [0]
Input signal e0 is new, then by e0 is newExclusive or is asked to be assigned to E [1] with the old value of E [1]；
(3) for n-th E [n-1] of register, the new value e of n-th input signal is first calculated0 new (n-1), then by e0 new (n-1)With
The old value of E [n-1] asks exclusive or to be assigned to E [n-1].
5. the communication system construction method according to claim 3 for realizing reaction system based on FPGA, which is characterized in that institute
The time for stating receiver R1 reception data is the midpoint in data maintenance period when computer sends data.
6. the communication system construction method according to claim 3 for realizing reaction system based on FPGA, which is characterized in that institute
The course of work for stating receiver R1 is divided into idle, beginning, sampling and stops 4 kinds of states, and wherein idle state is waited and detected
Data transfer signal starts state processing start bit, and sample states handle n-bit data position, and halted state handles stop bit.
7. the communication system construction method according to claim 3 for realizing reaction system based on FPGA, which is characterized in that institute
The start bit and stop bit for stating transmitter T1 are 0.
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Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2017535A1 (en) * | 1969-04-17 | 1970-12-23 | The Cincinnati Milling Machine Company, Cincinnati, Ohio (V.St.A,) | Model stylus control for copy machine tools |
| EP0316036A2 (en) * | 1987-11-09 | 1989-05-17 | Lsi Logic Corporation | Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults |
| EP0320843A1 (en) * | 1987-12-17 | 1989-06-21 | Alcatel Cit | Method of and device for transmitting a digital service channel by way of the parity channel of a parity check coded digital data stream |
| JP2005159532A (en) * | 2003-11-21 | 2005-06-16 | Kitakyushu Foundation For The Advancement Of Industry Science & Technology | Communication module and communication method of wireless sensor network system |
| US20050169230A1 (en) * | 2004-02-04 | 2005-08-04 | Atmel Germany Gmbh | Radio-controlled clock, receiver circuit and method for acquiring time information with economized receiver and microcontroller |
| WO2008125670A1 (en) * | 2007-04-17 | 2008-10-23 | Xmos Ltd | Timed ports |
| CN102567280A (en) * | 2010-12-17 | 2012-07-11 | 西安奇维测控科技有限公司 | Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array) |
| CN104050390A (en) * | 2014-06-30 | 2014-09-17 | 西南交通大学 | Mobile robot path planning method based on variable-dimension particle swarm membrane algorithm |
| CN104463114A (en) * | 2014-11-28 | 2015-03-25 | 清华大学 | Method for catching images and quickly recognizing targets and embedded device |
| DE102014101754A1 (en) * | 2014-02-12 | 2015-08-13 | Infineon Technologies Ag | A SENSOR COMPONENT AND METHOD FOR SENDING A DATA SIGNAL |
| CN205811530U (en) * | 2016-07-06 | 2016-12-14 | 西南交通大学 | Route protection measure and control device based on GOOSE signal |
| CN107766286A (en) * | 2017-09-28 | 2018-03-06 | 浙江大学 | A kind of Systemon-board implementation method based on FPGA |
| CN108845537A (en) * | 2018-06-08 | 2018-11-20 | 山东超越数控电子股份有限公司 | The communication means of CPU and digital logic module in PLC system based on SOC FPGA |
| CN109164812A (en) * | 2018-10-23 | 2019-01-08 | 西南交通大学 | Mobile robot multirow is fusion enzyme numerical value film control method under a kind of circumstances not known |
| CN109614367A (en) * | 2018-11-22 | 2019-04-12 | 西南交通大学 | A kind of improved DND algorithm and its implementation method based on FPGA |
-
2019
- 2019-05-17 CN CN201910413101.4A patent/CN110427634B/en not_active Expired - Fee Related
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2017535A1 (en) * | 1969-04-17 | 1970-12-23 | The Cincinnati Milling Machine Company, Cincinnati, Ohio (V.St.A,) | Model stylus control for copy machine tools |
| EP0316036A2 (en) * | 1987-11-09 | 1989-05-17 | Lsi Logic Corporation | Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults |
| EP0320843A1 (en) * | 1987-12-17 | 1989-06-21 | Alcatel Cit | Method of and device for transmitting a digital service channel by way of the parity channel of a parity check coded digital data stream |
| JP2005159532A (en) * | 2003-11-21 | 2005-06-16 | Kitakyushu Foundation For The Advancement Of Industry Science & Technology | Communication module and communication method of wireless sensor network system |
| US20050169230A1 (en) * | 2004-02-04 | 2005-08-04 | Atmel Germany Gmbh | Radio-controlled clock, receiver circuit and method for acquiring time information with economized receiver and microcontroller |
| WO2008125670A1 (en) * | 2007-04-17 | 2008-10-23 | Xmos Ltd | Timed ports |
| CN102567280A (en) * | 2010-12-17 | 2012-07-11 | 西安奇维测控科技有限公司 | Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array) |
| DE102014101754A1 (en) * | 2014-02-12 | 2015-08-13 | Infineon Technologies Ag | A SENSOR COMPONENT AND METHOD FOR SENDING A DATA SIGNAL |
| CN104050390A (en) * | 2014-06-30 | 2014-09-17 | 西南交通大学 | Mobile robot path planning method based on variable-dimension particle swarm membrane algorithm |
| CN104463114A (en) * | 2014-11-28 | 2015-03-25 | 清华大学 | Method for catching images and quickly recognizing targets and embedded device |
| CN205811530U (en) * | 2016-07-06 | 2016-12-14 | 西南交通大学 | Route protection measure and control device based on GOOSE signal |
| CN107766286A (en) * | 2017-09-28 | 2018-03-06 | 浙江大学 | A kind of Systemon-board implementation method based on FPGA |
| CN108845537A (en) * | 2018-06-08 | 2018-11-20 | 山东超越数控电子股份有限公司 | The communication means of CPU and digital logic module in PLC system based on SOC FPGA |
| CN109164812A (en) * | 2018-10-23 | 2019-01-08 | 西南交通大学 | Mobile robot multirow is fusion enzyme numerical value film control method under a kind of circumstances not known |
| CN109614367A (en) * | 2018-11-22 | 2019-04-12 | 西南交通大学 | A kind of improved DND algorithm and its implementation method based on FPGA |
Non-Patent Citations (7)
| Title |
|---|
| B. MURALIKRISHNA 等: ""Reconfigurable edge detection processor using Xilinx Platform Studio"", 《2014 2ND INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS)》 * |
| FEN ZHOU 等: ""A particle swarm optimization based on P systems"", 《2010 SIXTH INTERNATIONAL CONFERENCE ON NATURAL COMPUTATION》 * |
| 代耀东等: "基于FPGA的高速数据采集系统设计", 《四川兵工学报》 * |
| 倩倩: ""fpga实现uart串口通信"", 《HTTPS://WWW.ELECFANS.COM/TONGXIN/119/20171109577345.HTML》 * |
| 林思苗等: "基于FPGA的多点温度无线采集系统", 《电子测量技术》 * |
| 段素蓉等: "一种内置FIFO全双工UART的设计与实现", 《通信技术》 * |
| 郭树涛等: "基于FPGA的串口通讯设计", 《北京电子科技学院学报》 * |
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