CN108845537A

CN108845537A - The communication means of CPU and digital logic module in PLC system based on SOC FPGA

Info

Publication number: CN108845537A
Application number: CN201810585378.0A
Authority: CN
Inventors: 唐汉钊; 马双涛; 潘岩; 赵鹏
Original assignee: Shandong Chaoyue CNC Electronics Co Ltd
Current assignee: Shandong Chaoyue CNC Electronics Co Ltd
Priority date: 2018-06-08
Filing date: 2018-06-08
Publication date: 2018-11-20

Abstract

The present invention provides the communication means of CPU and digital logic module in a kind of PLC system based on SOC FPGA, it is related to field of communication technology, it is processor bus from equipment that FPGA digital logic, which is arranged, in the present invention, and building controls register and data storage area wherein, CPU is written and read these registers and memory block by data/address bus according to particular order, to realize the reliable communication with fpga logic, the control to PLC I/O device is then completed.

Description

The communication means of CPU and digital logic module in PLC system based on SOC FPGA

Technical field

The present invention relates to CPU in field of communication technology more particularly to a kind of PLC system based on SOC FPGA and Digital Logic mould The communication means of block.

Background technique

Programmable logic controller (PLC)（PLC）It is a kind of general automatic control dress developed exclusively for industry automatic control It sets.It has the characteristics that simple, easy to use high reliablity, programming, perfect in shape and function, versatility are good, and has online modification function Can, the demand in current industrial field is met well.

CPU and PLC chip are mostly discrete device in existing PLC system, and communication mode depends on device itself and mentions The interface of confession, therefore data transmission format is relatively fixed, to cause on communication efficiency and flexibility that there are some problems.Base Data processing is carried out using stone CPU part in the PLC system of SOC FPGA, and is carried out data transmission using FPGA, by setting The communication mode between CPU and fpga logic is set, system configuration scalability with higher can be made, and have high efficiency, Gao Ke concurrently The advantages of by property, the problem that task switching is complicated in traditional PLC structure that can forgo, file storage and network transmission are cumbersome.

But the distinctive flexible and changeable feature of SOC FPGA can be brought to the communication process between CPU and FPGA digital logic Unstable risk, existing communication plan is although varied, but specific aim is not strong, is not well positioned to meet PLC system Demand, therefore need a set of efficient and rational scheme and solve the problems, such as this.

Summary of the invention

In order to solve the above technical problems, the invention proposes CPU in a kind of PLC system based on SOC FPGA and number The communication means of logic module, to solve the reliability and flexibility that occur when CPU passes through bus communication with FPGA digital logic Problem.

The technical scheme is that：

The communication means of CPU and digital logic module in a kind of PLC system based on SOC FPGA,

Slave equipment of the FPGA digital logic as processor data bus is set, and construct inside it one group of control register and Data storage area, wherein the I/O device of the corresponding PLC work station in each data storage area.

CPU as bus main equipment control FPGA digital logic, when CPU wish by FPGA digital logic module to When some I/O device sends data, the control register that can be inquired in FPGA is confirmed whether that data transmit-receive can be carried out.

If not can be carried out, inquired again after waiting for a period of time.

If can carry out, by bus, into FPGA digital logic, data to be sent are written in corresponding data storage area, After the completion of the write-in of all data, the control register being reconfigured in FPGA issues the data；When fpga logic receives certain IO When the data of equipment, it is deposited into corresponding data storage area, after the completion of all data transmit-receives, then relevant control is modified and posts Storage states sign off.

When CPU inquires the data transfer ends of register discovery FPGA, i.e., the data are read.

By the above process, the integrality that ensure that data transmit-receive realizes the reliable of CPU and FPGA digital logic part Transmission, then realizes the stabilized communication with I/O device.

Detailed description of the invention

Fig. 1 is PLC word station hardware structure chart；

Fig. 2 is bus system explanatory diagram.

Specific embodiment

More detailed elaboration is carried out to the contents of the present invention below：

This method constructs enough data storage areas in FPGA digital logic and control is arranged according to the quantity of external I/O device Register, CPU is realized by reading and writing the data of memory block and register according to particular order described below and fpga logic The communication with I/O device is then realized in partial communication.

The structure of PLC system is as shown in Figure 1,1 PLC word station hardware system includes that 1 control equipment and N number of IO are set It is standby, equipment is controlled using SOC FPGA as core, and control register and data storage area are constructed in FPGA digital logic, wherein The corresponding I/O module in each data storage area, CPU pass through bus marco FPGA number as shown in Figure 2 as main control device Logic, FPGA digital logic receive CPU control as bus peripheral hardware, and the data forwarding that CPU is issued is to each I/O module, together When collect the data of I/O module and be uploaded to CPU.

The specific transmitting-receiving process of data is as follows：

CPU inquires " working condition register ", and whether confirmation FPGA digital logic can receive the control command sum number of CPU According to indicating to receive if FPGA is in idle condition, step can be carried out, otherwise wait for FPGA and enter idle state；

Data to be sent are written to corresponding " data storage area " by CPU；

CPU is to " sending buffer status register " write state flag data, to indicate depositing in which " data storage area " In valid data；

Enabled instruction is written to " work starting register " in CPU；

FPGA digital logic resets " work starting register ", " finishing receiving register " first and " receives buffer status at this time Register ", while determining there are data to be sent in which data storage area according to " sending buffer status register ", then open The valid data sent in corresponding data memory block are originated, juxtaposition " working condition register " is busy state, and data are transmitted across The operational order and data that CPU is issued no longer are responded in journey.It, will " hair when the data of a certain " data storage area " are sent completely Send buffer status register " correspond to bit clearings.

After data when a certain " data storage area " issue, before receiving the reply of I/O device, FPGA digital logic mould Block will always be in replying wait state, not retransmit the data in next " data storage area ".When receiving reply data Afterwards, it is 1 that FPGA digital logic, which will set in " receive buffer status register " bit corresponding with the memory block, and is started next The transmitting-receiving process of a " data storage area ".After waiting time-out（Timeout requirements are 1ms）, " reception is slow for FPGA digital logic setting Deposit status register " in bit corresponding with the memory block be 0, and the transmitting-receiving of next " data storage area " will be made a forcible entry into Journey.

After all " data storage area " poll transmitting-receiving processes, FPGA digital logic sets " finishing receiving register " It is 1, indicates to complete data transmit-receive, juxtaposition " working condition register " is idle state, and waiting for CPU is read；

It, can root after the completion of CPU poll " working condition register " and " finishing receiving register " confirmation data transmit-receive process Data mode is confirmed according to the instruction of " receiving buffer status register " and reads the content of needs；

CPU " will finish receiving register " after the completion of reading and reset.

Claims

1. the communication means of CPU and digital logic module in the PLC system based on SOC FPGA, which is characterized in that

In SOC system, slave equipment of the FPGA digital logic as processor data bus is set, and construct wherein one group it is special Control register and data storage area；CPU controls FPGA digital logic as the main equipment of bus, in sequence by total Line Read-write Catrol register and data storage area realize the reliable communication with FPGA digital logic, then complete to set PLC IO Standby control.

2. communication means according to claim 1, which is characterized in that

Main equipment of the CPU as processor data bus in SOC FPGA, FPGA digital logic is as bus slave, the two It is communicated by bus.

3. communication means according to claim 1, it is characterized in that be,

Building controls register so that CPU is controlled in FPGA digital logic, and the sky of 4Byte is assigned with for each register Between.

4. communication means according to claim 1, which is characterized in that

Data storage area is constructed in FPGA digital logic to cache the data from CPU and I/O device；It is every on PLC work station The data space of the corresponding 512KB of one I/O device, the data that CPU write enters the space can be forwarded to corresponding equipment, Data from the equipment can be stored to this space for CPU reading.

5. communication means according to claim 1, which is characterized in that when CPU wish by FPGA digital logic module to When some I/O device sends data, the control register in FPGA is first inquired, is confirmed whether to be able to carry out data transmission；If cannot Data transmission is carried out, then is inquired again after waiting；If being able to carry out data transmission, FPGA number is written by bus in data Corresponding data storage area in logic, the control register being reconfigured in FPGA issue the data.

6. communication means according to claim 1, which is characterized in that when the control register in CPU configuration FPGA should After data issue, the data in data storage area can be sent to corresponding I/O device and write the return information of the I/O device by FPGA Go back to respective storage areas.

7. communication means according to claim 1, which is characterized in that after fpga logic completes all data transmit-receives, repair Change relevant control register to inquire for CPU；When the data transmit-receive that CPU inquires register confirmation FPGA is completed, which is read Out.