CN102981801A - Conversion method and device of local bus data bit wide - Google Patents
Conversion method and device of local bus data bit wide Download PDFInfo
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Abstract
The invention discloses a conversion method and a device of a local highway data bit wide, 32 bits operated instructs of a CPU has the characteristic that two LOCAL BUS operated instructs with 16 bits can be produced automatically, the programmabie logic units through the staging data to compiete the conversion of 16 bits/32 bits of data, therefore outer arrangement of simultaneous write-in or simultaneous read-out of data with 16 bits high and 16 bits low can be achieved, Conversion driving softwares can not sense a conversion bit of operated instructs wide operated instructs, Operated instructs that a chip is arranged outside to a wide data wide bit by narrow data bit wide CPU local bus wide data is achieved, therefore working quantity of the driving software is further reduced and the operated instructing efficiency of the CPU is improved and the system cost is reduced.
Description
Technical field
The application relates to general central processing unit (CPU) system applies field in the data communication, refers more particularly to conversion method and the device of a kind of local bus (Local Bus) data bit width.
Background technology
In some Embedded System Design, CPU communicates and manages the peripheral hardware chip of realizing specific function by Local Bus bus.The Local Bus bus bit wide of CPU and peripheral hardware chip might be asymmetric, generally takes one of following dual mode to address this problem in the prior art:
Mode 1: again choose CPU or peripheral hardware chip, make both Local Bus buses symmetrical, the advantage of the method is not need to add the chip bridge joint and add any processing, and CPU just can carry out processing instruction to the peripheral hardware chip; But generally, because CPU or peripheral hardware chip have certain specific function, can not be substituted, and again choose CPU or the peripheral hardware chip need to expend a large amount of man power and materials, cause project development to be delayed, make the serious consequences such as the product of developing is no longer effective.
Mode 2: select the programmable logic chips such as CPLD (CPLD, Complex Programmable Logic Device) or field programmable gate array (FPGA, Field-Programmable Gate Array) to carry out bit width conversion.Be illustrated in figure 1 as in certain system CPU to the hardware block diagram of peripheral hardware management of software ic.CPU 10f are connected by bit wide with CPLD be that the LOCAL BUS bus of 16 bits (bit) connects, CPLD 102 and peripheral hardware chip 103 are the LOCAL BUS bus of 32 bits by bit wide.When design CPLD logic, usually still can require driver by 16 bit operating instructions: when the write operation instruction, can come the data of 32 bits of buffer memory for driver provides low 16 bit register of high 16 bit register and, then CPLD writes the peripheral hardware chip to this 32 Bit data by the sequential of peripheral hardware chip requirement again, also requires simultaneously driver must wait this operational order to finish just and can carry out new read-write; When the read operation instruction, need CPLD first the peripheral hardware chip to be sent a read command, in CPLD, then CPU reads back data come by height 16 bit register again the data buffer storage of 32 bits.This processing mode has higher system overhead, causes the efficient of CPU operational order not high.
Because in this, be necessary to propose a kind of new solution, solve existing CPU and the incompatible problem of peripheral hardware chip local bus.
Summary of the invention
The application provides a kind of conversion method and device of local bus data bit width, can reduce the workload of drive software, improves CPU operational order efficient, reduces system overhead.
The conversion method of a kind of local bus data bit width that the embodiment of the present application provides comprises:
The write command of 32 bits that CPU will receive is converted to two 16 bit write operation instructions;
Programmable logic cells is kept in data and high address in first 16 bit write operation instruction of CPU;
Programmable logic cells sends an external address termination signal/TA to CPU and stops first 16 bit write operation instruction;
CPU sends second 16 bit write operation instruction to programmable logic cells, and programmable logic cells sends on the address signal pin of peripheral hardware chip after the high address of first temporary 16 bit write operation instruction and low order address in second 16 bit write operation instruction are made up;
Data in temporary first the 16 bit write operation instruction of data in second 16 bit write operation instruction that programmable logic cells sends CPU and programmable logic cells are sent on 32 bit data bus of peripheral hardware chip, wait for that then the peripheral hardware chip sends termination signal Dtack_n;
Programmable logic cells stops the write operation instruction after receiving the Dtack_n that the peripheral hardware chip sends immediately, second 16 bit write operation instruction of sending one/TA signal terminating CPU to CPU simultaneously.
Preferably, the write operation instruction transformation of 32 bits that will receive of described CPU is that the method for two 16 bit write operation instructions is: the write operation instruction transformation of 32 bits that CPU will receive is the 16 bit write operation instructions of successively decreasing by 16 bit aligned in two addresses.
Preferably, the method that described programmable logic cells is kept in the data in the write operation instruction of first 16 bit of CPU and high address is: it is temporary that programmable logic cells allows the end ale signal to write in the address register of programmable logic cells by address latch 16 bit high addresses in first 16 bit write operation instruction of CPU, and low 16 Bit datas in first 16 bit write command are then by chip selection signal CSn with write in the data register of programmable logic cells temporary with effect signal WRn.
Preferably, CPU sends second 16 bit write command to programmable logic cells, the method that sends to after programmable logic cells makes up the high address in first temporary 16 bit write command and low order address in second 16 bit write operation instruction on the address signal pin of peripheral hardware chip comprises: CPU sends second 16 bit write operation instruction to programmable logic cells, programmable logic cells sends CSn to the peripheral hardware chip, address signal ASn and and low level RWn, send on the address signal pin of peripheral hardware chip after simultaneously 16 bit low order address in the address signal in 16 temporary bit high addresses and second the 16 bit write operation instruction being made up.
Preferably, the data of temporary first the 16 bit write operation instruction of the data of programmable logic cells second 16 bit write operation instruction that CPU is sent and programmable logic cells are sent on 32 bit data bus of peripheral hardware chip and comprise: be sent on 32 bit data bus of peripheral hardware chip after temporary low 16 Bit datas make up on high 16 Bit datas that programmable logic cells sends CPU and the programmable logic cells data register.
The embodiment of the present application also provides the conversion method of another kind of local bus data bit width, comprising:
The instruction transformation of reading of 32 bits that CPU will receive is that instruction is read by 16 bits that 16 bit aligned increase progressively in two addresses;
CPU sends first 16 bit and reads instruction to the programmable logic chip unit, the programmable logic chip unit allows the end ALE cycle that 16 bit high addresses in first 16 bit read operation instruction are kept at address latch, send chip selection signal CSn, address signal ASn and read-write selection signal RWn to the peripheral hardware chip subsequently, address signal pin sending to the peripheral hardware chip after 16 temporary bit high addresses and the combination of 16 bit low order address in described first 16 bit read operation instruction starts 32 bit read operation instructions to the peripheral hardware chip;
After the peripheral hardware chip was put into the data of 32 bits on the data bus, the programmable logic chip unit was transferred to CPU to low 16 Bit datas wherein, and high 16 Bit datas are wherein kept in data register; Then the peripheral hardware chip represents to the programmable logic chip unit that by sending Dtack_n the read operation instruction of this 32 bit finishes;
After the Dtack_n signal that peripheral hardware sends is received in the programmable logic chip unit, first 16 bit read operation instruction of then sending one/TA signal terminating CPU to CPU;
CPU sends second 16 bit read operation instruction to the programmable logic chip unit, the programmable logic chip unit is sent to CPU to 16 Bit datas that are temporarily stored in the data register, and sends second 16 bit read operation instruction of one/TA signal terminating CPU to CPU.
Preferably, described programmable logic cells is complex programmable logic device (CPLD) or on-site programmable gate array FPGA.
The embodiment of the present application also provides a kind of conversion equipment of local bus data bit width, comprises the CPU of 16 bit local bus, the peripheral hardware chip of 32 bit local bus, and is connected a programmable logic cells that connects respectively described CPU and peripheral hardware chip,
Described CPU, the write command that is used for 32 bits that will receive is converted to two 16 bit write operation instructions, and these two 16 bit write operation instructions are sent to respectively described programmable logic cells two adjacent clock period;
Described programmable logic cells after being used for the data of first 16 bit write operation instruction that CPU is sent and high address and keeping in, sends an external address termination signal/TA to CPU and stops first 16 bit write operation instruction;
And after receiving that CPU sends second 16 bit write operation instruction, send on the address signal pin of peripheral hardware chip after the high address of first temporary 16 bit write operation instruction and low order address in second 16 bit write operation instruction made up;
Data in temporary first the 16 bit write operation instruction of data in second 16 bit write operation instruction that CPU is sent and programmable logic cells are sent on 32 bit data bus of peripheral hardware chip, wait for that then the peripheral hardware chip sends termination signal Dtack_n;
Stop immediately the write operation instruction after receiving the Dtack_n that the peripheral hardware chip sends, second 16 bit write operation instruction of sending one/TA signal terminating CPU to CPU simultaneously.
The embodiment of the present application also provides a kind of conversion equipment of local bus data bit width, comprises the CPU of 16 bit local bus, the peripheral hardware chip of 32 bit local bus, and is connected a programmable logic cells that connects respectively described CPU and peripheral hardware chip,
Described CPU, the instruction transformation of reading that is used for 32 bits that will receive is the 16 bit read operation instructions that two addresses increase progressively by 16 bit aligned, and these two 16 bit read operation instructions are sent to respectively described programmable logic cells two adjacent clock period;
Described programmable logic cells is used for:
After receiving that CPU sends first 16 bit and reads instruction, allow the end ALE cycle that 16 bit high addresses in first 16 bit read operation instruction are kept at address latch, send chip selection signal CSn, address signal ASn and read-write selection signal RWn to the peripheral hardware chip subsequently, address signal pin sending to the peripheral hardware chip after 16 temporary bit high addresses and the combination of 16 bit low order address in described first 16 bit read operation instruction starts 32 bit read operation instructions to the peripheral hardware chip;
Receive the data of 32 bits of peripheral hardware chip from data bus after, wherein low 16 Bit datas are transferred to CPU, high 16 Bit datas are wherein kept in data register; Then after receiving the Dtack_n signal that the peripheral hardware chip sends, then send first 16 bit read operation instruction of one/TA signal terminating CPU to CPU;
After receiving that CPU sends second 16 bit read operation instruction, 16 Bit datas that are temporarily stored in the data register are sent to CPU, and send second 16 bit read operation instruction of one/TA signal terminating CPU to CPU.
Preferably, described programmable logic cells is complex programmable logic device (CPLD) or on-site programmable gate array FPGA.
As can be seen from the above technical solutions, utilize the automatic characteristics that produce the LOCAL BUS operational order of two 16 bits of 32 bit operating instruction meetings of CPU, finished the conversion of 16 bits/32 Bit datas by the way of temporal data by programmable logic cells, to realize " writing simultaneously " or " reading simultaneously " peripheral hardware of high 16 bits and low 16 Bit datas, make the bit width conversion operational order concerning drive software, not have perception.The narrow data bit width CPU Local Bus that realizes by this method can further reduce the workload of drive software to the operational order of wide data bit width peripheral hardware, improves CPU operational order efficient, reduces system overhead.
Description of drawings
Fig. 1 be in the prior art in certain system CPU to the hardware block diagram of peripheral hardware management of software ic;
Fig. 2 be CPU of the present invention to CPLD send 32 a bit write operation instruction time sequential chart;
Fig. 3 is that CPLD of the present invention is to the sequential chart that sends 32 bit write operation instructions of peripheral hardware chip;
Fig. 4 sends 32 a bit write command data circulation sequential chart by CPLD to the peripheral hardware chip for the CPU that the embodiment of the invention one provides;
The CPU that Fig. 5 provides for the embodiment of the invention one is to 32 bit write operation instruction flow charts of peripheral hardware chip;
Fig. 6 is that CPU of the present invention reads the sequential chart of instruction to 32 bits that send of CPLD;
Fig. 7 is that CPLD of the present invention reads the sequential chart of instruction to 32 bits that send of peripheral hardware chip;
The CPU that Fig. 8 provides for the embodiment of the invention one sends 32 bits by CPLD to the peripheral hardware chip and reads director data circulation sequential chart;
The CPU that Fig. 9 provides for the embodiment of the invention two is to 32 bit read operation instruction flow charts of peripheral hardware chip.
Embodiment
For problems of the prior art, the application proposes a kind of conversion method of Local Bus data bit width, operate the peripheral hardware of 32 bits on the basis of existing CPU standard 16 bit Local Bus bus read write commands, utilize the 32 bit instruction meetings of CPU automatically to produce the characteristics of the Local Bus instruction of two 16 bits, finished the conversion of 16 bits/32 Bit datas by the way of temporal data by the CPLD logic, to realize " writing simultaneously " or " reading simultaneously " peripheral hardware of high 16 bits and low 16 Bit datas, make the bit width conversion operation concerning drive software, not have perception.Improve readability and the efficient of drive software.
Clearer for the know-why, characteristics and the technique effect that make the present techniques scheme, below in conjunction with specific embodiment the present techniques scheme is described in detail.The conversion of the data bit width of local bus is divided into two kinds of operational orders of write operation instruction and read operation instruction and realizes, below is set forth respectively by two embodiment.
Embodiment one: the local bus bit width conversion in the write operation instruction
Fig. 2 be CPU to CPLD send 32 a bit write command time sequential chart, A[15:0 wherein] be the address signal of 16 bits, Csn/WRn is chip selection signal/write enable signal, ALE is that address latch allows end (Address lock enable) signal, AD[31:16] be 16 bit addresses/data-reusing signal ,/TA is the external address termination signal.When CPU received the write command of 32 bits, for the local busLocal Bus of 16 bits, actual what send was to successively decrease by 16 bit aligned in two addresses, and data bit is the write operation instruction of 16 bit widths.The local busLocal Bus of CPU must be configured such that the write operation instruction of finishing CPU with external address termination signal/TA.
Fig. 3 is that CPLD is to the sequential chart that sends 32 bit write operation instructions of peripheral hardware chip.Wherein, CPU CLK is clock signal, and CSn is chip selection signal, and ASn is address signal, RWn selects signal for read-write, and high expression is read, and low expression is write, A[23:2] be 22 bit writing address signals, D[31:0] be 32 bit write data signals, Dtack_n is that data transmit termination signal.Sent in the ASn cycle address, sends subsequently 32 Bit datas, until the peripheral hardware chip provides termination signal Dtack_n.
As can be seen from Figures 2 and 3, as long as CPLD is embedded into CPU to second write cycle time that CPLD sends to the write operation instruction of peripheral hardware chip, can realize bumpless transfer.
The CPU that Fig. 4 shows embodiment one to be provided sends the data circulation sequential chart of 32 bit write operation instructions to the peripheral hardware chip by CPLD.Based on this sequential, CPU comprises to 32 bit write operation instruction flows of peripheral hardware chip as shown in Figure 5:
After step 501:CPU receives the write command of 32 bits, for the local bus of 16 bits, be converted to the 16 bit write operation instructions of successively decreasing by 16 bit aligned in two addresses.
When CPU writes 32 Bit data, always write first low 16 Bit datas, write high 16 Bit datas again, general address wire A1 is low, thereby CPLD can be low by recognizing address wire A1, confirms that this is first 16 bit write operation instruction of writing 32 bits.In follow-up sequential, CPLD recognizes address wire A1 when being high, is confirmed to be second 16 bit write operation instruction writing 32 bits.
Step 502:CPLD is with 16 bit high address A[31:16 in first 16 bit write operation instruction of CPU] to allow the end ale signal to write in the address register of CPLD by address latch temporary, and low 16 Bit datas in first 16 bit write operation instruction then write in the data register of CPLD temporary by CSn and WRn signal;
Step 503:CPLD sends the write operation instruction that one/TA stops first 16 bit to CPU;
Step 504:CPU sends second 16 bit write operation instruction high 16 Bit datas is sent to CPLD, CPLD then to the peripheral hardware chip send CSn, address signal ASn and and low level RWn, send on the address signal pin of peripheral hardware chip after the low order address combination in the high address of first the 16 bit write operation instruction that will keep in according to the address signal pin scope of peripheral hardware chip and second the 16 bit write operation instruction, wait for that then the peripheral hardware chip sends termination signal Dtack_n;
How to make up herein two in the 16 bit write operation instructions the high address and the address realm of the address wire support of status address and peripheral hardware chip relation is arranged, as being FA[23:2 when the address signal pin of peripheral hardware chip], then 16 temporary bit high address A[31:16] in A[23:16] with second 16 bit write operation instruction in 16 bit low order address A[15:0 in the address signal] in A[15:2] make up, send to the address signal pin FA[23:2 of peripheral hardware chip] on, close low 16 Bit datas preserved on the CPLD data register of high 16 bits data set that CPLD sends CPU are put into the peripheral hardware chip data bus D[31:0 of 32 bits] on;
Step 505:CPLD stops the write operation instruction after receiving the Dtack_n that the peripheral hardware chip sends immediately, simultaneously send second 16 bit write operation instruction of one/TA signal terminating CPU to CPU, thereby finished the 32 bit write operation instructions of CPU to the peripheral hardware chip.
Embodiment two: the local bus bit width conversion in the read operation instruction
Fig. 6 is that CPU is to the sequential chart that 32 bits are read that sends of CPLD.As shown in Figure 6, CPU receive 32 bits read instruction the time, for the Local Bus of 16 bits, actual what send is that two addresses increase by 16 bit aligned, data bit is the read operation instruction of 16 bit widths.Local Bus uses external address termination signal/TA still to finish the read operation instruction of CPU.
Fig. 7 is that CPLD is to the sequential chart that 32 bits are read that sends of peripheral hardware chip.Sent in the ASn cycle address, and 32 Bit datas send subsequently, until the peripheral hardware chip provides termination signal Dtack_n.
As can be seen from Figures 6 and 7, as long as the CPLD data of taking out 32 bits from the peripheral hardware chip in first CPU read cycle, and low 16 bits are issued CPU, again in second read cycle of CPU, high 16 bits are issued CPU, can realize the bumpless transfer of read operation instruction.
The CPU that Fig. 8 shows embodiment two to be provided sends the data circulation sequential chart of 32 bit read operation instructions to the peripheral hardware chip by CPLD.Based on this sequential, CPU comprises to 32 bit read operation instruction flows of peripheral hardware chip as shown in Figure 9:
Step 901:CPU receive 32 bits read instruction after, for the Local Bus of 16 bits, actually send the read operation instruction that the data bit of successively decreasing by 16 bit aligned two addresses is 16 bit widths.When CPU reads 32 Bit data, always read first low 16 Bit datas, read again high 16 Bit datas, thereby CPLD can be low by recognizing address wire A1, confirm that this is first 16 bit read operation instruction that 32 bits are read instruction.
Step 902:CPLD receives for first 16 bit read operation instruction, then begin to send CSn, ASn and RWn to the peripheral hardware chip, simultaneously address signal A[15:0 on the 16 temporary bit high address recombinants] in 16 bit low order address send to the address signal pin FA[23:2 of peripheral hardware chip] on, start 32 bit read operation instructions to the peripheral hardware chip;
Step 903: when the peripheral hardware chip is put into data bus D[31:0 to the data of 32 bits] upper after, CPLD is wherein the 16 bit D[15:0 that hang down] be put into data bus D[15:0] on, high 16 bit D[31:16 wherein] preserve with data register; Then the peripheral hardware chip represents that to CPLD the read operation instruction of this 32 bit finishes by sending Dtack_n.
After step 904:CPLD receives the Dtack_n signal that peripheral hardware sends, first 16 bit read operation instruction of then sending one/TA signal terminating CPU to CPU;
Step 905:CPU is followed by sending second 16 bit read operation instruction, and CPLD is put into AD[15:0 to 16 Bit datas that are temporarily stored in the register immediately] on the bus, second 16 bit read operation instruction of sending one/TA signal terminating CPU to CPU simultaneously.
Among the above embodiment, the programmable logic device (PLD) of carrying out bit width conversion between CPU and peripheral hardware chip is CPLD.Also can adopt the programmable logic device (PLD) of other types in the practical application, for example FPGA.
The above only is the application's preferred embodiment; not in order to limit the application's protection domain; all within the spirit and principle of present techniques scheme, any modification of making, be equal to replacement, improvement etc., all should be included within the scope of the application's protection.
Claims (10)
1. the conversion method of a local bus data bit width is characterized in that, comprising:
The write command of 32 bits that CPU will receive is converted to two 16 bit write operation instructions;
Programmable logic cells is kept in data and high address in first 16 bit write operation instruction of CPU;
Programmable logic cells sends an external address termination signal/TA to CPU and stops first 16 bit write operation instruction;
CPU sends second 16 bit write operation instruction to programmable logic cells, and programmable logic cells sends on the address signal pin of peripheral hardware chip after the high address of first temporary 16 bit write operation instruction and low order address in second 16 bit write operation instruction are made up;
Data in temporary first the 16 bit write operation instruction of data in second 16 bit write operation instruction that programmable logic cells sends CPU and programmable logic cells are sent on 32 bit data bus of peripheral hardware chip, wait for that then the peripheral hardware chip sends termination signal Dtack_n;
Programmable logic cells stops the write operation instruction after receiving the Dtack_n that the peripheral hardware chip sends immediately, second 16 bit write operation instruction of sending one/TA signal terminating CPU to CPU simultaneously.
2. method according to claim 1, it is characterized in that the write operation instruction transformation of 32 bits that described CPU will receive is that the method for two 16 bit write operation instructions is: the write operation instruction transformation of 32 bits that CPU will receive is the 16 bit write operation instructions of successively decreasing by 16 bit aligned in two addresses.
3. method according to claim 2, it is characterized in that, the method that described programmable logic cells is kept in the data in the write operation instruction of first 16 bit of CPU and high address is: it is temporary that programmable logic cells allows the end ale signal to write in the address register of programmable logic cells by address latch 16 bit high addresses in first 16 bit write operation instruction of CPU, and low 16 Bit datas in first 16 bit write command are then by chip selection signal CSn with write in the data register of programmable logic cells temporary with effect signal WRn.
4. method according to claim 3, it is characterized in that, CPU sends second 16 bit write command to programmable logic cells, the method that sends to after programmable logic cells makes up the high address in first temporary 16 bit write command and low order address in second 16 bit write operation instruction on the address signal pin of peripheral hardware chip comprises: CPU sends second 16 bit write operation instruction to programmable logic cells, programmable logic cells sends CSn to the peripheral hardware chip, address signal ASn and and low level RWn, send on the address signal pin of peripheral hardware chip after simultaneously 16 bit low order address in the address signal in 16 temporary bit high addresses and second the 16 bit write operation instruction being made up.
5. method according to claim 4, it is characterized in that the data of first 16 bit write operation instruction that the data of second 16 bit write operation instruction that programmable logic cells sends CPU and programmable logic cells are temporary are sent on 32 bit data bus of peripheral hardware chip and comprise: be sent on 32 bit data bus of peripheral hardware chip after temporary low 16 Bit datas make up on high 16 Bit datas that programmable logic cells sends CPU and the programmable logic cells data register.
6. the conversion method of a local bus data bit width is characterized in that, comprising:
The instruction transformation of reading of 32 bits that CPU will receive is that instruction is read by 16 bits that 16 bit aligned increase progressively in two addresses;
CPU sends first 16 bit and reads instruction to the programmable logic chip unit, the programmable logic chip unit allows the end ALE cycle that 16 bit high addresses in first 16 bit read operation instruction are kept at address latch, send chip selection signal CSn, address signal ASn and read-write selection signal RWn to the peripheral hardware chip subsequently, address signal pin sending to the peripheral hardware chip after 16 temporary bit high addresses and the combination of 16 bit low order address in described first 16 bit read operation instruction starts 32 bit read operation instructions to the peripheral hardware chip;
After the peripheral hardware chip was put into the data of 32 bits on the data bus, the programmable logic chip unit was transferred to CPU to low 16 Bit datas wherein, and high 16 Bit datas are wherein kept in data register; Then the peripheral hardware chip represents to the programmable logic chip unit that by sending Dtack_n the read operation instruction of this 32 bit finishes;
After the Dtack_n signal that peripheral hardware sends is received in the programmable logic chip unit, first 16 bit read operation instruction of then sending one/TA signal terminating CPU to CPU;
CPU sends second 16 bit read operation instruction to the programmable logic chip unit, the programmable logic chip unit is sent to CPU to 16 Bit datas that are temporarily stored in the data register, and sends second 16 bit read operation instruction of one/TA signal terminating CPU to CPU.
7. according to claim 1 to 6 each described methods, it is characterized in that described programmable logic cells is complex programmable logic device (CPLD) or on-site programmable gate array FPGA.
8. the conversion equipment of a local bus data bit width comprises the CPU of 16 bit local bus, the peripheral hardware chip of 32 bit local bus, and is connected a programmable logic cells that connects respectively described CPU and peripheral hardware chip, it is characterized in that,
Described CPU, the write command that is used for 32 bits that will receive is converted to two 16 bit write operation instructions, and these two 16 bit write operation instructions are sent to respectively described programmable logic cells two adjacent clock period;
Described programmable logic cells after being used for the data of first 16 bit write operation instruction that CPU is sent and high address and keeping in, sends an external address termination signal/TA to CPU and stops first 16 bit write operation instruction;
And after receiving that CPU sends second 16 bit write operation instruction, send on the address signal pin of peripheral hardware chip after the high address of first temporary 16 bit write operation instruction and low order address in second 16 bit write operation instruction made up;
Data in temporary first the 16 bit write operation instruction of data in second 16 bit write operation instruction that CPU is sent and programmable logic cells are sent on 32 bit data bus of peripheral hardware chip, wait for that then the peripheral hardware chip sends termination signal Dtack_n;
Stop immediately the write operation instruction after receiving the Dtack_n that the peripheral hardware chip sends, second 16 bit write operation instruction of sending one/TA signal terminating CPU to CPU simultaneously.
9. the conversion equipment of a local bus data bit width, comprise the CPU of 16 bit local bus, the peripheral hardware chip of 32 bit local bus, with is connected a programmable logic cells that connects respectively described CPU and peripheral hardware chip, it is characterized in that, described CPU, the instruction transformation of reading for 32 bits that will receive is the 16 bit read operation instructions that two addresses increase progressively by 16 bit aligned, and these two 16 bit read operation instructions are sent to respectively described programmable logic cells two adjacent clock period;
Described programmable logic cells is used for:
After receiving that CPU sends first 16 bit and reads instruction, allow the end ALE cycle that 16 bit high addresses in first 16 bit read operation instruction are kept at address latch, send chip selection signal CSn, address signal ASn and read-write selection signal RWn to the peripheral hardware chip subsequently, address signal pin sending to the peripheral hardware chip after 16 temporary bit high addresses and the combination of 16 bit low order address in described first 16 bit read operation instruction starts 32 bit read operation instructions to the peripheral hardware chip;
Receive the data of 32 bits of peripheral hardware chip from data bus after, wherein low 16 Bit datas are transferred to CPU, high 16 Bit datas are wherein kept in data register; Then after receiving the Dtack_n signal that the peripheral hardware chip sends, then send first 16 bit read operation instruction of one/TA signal terminating CPU to CPU;
After receiving that CPU sends second 16 bit read operation instruction, 16 Bit datas that are temporarily stored in the data register are sent to CPU, and send second 16 bit read operation instruction of one/TA signal terminating CPU to CPU.
10. install as claimed in claim 8 or 9, it is characterized in that described programmable logic cells is complex programmable logic device (CPLD) or on-site programmable gate array FPGA.
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| WO2019165954A1 (en) * | 2018-03-01 | 2019-09-06 | 深圳市中兴微电子技术有限公司 | Data bit width conversion method and device, and computer-readable storage medium |
| CN111309653A (en) * | 2018-12-12 | 2020-06-19 | 北京兆易创新科技股份有限公司 | Data bus and method for reading data and writing data |
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