CN108153485A - A kind of more equipment collaborations access the method and system of SRAM - Google Patents
A kind of more equipment collaborations access the method and system of SRAM Download PDFInfo
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- CN108153485A CN108153485A CN201711159777.2A CN201711159777A CN108153485A CN 108153485 A CN108153485 A CN 108153485A CN 201711159777 A CN201711159777 A CN 201711159777A CN 108153485 A CN108153485 A CN 108153485A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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Abstract
The present invention provides the method and system that a kind of more equipment collaborations access SRAM, belongs to technical field of integrated circuits, and this method and system do not increase hardware spending, reliably realizes that more equipment collaborations access SRAM.When multiple equipment involved in method and system is both needed to access SRAM, using one of them as main equipment, other is slave device, slave device obtains current SRAM states by the interactive information between main equipment, the SRAM read-writes primary device control that slave device is sent out determines carry out read or write to SRAM with which equipment of each priority facility by main equipment according to current SRAM states.The system that the more equipment higher for real-time access SRAM provides a kind of effective method, handshake mechanism is realized simple twice, can ensure that read-write SRAM operations are reliable effective, and this method to the read-write moment of SRAM and read-write cycle etc. without particular/special requirement, versatility is stronger.
Description
Technical field
The invention belongs to technical field of integrated circuits, more particularly to a kind of reliable more equipment collaborations access the side of SRAM
Method.
Background technology
Data are stored as the key component in digital circuitry, carry the important function of data buffer storage.Data are deposited
For common SRAM with it without refresh circuit, the advantages that read-write interface sequential is simple, becomes the memory of current mainstream in storage, and
It is widely used in embedded system.In digital circuitry, often there is multiple equipment and be both needed to access with a piece of SRAM's
A kind of situation, since SRAM synchronizations can only be accessed by an equipment, it is therefore desirable to realization multiple equipment alternate access SRAM
Method.Traditional method is typically accessed by software timesharing or hardware timesharing is accessed and realized.Existing software timesharing accesses
Method cannot be guaranteed to read and write the real-time of SRAM mostly；And hardware timesharing access method is typically design alternative circuit, is increased
The area and cost of circuit, reduce the competitiveness of product in market.In order to cost-effective, it is ensured that the reliability of product carries herein
A kind of method that reliable more equipment collaborations access SRAM is gone out.This method hardware is simple, and software overhead is smaller, in practice it has proved that adopts
It is effectively reliable that SRAM is accessed with this method.
Invention content
The purpose of the present invention：Overcome the deficiencies in the prior art proposes that a kind of reliable more equipment collaborations access the side of SRAM
Method, this method are based on software coordinates thought, do not increase hardware spending, reliably realize that more equipment collaborations access SRAM.
To achieve the above objectives, the technical solution taken of the present invention is：A kind of method that more equipment collaborations access SRAM, when
When multiple equipment is both needed to access SRAM, using one of them as main equipment, other is slave device, and slave device passes through between main equipment
Interactive information obtain current SRAM states, the SRAM read-writes primary device control that slave device is sent out, by main equipment according to
Current SRAM states determine which equipment carries out read or write to SRAM.
A kind of method that more equipment collaborations access SRAM, this method include the following steps：
S1 is when multiple equipment is both needed to access SRAM, and using one of them as main equipment, other is slave device；
Main equipment and SRAM are connected directly by S2, and slave device is connected with main equipment, and slave device is set the access of SRAM by master
Standby switching is realized；
S3 main equipments are responsible for monitoring and record the current state of SRAM, when multiple equipment accesses SRAM simultaneously, main equipment
According to current state and each priority facility determine which equipment to access SRAM by；
S4 accesses SRAM when higher priority equipment, and no matter what state current SRAM is in, and equal N-free diet method grasps SRAM
Make the equipment that power gives highest priority；
S5 accesses SRAM when low priority equipment, SRAM current states is first judged, to determine whether to start this reading
Or write, it needs to judge this time to read or write whether succeed after SRAM is read or write, if successfully mark is exactly to judge to operate at this
Whether period has other equipment to SRAM read or writes；If judging result need to read or write, Zhi Daocheng again to read or write failure
Until work(；
The system that a kind of more equipment collaborations access SRAM, which is characterized in that including：MCU、FPGA、SRAM；It is set based on FPGA
Standby, MCU is slave device；FPGA is directly connected with SRAM, and MCU is connected with FPGA, and MCU transfers to the operation of SRAM by FPGA real
It is existing；
(1) FPGA controls two labels：One is SRAM current states, and one is SRAM read-write labels；The current shapes of SRAM
State is defaulted as idle state, and when there is equipment to read or write SRAM, SRAM current states need to be set to read states or write state by FPGA,
After the completion of read or write, SRAM current states are reverted into idle state；Read-write label is defaulted as idle state, when there is equipment
When reading or writing SRAM, read-write label need to be set to read-write state by FPGA, when FPGA completes once to read or write SRAM operations, and read
After read-write label, read-write label is reverted into idle state；
(2) MCU accesses the priority of SRAM higher than FPGA；
Before the relatively low FPGA of priority reads or writes SRAM, FPGA need to first judge SRAM current states, if the current shapes of SRAM
State is idle state, and FPGA can read or write SRAM, and inquiry read-write flag register is needed to judge this after SRAM is read or write
It reads or writes and whether succeeds, if read-write flag register is read-write state, prove that this read or write fails, if read-write label
Register is idle state, then proves this read or write success；If judging result to read or write failure, need to read again or
It writes, until success；When the higher MCU of priority reads or writes SRAM, SRAM is connected by the control of FPGA N-free diet methods with MCU,
Ensure MCU, real time access SRAM.
The system that a kind of more equipment collaborations access SRAM, which is characterized in that including：MCU、FPGA、SRAM；It is set based on FPGA
Standby, MCU is slave device；FPGA is directly connected with SRAM, and MCU is connected with FPGA, and MCU transfers to the operation of SRAM by FPGA real
It is existing；
(1) FPGA controls two labels：One is SRAM current states, and one is SRAM read-write labels；The current shapes of SRAM
State is defaulted as idle state, and when there is equipment to read or write SRAM, SRAM current states need to be set to read states or write state by FPGA,
After the completion of read or write, SRAM current states are reverted into idle state；Read-write label is defaulted as idle state, when there is equipment
When reading or writing SRAM, read-write label need to be set to read-write state by FPGA, when FPGA completes once to read or write SRAM operations, and read
After read-write label, read-write label is reverted into idle state；
(2) FPGA accesses the priority of SRAM higher than MCU；Before the relatively low MCU of priority reads or writes SRAM, MCU first sentences
Disconnected SRAM current states, if SRAM current states are idle state, MCU is carried out reading or writing SRAM, be inquired after SRAM is read or write
Whether this reads or writes and succeeds read-write marker for judgment, if read-write labeled as read-write state, proves that this read or write fails,
If read-write proves this read or write success labeled as idle state；If judging result need to be read again to read or write failure
Or write, until success；When the higher FPGA of priority reads or writes SRAM, FPGA N-free diet methods are read or write.
Preferably, the system that a kind of above-mentioned more equipment collaborations access SRAM, which is characterized in that further include RS422 interfaces
Circuit, data transmission interface circuit, a host computer for being equipped with data acquisition device；SRAM and FPGA input/output port phases
Even；MCU has the EPI interfaces of peripheral hardware, and EPI interfaces are connected with other input/output ports of FPGA, and EPI interfaces can be configured
FPGA and SRAM patterns are accessed for timesharing；The RS422 interface circuits realize the reception of host computer serial port command, and are transmitted to
FPGA；The data transmission interface circuit realizes the transmission of SRAM data；The host computer is used for the transmission of serial port command
With the acquisition and parsing of SRAM data；FPGA can realize that serial port command receives, control EPI interfaces timesharing accesses FPGA and
SRAM。
Preferably, the system that a kind of above-mentioned more equipment collaborations access SRAM, which is characterized in that including：FPGA can be realized
SRAM Read-write Catrols function, data sending function, SRAM state control functions.
Preferably, the system that a kind of above-mentioned more equipment collaborations access SRAM, which is characterized in that MCU for TI preferably, on
The system that a kind of more equipment collaborations stated access SRAM, which is characterized in that the MCU has the EPI interfaces of peripheral hardware, can realize 8,
16 or 32 parallel-by-bit bus interface.
The system that a kind of more equipment collaborations access SRAM, which is characterized in that including：MCU、FPGA、SRAM；It is set based on FPGA
Standby, MCU is slave device；FPGA is directly connected with SRAM, and MCU is connected with FPGA, and MCU transfers to the operation of SRAM by FPGA real
It is existing；The priority that FPGA accesses SRAM is higher than MCU；Its specific access method is as follows：
(1) SRAM orders are read：Host computer, which is sent, reads SRAM orders, and FPGA receives and parses through order by serial ports；
(2) SRAM data is read：After FPGA receives reading SRAM orders, N-free diet method generation SRAM read signals, SRAM pieces choosing letter
Number, forbid SRAM write enable signal, the data read from SRAM are sent to host computer；
(3) SRAM states control：FPGA controls the state of two register tagging SRAM：Respectively SRAM current states are posted
Storage and SRAM read-write flag registers, so that MCU is read；The default conditions of current status register are " idle state ", when
When starting to read SRAM operations, current status register is set to " read states ", read operation terminates to restore current status register
For " idle state ", when starting to write SRAM operations, current status register is set to " write state ", write operation terminates will be current
Status register reverts to " idle state ", and read-write flag register is defaulted as idle state, will when starting to read SRAM operations
Read-write flag register is set to read-write state；
(4) SRAM data is write：The interaction of the EPI interfaces and FPGA of FPGA controls MCU, before SRAM is write, MCU is looked into first
SRAM current status registers are ask, when being " idle state ", MCU writes SRAM by the initiation of EPI interfaces and operates, and FPGA judges SRAM
Current state, if currently empty spare time state, FPGA are sent to the following signals of SRAM：MCU write SRAM signals, SRAM chip selection signals,
SRAM data signal is write, otherwise FPGA does not send above-mentioned signal；After the completion of MCU writes SRAM operations, MCU inquiry SRAM read-write labels
Register, if read-write flag register is read-write state, then it represents that received during writing SRAM and read SRAM orders, write SRAM and be forced
It interrupts, writes SRAM operation failures, MCU sends order and SRAM read-write flag registers are set to idle state at this time, and FPGA is received
Read-write flag register is set to idle state, while this data is re-write SRAM by MCU after order, is until being write as work(
Only.
Our bright advantageous effect compared with prior art is：
(1) highly reliable, the thought based on software coordinates ensures the reliable read write of SRAM using handshake mechanism twice, both
Hardware spending is reduced, has saved cost, and improves the reliability of system；
(2) versatility is good, and for this method to reading and writing the SRAM specific moment, read-write cycle etc. without particular/special requirement, adaptability is stronger；
(3) real-time is high, it can be achieved that the high equipment N-free diet method of priority accesses SRAM.
Description of the drawings
A kind of more equipment collaborations that Fig. 1 is the present invention access SRAM system composition.
Fig. 2 is the system data flow direction figure in the embodiment of the present invention two.
Fig. 3 is the SRAM read-write flow charts in the embodiment of the present invention two.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and embodiments.It should be appreciated that described herein
Specific embodiment is used only for explaining the present invention, is not intended to limit the present invention.
A kind of method that reliable more equipment collaborations access SRAM, when multiple equipment is both needed to access SRAM, with wherein one
A other for slave device, slave device obtains current SRAM states by the interactive information between main equipment for main equipment, from setting
The control of SRAM read-writes primary device that preparation goes out, by main equipment according to current SRAM states determine with each priority facility which
One equipment carries out read or write to SRAM.
The system that a kind of reliable more equipment collaborations access SRAM, including defined below：
(1) in the system for designing more equipment collaborations access SRAM, main equipment and SRAM are connected directly, slave device and master
Equipment is connected, and slave device is finally transferred to the access of SRAM by main equipment and realized.
(2) main equipment is responsible for monitoring and records the current state of SRAM；When multiple equipment accesses SRAM simultaneously, main equipment
According to current state and each priority facility determine which equipment to access SRAM by；
(3) when higher priority equipment accesses SRAM, no matter current SRAM is in any state, and equal N-free diet method grasps SRAM
Make the equipment that power gives highest priority；
(4) the relatively low equipment of priority may be interrupted the read-write operation of SRAM by the higher equipment of priority, therefore need
Establishment of a mechanism ensures the reliable read write of SRAM.The present invention is realized using handshake mechanism twice, when low priority equipment exists
Inquiry SRAM current states are needed before read/write SRAM to determine whether to start this read/write (if SRAM current states is the free time
State can then start this read/write operation, otherwise cannot start this read/write operation), it needs to judge after read/write SRAM
This time whether (inquiry read/write flag register) read/write succeeds, if successfully mark be exactly judge be during this operation
The no control for having other equipment successfully to obtain SRAM has simultaneously carried out read/write operation (if read/write flag register is read/write
State then proves that this read/write operation fails, if read/write flag register is idle state, proves this read/write operation
Success).If judging result fails for read/write, read/write again is needed, until success.
Embodiment one：A kind of more equipment collaborations of the present invention access SRAM system, specifically include：MCU、FPGA、SRAM.
MCU and FPGA is both needed to access SRAM, and in this embodiment, and MCU accesses the priority of SRAM higher than FPGA.FPGA directly with
SRAM is connected, and MCU is connected with FPGA, and MCU transfers to the operation of SRAM by FPGA and realizes.MCU is cooperateed with FPGA accesses SRAM's
It is as follows：
(3) FPGA is responsible for two registers, and one is SRAM current status registers, and one is that read/write label is posted
Storage.SRAM current status registers are defaulted as idle state, and when there is equipment read/write SRAM, FPGA need to be by the current shapes of SRAM
State register is set to read states or write state, and after the completion of read/write operation, SRAM current status registers are reverted to idle shape
State.Read/write flag register is defaulted as idle state, and when there is equipment read/write SRAM, FPGA need to be by read/write flag register
Read states or write state are set to, when FPGA completes read/write SRAM operation, and after reading read/write flag register, will read/
It writes flag register and reverts to idle state.
(4) before the relatively low FPGA of priority reads or writes SRAM, FPGA need to first judge SRAM current states, if SRAM is current
State is idle state, and FPGA can read or write SRAM, and inquiry read-write flag register is needed to judge this after SRAM is read or write
Whether secondary read or write succeeds, if read-write flag register is read-write state, proves that this read or write fails, if read-write mark
Note register is idle state, then proves this read or write success.If judging result be read/write failure, need to read again or
It writes, until success.
(5) as the higher MCU read/write SRAM of priority, FPGA needs N-free diet method that SRAM is connected with MCU, it is ensured that MCU
It can be with real time access SRAM.
A kind of more equipment collaborations access SRAM systems of embodiment two, the present invention, specifically include：MCU、FPGA、SRAM.
FPGA is main equipment, and MCU is slave device；MCU and FPGA is both needed to access SRAM, and in this embodiment, and FPGA accesses SRAM
Priority be higher than MCU.FPGA is directly connected with SRAM, and MCU is connected with FPGA, and MCU transfers to the operation of SRAM by FPGA real
It is existing.MCU cooperates with access SRAM to be as follows with FPGA：
(3) FPGA controls two labels：One is SRAM current states, and one is SRAM read-write labels；The current shapes of SRAM
State is defaulted as idle state, and when there is equipment to read or write SRAM, SRAM current states need to be set to read states or write state by FPGA,
After the completion of read or write, SRAM current states are reverted into idle state；Read-write label is defaulted as idle state, when there is equipment
When reading or writing SRAM, read-write label need to be set to read states or write state by FPGA, be operated when FPGA completes the primary SRAM that reads or writes,
And after reading read-write label, read-write label is reverted into idle state；
(2) when the FPGA priority for accessing SRAM is higher than MCU；Before the relatively low MCU of priority reads or writes SRAM, MCU is first
Judge SRAM current states, if SRAM current states are idle state, MCU is carried out reading or writing SRAM, be looked into after SRAM is read or write
Asking read-write marker for judgment, whether this reads or writes and succeeds, if read-write proves that this read or write is lost labeled as read-write state
It loses, if read-write proves this read or write success labeled as idle state；If judging result needs weight to read or write failure
It newly reads or writes, until success；
(3) when the higher FPGA of priority reads or writes SRAM, FPGA N-free diet methods are read or write；
In short, when main equipment priority is less than slave device, after slave device is initiated to the read or write of SRAM, main equipment
Slave device is connected with SRAM, when main equipment priority is higher than slave device, after slave device is initiated to the read or write of SRAM,
Main equipment first judges SRAM states, is idle state if SRAM, and slave device is connected by main equipment with SRAM.
Embodiment three：As shown in Figure 1, a kind of reliable more equipment collaborations of the present invention access the system composition of SRAM, packet
It includes：One piece of SRAM read-write equipment being made of MCU, FPGA, SRAM, RS422 interface circuits, data transmission interface circuit, one
The host computer of data acquisition device is installed.In the SRAM read-write equipments, MCU and FPGA are both needed to access SRAM, and FPGA is straight
It connects and is connected with SRAM, MCU is connected with FPGA, and MCU transfers to the operation of SRAM by FPGA and realizes.MCU needs to write data into SRAM,
FPGA accesses SRAM priority in this embodiment needs N-free diet method to read higher than MCU, FPGA after reading SRAM orders are received
Take the data in SRAM.
In the SRAM read-write equipments, MCU realizes that the processor has Peripheral Interface by the TM4C1294 of TI companies
(EPI), it can be achieved that 8/16/32 parallel-by-bit bus interface, EPI interfaces are connected with FPGA IO, EPI interfaces have a variety of Working moulds
Formula can access FPGA and SRAM by the corresponding pattern timesharing of software configuration；
FPGA as main equipment, need to realize serial port command receive capabilities, SRAM Read-write Catrols function, data sending function,
SRAM states control function and EPI interface control functions, FPGA select the Spartan6 family chips of Xilinx companies
XC6SLX45, model FPGA are capable of providing the hardware resources such as enough logic gate numbers, I/O pin, RAM for users to use；
SRAM selects the CY7C1061, capacity 2MB, data width 16bits of CYPRESS companies；
RS422 interface circuits realize the reception of host computer serial port command；
Data transmission interface circuit realizes the transmission of SRAM data；
Host computer is for the transmission of serial port command and the acquisition and parsing of SRAM data.
As shown in Fig. 2, a kind of method that reliable more equipment collaborations access SRAM, data flow figure lead to comprising four datas
Road, it is as follows per data access data flow：
(5) SRAM order accesses are read, host computer, which is sent, reads SRAM orders, and FPGA is received simultaneously by serial port command receiving module
After resolve command, read command is forwarded to SRAM Read-write Catrol modules；
(6) SRAM data access is read, after FPGA receives reading SRAM orders, the generation of SRAM Read-write Catrol modules N-free diet method
SRAM read signals/RD, SRAM chip selection signal/CS, SRAM byte enable signal/BLE and/BHE, SRAM address signal ADDR, together
When forbid SRAM write enable signal/WE, and above-mentioned signal is connected to SRAM, will be read by data transmission blocks from SRAM
Data are sent to host computer data acquisition device；
(7) SRAM states control access generates two register tagging SRAM states by SRAM status control modules, with
It is read for MCU, respectively SRAM current status registers SRAM_STA and SRAM read-write flag register READ_FLAG, currently
The default conditions of status register SRAM_STA are " idle state ", when starting to read SRAM operations, by current status register
SRAM_STA is set to " read states ", and read operation terminates current status register SRAM_STA reverting to " idle state ", when opening
When beginning writes SRAM operations, current status register SRAM_STA is set to " write state ", write operation terminates to deposit current state
Device SRAM_STA is reverted to " idle state ", and read flag register READ_FLAG is defaulted as invalid state, is grasped when starting reading SRAM
When making, read flag register READ_FLAG is set to effective (read states or write state)；
(8) write SRAM data access, MCU realizes the interaction with FPGA by EPI interface control modules, write SRAM it
Before, MCU inquires SRAM current status registers SRAM_STA first, and when SRAM_STA is " idle state ", MCU is connect by EPI
Mouth initiation is write SRAM and is operated, and the SRAM Read-write Catrol modules inside FPGA judge SRAM current states, if currently empty spare time state,
MCU is write into SRAM signals/WE, SRAM chip selection signal/CS, SRAM byte enable signal/BLE and/BHE, SRAM address signal
ADDR, SRAM data signal DATA is write, be connected with SRAM, otherwise FPGA is not responding to this write operation, after completing a write operation,
MCU inquires SRAM read/write flag register READ_FLAG, if READ_FLAG is read states, then it represents that received during writing SRAM
It to SRAM orders are read, writes SRAM and is forced to interrupt, write SRAM operation failures, MCU sends order and SRAM read/write is marked deposit at this time
Device READ_FLAG is set to idle state, and FPGA is received and READ_FLAG is set to idle state after order, while MCU is by this number
According to re-writing SRAM, until being write as work(.
In conclusion provided herein is a kind of reliable more equipment collaborations method for accessing SRAM, flow is as shown in Figure 3.
Reading SRAM operations needs N-free diet method to perform, i.e., ongoing to write SRAM operations it is possible that being interrupted, the present invention passes through MCU and FPGA
Between handshake mechanism twice ensure that MCU can be reliably completed the write operation of SRAM.MCU, which writes to need before SRAM first to inquire SRAM, to be worked as
Preceding status register, it is ensured that SRAM current states are idle state, are so far completed for the first time " shaking hands ", completion once writes SRAM
It after operation, also needs to judge SRAM read flag registers again, to confirm that this writes whether SRAM succeeds, if unsuccessful need to send life
SRAM read flag registers are set in vain, and rewrite SRAM by order, are so far completed second " shaking hands ".This machine of shaking hands twice
System ensures that MCU can reliably write SRAM in the case where FPGA needs N-free diet method to read SRAM.
The method that a kind of reliable more equipment collaborations of the present invention access SRAM realizes simple, software, hardware spending
Smaller, the system that more equipment higher for real-time access SRAM provides a kind of effective method, it is described twice
Handshake mechanism is realized simple, it can be ensured that read-write SRAM operations are reliable effective, and read-write moment and read-write of this method to SRAM
Period etc., versatility was stronger without particular/special requirement.
Claims (9)
1. a kind of method that more equipment collaborations access SRAM, which is characterized in that when multiple equipment is both needed to access SRAM, with wherein
One is main equipment, and other is slave device, and slave device obtains current SRAM states by the interactive information between main equipment, from
Which equipment pair the SRAM read-writes primary device control that equipment is sent out, determine by main equipment according to current SRAM states
SRAM carries out read or write.
2. a kind of method that more equipment collaborations access SRAM, which is characterized in that this method includes the following steps：
S1 is when multiple equipment is both needed to access SRAM, and using one of them as main equipment, other is slave device；
Main equipment and SRAM are connected directly by S2, and slave device is connected with main equipment, and slave device is turned the access of SRAM by main equipment
Connect realization；
S3 main equipments are responsible for monitoring and record the current state of SRAM, when multiple equipment accesses SRAM simultaneously, main equipment according to
Current state and each priority facility determine which equipment to access SRAM by；
S4 accesses SRAM when higher priority equipment, and no matter what state current SRAM is in, and equal N-free diet method is by SRAM operating rights
The equipment for giving highest priority；
S5 accesses SRAM when low priority equipment, first judges SRAM current states, is read or write with determining whether to start this,
Need to judge this time to read or write and whether succeed after SRAM is read or write, if successfully mark be exactly judge be during this operation
It is no to have other equipment to SRAM read or writes；If judging result need to read or write, to read or write failure until being successfully again
Only.
3. a kind of system that more equipment collaborations access SRAM, which is characterized in that including：MCU、FPGA、SRAM；It is set based on FPGA
Standby, MCU is slave device；FPGA is directly connected with SRAM, and MCU is connected with FPGA, and MCU transfers to the operation of SRAM by FPGA real
It is existing；
(1) FPGA controls two labels：One is SRAM current states, and one is SRAM read-write labels；
SRAM current states are defaulted as idle state, and when there is equipment to read or write SRAM, SRAM current states need to be set to by FPGA
SRAM current states after the completion of read or write, are reverted to idle state by read states or write state；Read-write label is defaulted as sky
Not busy state, when there is equipment to read or write SRAM, read-write label need to be set to read-write state by FPGA, when FPGA completions once read or write
SRAM operate, and read read-write label after, will read-write label revert to idle state；
(2) MCU accesses the priority of SRAM higher than FPGA；
Before the relatively low FPGA of priority reads or writes SRAM, FPGA need to first judge SRAM current states, if SRAM current states are
Idle state, FPGA can read or write SRAM, needed after SRAM is read or write inquiry read-write flag register with judge this read or
It writes and whether succeeds, if read-write flag register is read-write state, prove that this read or write fails, if read-write label deposit
Device is idle state, then proves this read or write success；If judging result need to read or write, directly again to read or write failure
Until success；
When the higher MCU of priority reads or writes SRAM, SRAM is connected by the control of FPGA N-free diet methods with MCU, it is ensured that MCU, real-time
Access SRAM.
4. a kind of system that more equipment collaborations access SRAM, which is characterized in that including：MCU、FPGA、SRAM；It is set based on FPGA
Standby, MCU is slave device；FPGA is directly connected with SRAM, and MCU is connected with FPGA, and MCU transfers to the operation of SRAM by FPGA real
It is existing；
(1) FPGA controls two labels：One is SRAM current states, and one is SRAM read-write labels；SRAM current states are write from memory
Think idle state, when there is equipment to read or write SRAM, SRAM current states need to be set to read states or write state by FPGA, read or
After the completion of write operation, SRAM current states are reverted into idle state；Read-write label be defaulted as idle state, when have equipment read or
When writing SRAM, read-write label need to be set to read-write state by FPGA, when FPGA completes once to read or write SRAM operations, and read read-write
After label, read-write label is reverted into idle state；
(2) FPGA accesses the priority of SRAM higher than MCU；Before the relatively low MCU of priority reads or writes SRAM, MCU first judges
SRAM current states, if SRAM current states are idle state, MCU carries out reading or writing SRAM, inquires and reads after SRAM is read or write
Writing marker for judgment, whether this reads or writes and succeeds, if read-write labeled as read-write state, proves that this read or write fails, if
Read-write then proves this read or write success labeled as idle state；If judging result to read or write failure, need to read again or
It writes, until success；
When the higher FPGA of priority reads or writes SRAM, FPGA N-free diet methods are read or write.
5. the system that a kind of more equipment collaborations according to claim 3 or 4 access SRAM, which is characterized in that further include
RS422 interface circuits, data transmission interface circuit, a host computer for being equipped with data acquisition device；
SRAM is connected with FPGA input/output ports；MCU has the EPI interfaces of peripheral hardware, and other inputs of EPI interfaces and FPGA are defeated
Exit port is connected, and EPI interfaces can be configured as timesharing and access FPGA and SRAM patterns；
The RS422 interface circuits realize the reception of host computer serial port command, and are transmitted to FPGA；
The data transmission interface circuit realizes the transmission of SRAM data；
The host computer is for the transmission of serial port command and the acquisition and parsing of SRAM data；
FPGA can realize that serial port command receives, the timesharing of control EPI interfaces accesses FPGA and SRAM.
6. a kind of system that more equipment collaborations access SRAM according to claim 5, which is characterized in that including：FPGA can
Realize SRAM Read-write Catrols function, data sending function, SRAM state control functions.
7. the system that a kind of more equipment collaborations according to claim 5 access SRAM, which is characterized in that MCU is TI companies
TM4C1294.
8. the system that a kind of more equipment collaborations according to claim 5 access SRAM, which is characterized in that the MCU has outer
If EPI interfaces, can realize 8,16 or 32 parallel-by-bit bus interface.
9. a kind of system that more equipment collaborations access SRAM, which is characterized in that including：MCU、FPGA、SRAM；It is set based on FPGA
Standby, MCU is slave device；FPGA is directly connected with SRAM, and MCU is connected with FPGA, and MCU transfers to the operation of SRAM by FPGA real
It is existing；The priority that FPGA accesses SRAM is higher than MCU；Its specific access method is as follows：
(1) SRAM orders are read：Host computer, which is sent, reads SRAM orders, and FPGA receives and parses through order by serial ports；
(2) SRAM data is read：After FPGA receives reading SRAM orders, N-free diet method generation SRAM read signals, are prohibited SRAM chip selection signals
The data read from SRAM are sent to host computer by only SRAM write enable signal；
(3) SRAM states control：FPGA controls the state of two register tagging SRAM：Respectively SRAM current status registers
Flag register is read and write with SRAM, so that MCU is read；The default conditions of current status register are " idle state ", work as beginning
When reading SRAM operations, current status register is set to " read states ", read operation terminates to revert to current status register " empty
Not busy state " when starting to write SRAM operations, current status register is set to " write state ", write operation terminates current state
Register reverts to " idle state ", and read-write flag register is defaulted as idle state, when starting to read SRAM operations, will read and write
Flag register is set to read-write state；
(4) SRAM data is write：The interaction of the EPI interfaces and FPGA of FPGA controls MCU, before SRAM is write, MCU is inquired first
SRAM current status registers, when being " idle state ", MCU writes SRAM by the initiation of EPI interfaces and operates, and FPGA judges that SRAM works as
Preceding state, if currently empty spare time state, FPGA are sent to the following signals of SRAM：MCU writes SRAM signals, SRAM chip selection signals, writes
SRAM data signal, otherwise FPGA do not send above-mentioned signal；After the completion of MCU writes SRAM operations, MCU inquiry SRAM read-write labels are posted
Storage, if read-write flag register is read-write state, then it represents that received during writing SRAM and read SRAM orders, write during SRAM is forced
It is disconnected, SRAM operation failures are write, MCU sends order and SRAM read-write flag registers are set to idle state at this time, and FPGA receives life
Read-write flag register is set to idle state, while this data is re-write SRAM by MCU after order, is until being write as work(
Only.
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