WO2019165954A1

WO2019165954A1 - Data bit width conversion method and device, and computer-readable storage medium

Info

Publication number: WO2019165954A1
Application number: PCT/CN2019/076141
Authority: WO
Inventors: 杨意
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2018-03-01
Filing date: 2019-02-26
Publication date: 2019-09-06
Also published as: CN110221994B; CN110221994A

Abstract

A data bit width conversion method and device, and a computer-readable storage medium. The method comprises: generating, according to parallel data conversion information, control information of data bit width conversion; and performing, based on the control information, parallel data bit width conversion, a cross-clock-domain operation and cross-clock anti-jitter processing. According to the embodiments of the present invention, the matching of a parallel data bit width between a PCS/FEC and Serdes of various interface protocols can be realized.

Description

Method and device for data bit width conversion, computer readable storage medium

Technical field

Embodiments of the present invention relate to, but are not limited to, the field of digital communication technologies, and in particular, to a method and apparatus for data bit width conversion, and a computer readable storage medium.

Background technique

In the field of digital communication, it is often used in chip cascading, backplane interconnection, etc., and is widely applicable to the Common Public Radio Interface (CPRI), Ethernet, and high-speed serial computer expansion bus standard (PCIE, Peripheral). In the high-speed serial interface technology, such as Component Interconnect Express) and JESD204, serial/parallel-serial converter (Serdes), one of the key technologies, uses the physical coding sublayer (PCS) of different protocol scenarios and different physical media. The related layers are connected to realize high-speed transmission of data on different media such as cables and optical fibers.

The PCS encoding mode is different in different protocol application scenarios. In the same protocol scenario, the specific PCS encoding mode can also be in various forms. For example, the JESD204B protocol uses 8B/10B encoding, and the JESD204C includes 64B/66B and 64B/80B, such as 128B/130B encoding in the PCIE protocol. In the IEEE 802.3 protocol standard, the coding methods contained in the PCS are different under different transmission rates, for example, 100BASE-X uses 4B/5B encoding, 1GBASE-R uses 8bB/10B encoding, and 10GBASE-R uses 64B/66B encoding. When the 50G rate or higher, the PCS needs to have a distribution function, and to support Forward Error Correction (FEC) or RS (Reed Solomon)-FEC, according to its specific FEC/RS-FEC The degree of parallelism of the implementation methods is different, and the bit width of the parallel data that causes the PCS to interact with Serdes is related to the degree of parallelism of the implementation method. Often the parallel data bit width supported by Serdes does not exactly match the parallel bit width of the PCS encoded output. Therefore, a flexible and efficient cross-clock high-speed data bit width conversion solution is required without changing the data transfer rate. It became a key issue for parallel data docking between PCS and Serdes. For this problem, no effective solution has been proposed yet.

Summary of invention

Embodiments of the present invention provide a data bit width conversion method and apparatus, and a computer readable storage medium, to implement parallel data bit width matching between PCS/FEC and Serdes of each interface protocol.

The application provides the following technical solutions.

A method of data bit width conversion, comprising:

Generating control information for data bit width conversion according to parallel data conversion information;

Parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing are performed based on the control information.

The parallel data conversion information includes: a first parallel data bit width and a first clock frequency before conversion, and a converted second parallel data bit width and a second clock frequency.

Before the step of generating control information for data bit width conversion according to the parallel data conversion information, the method further includes: determining, according to the parallel data conversion information, whether data transmission rates before and after conversion are consistent; The data conversion information, the step of generating control information for data bit width conversion includes: generating control information for data bit width conversion according to the parallel data conversion information when the data transmission rates before and after the conversion are the same.

The step of determining whether the data transmission rates before and after the conversion are consistent according to the parallel data conversion information includes: determining a product of a first parallel data bit width before conversion and a corresponding first clock frequency, and converting the second parallel data. Whether the product of the bit width and the second clock frequency is the same.

The step of determining whether the data transmission rates before and after the conversion are consistent according to the parallel data conversion information includes: generating, according to the parallel data conversion information, based on w _i *N _i =w _o *N _o =LCM Control information; wherein LCM is the least common multiple of w _i and w _o , w _i represents the first parallel data bit width before conversion, w _o represents the converted second parallel data bit width, and N _i represents the first clock frequency The number of cycles of writing data, N _o represents the number of cycles of reading data at the second clock frequency.

The step of generating control information for data bit width conversion according to the parallel data conversion information includes: generating an indication including the indication when the first parallel data bit width before the conversion is smaller than the converted second parallel data bit width Control information of a mode of routing information; when the first parallel data bit width before the conversion is greater than the converted second parallel data bit width, generating control information including routing information indicating the second mode; wherein, the first In the mode, the parallel data bit width conversion is prior to the cross clock domain operation; in the second mode, the cross clock domain operation is prior to the parallel data bit width conversion mode.

The control information includes: routing information, the routing information is used to indicate a mode used for data bit width conversion, and the mode includes a first mode or a second mode, where the parallel mode is performed in the first mode. Data bit width conversion first, the cross clock domain operation is followed, in the second mode, the cross clock domain operation is prior, and the parallel data bit width is converted after;

The step of performing data bit width conversion, cross-clock domain operation, and cross-clock anti-shake processing based on the control information includes: performing data bit width conversion, cross-clock domain operation, and cross-clock prevention by using a mode indicated by the routing information Jitter processing.

Wherein, when the routing information included in the control information is indicated as the first mode, the input data first completes the data bit width conversion of the first parallel data bit width to the second parallel data bit width at the first clock frequency, and then The data of the second parallel data bit width performs a cross-clock domain operation from the first clock frequency to the second clock frequency, and performs cross-clock anti-shake processing during the cross-clock operation.

Wherein, when the routing information included in the control information is indicated as the second mode, the data of the first parallel data bit width first completes the cross-clock domain operation from the first clock frequency to the second clock frequency, and is in a cross-clock operation process. Performing cross-clock anti-shake processing, and then performing data bit width conversion of the first parallel data bit width to the second parallel data bit width at the second clock frequency.

The control information includes: buffer configuration information, where the buffer configuration information includes: capacity information of the buffer unit, and read and write configuration information;

And generating a buffer unit corresponding to the storage capacity according to the capacity information of the buffer unit, and completing the parallel data bit width conversion according to the read/write configuration information of the buffer unit.

The control information includes: storage configuration information, where the storage configuration information includes: capacity information of the storage unit, and read and write configuration information;

Generating a storage unit of a corresponding storage capacity according to the capacity information of the storage unit, and completing the cross-clock domain operation of the same data bit width according to the read/write configuration information of the storage unit.

The control information includes: anti-jitter configuration information, where the anti-jitter configuration information includes: period information of anti-shake monitoring and a read-write recovery address;

The cross-clock anti-shake processing includes: monitoring the read/write address of the storage unit according to the period information of the anti-shake monitoring; if the relative offset of the read/write address is within the jitter range tolerance information, The read/write address is maintained; if the relative offset of the read/write address is not within the jitter range tolerance information, the read/write address is restored according to the read/write recovery address.

A data bit width conversion device includes: a controller and a data bit width conversion circuit;

The controller includes: a storage unit configured to store a computer program, the processing unit configured to read the computer program to perform an operation of generating a data bit according to the parallel data conversion information Wide conversion control information;

The data bit width conversion circuit is configured to perform parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing based on the control information.

The processing unit is configured to read the computer program to perform an operation of: determining, according to the parallel data conversion information, whether data transmission rates before and after conversion are consistent; when data transmission rates before and after conversion are consistent, according to parallel data The conversion information generates control information for data bit width conversion.

Wherein the processing unit is configured to read the computer program to perform the following operations:

Generating the control information according to the parallel data conversion information and based on w _i *N _i =w _o *N _o =LCM;

Where LCM is the least common multiple of w _i and w _o , w _i represents the first parallel data bit width before conversion, w _o represents the converted second parallel data bit width, and N _i represents the data written at the first clock frequency. number of cycles, N _o represents the number of read data at a second frequency clock cycle.

Generating control information including routing information indicating the first mode when the first parallel data bit width before the conversion is less than the converted second parallel data bit width;

Generating control information including routing information indicating the second mode when the first parallel data bit width before the conversion is greater than the converted second parallel data bit width;

In the first mode, the parallel data bit width conversion is prior to the cross-clock domain operation; in the second mode, the cross-clock domain operation is prior, and the parallel data bit width is converted. Rear.

The storage unit is further configured to store the control information;

The data bit width conversion circuit is configured to read the control information from the storage unit, and perform parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing based on the control information.

The control information includes: routing information, where the routing information is used to indicate a first mode and a second mode of data bit width conversion, and in the first mode, the parallel data bit width is converted first, After the cross-clock domain operation, in the second mode, the cross-clock domain operation is prior to the parallel data bit width conversion; the data bit width conversion circuit is configured to: use the routing information to indicate The mode performs data bit width conversion, cross clock domain operation, and cross clock anti-shake processing.

The data bit width conversion circuit includes: a data bit width conversion buffer module, a cross clock domain storage module, and a cross clock anti-jitter module; the data bit width conversion buffer module is configured to complete parallel data bit width conversion; The cross-clock domain storage module is configured to perform cross-clock domain operation; the cross-clock anti-jitter module is configured to complete cross-clock anti-shake processing; wherein the data bit width conversion buffer module and the cross-clock domain storage module The inter-clock domain storage module is interoperable with the cross-clock anti-jitter module.

A computer readable storage medium having stored thereon a computer program, the computer program being executed by a processor to perform the following operations:

Based on the parallel data conversion information, control information for data bit width conversion is generated such that the data bit width conversion circuit performs parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing based on the control information.

Wherein, when the computer program is executed by the processor, the following operations are performed:

Determining whether the data transmission rates before and after the conversion are consistent according to the parallel data conversion information; and generating control information for data bit width conversion according to the parallel data conversion information when the data transmission rates before and after the conversion are consistent.

Determining whether the product of the first parallel data bit width before conversion and its corresponding first clock frequency, and the product of the converted second parallel data bit width and the second clock frequency are the same, and generating the same according to the parallel data conversion information Control information for data bit width conversion.

The control information includes one or more of the following:

The routing information is used to indicate a mode used by the data bit width conversion, where the mode is a first mode or a second mode, and in the first mode, the parallel data bit width conversion is prior to the cross clock domain operation After the second mode, the cross-clock domain operation is prior to the parallel data bit width conversion;

The buffer configuration information used for the parallel data bit width conversion includes: capacity information of the buffer unit, and read and write configuration information;

Storage configuration information for the operation of the cross-clock domain, including: capacity information of the storage unit, read and write configuration information;

The anti-jitter configuration information used for the cross-clock anti-shake processing includes: period information of anti-shake monitoring and a read/write recovery address.

In the embodiment of the invention, the parallel data bit width matching between the PCS/FEC and the Serdes of each interface protocol can be realized, and the trans-clock high-speed data bit width conversion can be flexibly and efficiently realized without changing the data transmission rate, thereby reducing PCS and Serdes. Constraint in actual design.

The embodiment of the invention can be widely applied to various protocol scenarios such as CPRI, Ethernet, PCIE and JESD204 and different transmission rate requirements in the communication technology, and can support the conversion function of any parallel data bit width between the PCS and the Serdes of the high-speed serial port protocol. , with great versatility and compatibility.

Other features and advantages of the invention will be set forth in the description which follows, The objectives and other advantages of the invention may be realized and obtained by means of the structure particularly pointed in the appended claims.

BRIEF abstract

The drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the specification, which together with the embodiments of the present application are used to explain the technical solutions of the present invention, and do not constitute a limitation of the technical solutions of the present invention.

1 is a schematic flow chart of a data bit width conversion method according to Embodiment 1;

2 is a schematic flow chart of a specific implementation manner of a data bit width conversion method;

3 is a schematic diagram of a trend of a data stream in a data conversion circuit in a first mode;

4 is a schematic diagram showing a trend of a data flow in a data conversion circuit in a second mode;

5 is a schematic structural diagram of a data bit width conversion device of Embodiment 2;

6 is a block diagram showing an exemplary embodiment of a data bit width conversion device.

Detailed

The following is a summary of the subject matter described in detail herein, and is not intended to limit the scope of the claims.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments in the present application may be arbitrarily combined with each other.

The steps illustrated in the flowchart of the figures may be executed in a computer system such as a set of computer executable instructions. Also, although the logical order is shown in the flowcharts, in some cases, the steps shown or described may be performed in a different order than the ones described herein.

For the problem that the parallel data bit width mismatch between the PCS/FEC and the Serdes of each interface protocol in the related art, the following technical solutions are provided.

The implementation manner of the technical solution of the present application is described in detail below.

Embodiment 1

As shown in FIG. 1, a method for data bit width conversion according to an embodiment of the present invention includes:

Step 101: Generate control information for data bit width conversion according to parallel data conversion information.

Step 102: Perform parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing based on the control information.

In this embodiment, the parallel data conversion information may include: a first parallel data bit width and a first clock frequency before conversion, and a converted second parallel data bit width and a second clock frequency.

In this embodiment, before the generating the control information for the data bit width conversion according to the parallel data conversion information, the method may further include: determining, according to the parallel data conversion information, whether the data transmission rate before and after the conversion is consistent;

The generating control information for data bit width conversion according to the parallel data conversion information includes: generating control information for data bit width conversion according to the parallel data conversion information when the data transmission rates before and after the conversion are consistent.

Here, determining whether the data transmission rate before and after the conversion is consistent according to the parallel data conversion information may include: determining a product of a first parallel data bit width before conversion and a corresponding first clock frequency, and converting the second parallel data. Whether the product of the bit width and the second clock frequency is the same. If they are the same, the data transmission rate before and after the conversion is the same. If they are not the same, the data transmission rate before and after the conversion is inconsistent.

In an exemplary implementation, the generating control information for data bit width conversion according to the parallel data conversion information may include: converting information according to the parallel data and based on w _i *N _i =w _o *N _o = LCM, generating the control information; wherein LCM is the least common multiple of w _i and w _o , w _i represents the first parallel data bit width before conversion, and w _o represents the converted second parallel data bit width, N _i represents the number of cycles of writing data at the first clock frequency, and N _o represents the number of cycles of reading data at the second clock frequency.

In an exemplary implementation, the generating control information for data bit width conversion according to the parallel data conversion information may include: the first parallel data bit width before the conversion is smaller than the converted second parallel data bit Width-time, generating control information including routing information indicating the first mode; generating control information including routing information indicating the second mode when the first parallel data bit width before the conversion is greater than the converted second parallel data bit width Wherein, in the first mode, the parallel data bit width conversion is prior to the cross-clock domain operation; and in the second mode, the cross-clock domain operation is prior to the parallel data bit The width is converted later.

In an exemplary implementation, the control information may include: routing information, where the routing information is used to indicate a mode used for data bit width conversion, where the mode is a first mode or a second mode, where the first In the mode, the parallel data bit width conversion is preceded by the cross clock domain operation, and in the second mode, the cross clock domain operation is prior, and the parallel data bit width is converted later. The performing data bit width conversion, the cross-clock domain operation, and the cross-clock anti-shake processing based on the control information may include: performing data bit width conversion, cross-clock domain operation, and cross-clock prevention by using the mode indicated by the routing information. Jitter processing.

Specifically, when the routing information included in the control information is indicated as the first mode, the input data first performs data bit width conversion from the first parallel data bit width to the second parallel data bit width at the first clock frequency, and then The data of the second parallel data bit width performs a cross-clock domain operation from the first clock frequency to the second clock frequency, and performs cross-clock anti-shake processing during the cross-clock operation.

Specifically, when the routing information included in the control information is indicated as the second mode, the data of the first parallel data bit width first completes the cross-clock domain operation from the first clock frequency to the second clock frequency, and operates across the clock. The process performs cross-clock anti-shake processing, and then performs data bit width conversion of the first parallel data bit width to the second parallel data bit width at the second clock frequency.

In an exemplary implementation, the control information may include: buffering configuration information, where the buffering configuration information includes: capacity information of the buffer unit, read and write configuration information, and generating a corresponding storage capacity according to the capacity information of the buffer unit. And buffering the unit, and completing the parallel data bit width conversion according to the read/write configuration information of the buffer unit.

In an exemplary implementation, the control information may include: storage configuration information, where the storage configuration information includes: capacity information of the storage unit, read and write configuration information; and generating a corresponding storage capacity according to the capacity information of the storage unit. The storage unit performs the cross-clock domain operation of the same data bit width according to the read and write configuration information of the storage unit.

In an exemplary implementation, the control information may include: anti-jitter configuration information, where the anti-jitter configuration information includes: period information of anti-shake monitoring and a read/write recovery address. The cross-clock anti-shake processing may include: monitoring a read/write address of the storage unit according to the period information of the anti-shake monitoring; if the relative offset of the read/write address is within the jitter range tolerance information, And maintaining the read/write address; if the relative offset of the read/write address is not within the jitter range tolerance information, recovering the read/write address according to the read/write recovery address.

In practical applications, the foregoing method in this embodiment can be implemented in a software and hardware cooperative manner, and supports conversion of an arbitrary data bit width. Specifically, in the above method of the embodiment, the parallel data conversion information is first set to the software and is arbitrated by the software (ie, whether to perform data bit width conversion); the control information for data conversion is generated by software calculation; the hardware part According to the control information, the mode used for data bit width conversion is automatically matched; the hardware part performs corresponding data bit width conversion according to this mode, and the data bit width conversion includes: parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing. . In this way, the software calculates the control information when generating the data conversion, which greatly reduces the hardware logic resources and greatly enriches the flexibility of the hardware design; the software controllable cross-clock anti-jitter also has universal applicability. Meet the anti-jitter requirements of different clock frequencies, so that the system has better stability.

The above method of the embodiment can be widely applied to various protocol scenarios such as CPRI, Ethernet, PCIE and JESD204 in communication technologies and different transmission rate requirements, and can support any parallel data bit width between PCS and Serdes of high-speed serial port protocols. The conversion function has strong versatility and compatibility; the method of the embodiment can realize parallel data bit width matching of different PCS and Serdes, and reduces the constraint of PCS and Serdes in actual design.

The specific implementation process of the present application will be described below.

As shown in FIG. 2, the above data bit width conversion method of this embodiment may include the following steps:

Step 201 to step 203, setting parallel data conversion information to the software and arbitrating by software.

Specifically, the parallel data conversion information is set, and the software arbitration parallel data conversion information is correct. If it is correct, the process proceeds to step 204. If not, the software prompts an input error and prompts to re-enter the correct parallel data conversion information.

Here, the parallel data conversion information input to the software may include the parallel data bit width w _i and the corresponding clock frequency f _{i before} conversion and the converted parallel data bit width w _o and the corresponding clock frequency f _o , in order to ensure PCS and Serdes. The data transmission rate is consistent, and the software determines whether the input information satisfies the condition w _i *f _i =w _o *f _o . If it is not satisfied, the information is incorrect, and the parallel conversion information needs to be re-entered; if it is satisfied, the information is correct.

Step 204 to step 205, calculating and generating control information for data conversion.

Specifically, the software calculates and generates data conversion control information, and stores the control information in the control information storage module.

Here, the process of calculating the control information may include: the software generates routing information according to w _i and w _o , calculates buffer configuration information required for parallel data bit width conversion, storage configuration information required for operation across clock domains, and cross-clock anti-jitter Process the required anti-jitter configuration information and write these related control information to the control information storage module. In order to complete the read and write control of the data bit width conversion buffer module and the cross clock storage module based on the information and automatically calculate the buffer storage capacity corresponding to the corresponding depth (ie, the buffer unit below) and the cross clock storage capacity (ie, the following storage unit) ).

The buffer configuration information, the storage configuration information, and the anti-jitter configuration information may be calculated according to the formula w _i *N _i =w _o *N _o =LCM. Where LCM is the least common multiple of w _i and w _o , N _i represents the number of cycles of writing data at clock frequency f _i , and N _o represents the number of cycles of reading data at clock frequency f _o .

The buffering configuration information includes: capacity information of the buffer unit, read and write configuration information, and the read/write configuration information of the buffer unit may include: read/write control information of the buffer unit and specific read/write position information.

The storage configuration information includes: storage unit capacity information and read/write configuration information, and the read/write configuration information of the storage unit may include read/write control information and read/write address information of the storage unit.

The anti-jitter configuration information includes: period information of anti-shake monitoring and a read/write recovery address.

The routing information is used to indicate a mode used for data bit width conversion, where the mode is a first mode or a second mode, and in the first mode, the parallel data bit width conversion is prior to the cross clock domain operation Thereafter, in the second mode, the cross-clock domain operation is prior, and the parallel data bit width is converted later. If w _i <w _o , the routing information indicates the first mode, and if w _i >w _o , the routing information indicates the second mode. If w _i =w _o , no data bit width conversion is needed, and it is not necessary to generate routing information and calculate various types of configuration information.

Steps 206 to 212, the data bit width conversion circuit reads the control information and performs parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing based on the control information.

Step 206: Read control information from the control information storage module, and perform data bit width conversion according to the mode indicated by the routing information in the control information.

If the routing information indicates the first mode, the data flow is processed according to the path shown in FIG. 3, and steps 207 to 209 are performed, and the input data first enters the data bit width conversion buffer module for parallel data bit width conversion, at the clock frequency. The conversion of the data bit width from w _i to w _o is completed under f _i , and then the converted data enters the cross-clock memory module for cross-clock domain operation, and the data of w _o bit width is completed from the clock frequency f _i to the clock frequency f _o Conversion, cross-clock anti-shake processing is performed by the cross-clock anti-jitter module during the conversion of the cross-clock storage module.

Specifically, if w _i <w _o , the data bit width conversion buffer module first acquires the buffer information of the buffer unit from the control information storage module to generate the buffer unit of the corresponding storage capacity, that is, the data bit width conversion buffer module generates the minimum storage as w _i *(N _i -N _o +1) bits (that is, buffer unit capacity information) buffer unit, buffer unit (according to read and write control information and read and write address information) continuously write w _i bit width data, when writing (N _i -N _o) after the shot, the data read from the buffer unit bit width w _o, N _o and read continuously shot, and then stops reading (N _i -N _o) beat, and in accordance with the periodic law The read, completes the conversion of the data bit width in the same clock domain. Then, the cross-clock storage module acquires the capacity information of the storage unit from the control information storage module to generate a storage unit of the corresponding storage capacity, and performs the cross-clock domain operation on the data of the w _o -bit width converted by the bit width through the storage unit, and writes the storage unit the same clock frequency f _i, the read clock frequency f _o, the write enable buffer unit periodicity and the read cycle, read enable enable enable delay by the write clock is generated after N _o cross shot, which avoids the read-write delay Conflicts, and continue to be valid after generation, the depth of the memory cell is 2*N _o +X, where X is the write enable enable maximum stable time data for read enable to complete the operation across the clock domain through the memory unit.

If the routing information is in the second mode, the data flow is processed according to the path shown in FIG. 4, and the steps 210 to 212 are performed. The input data first enters the cross-clock storage module to perform the cross-clock domain operation, and the w _i -bit width is completed. The data is converted from the clock frequency f _i to the clock frequency f _o , and the cross-clock anti-shake module is processed by the cross-clock anti-shake module during the conversion process of the cross-clock memory module, and then the data converted across the clock enters the data bit width. The conversion buffer module performs parallel data bit width conversion, and completes the conversion of the data bit width from w _i to w _o at the clock frequency f _o .

Specifically, if w _i >w _o , the cross-clock storage module acquires the storage unit capacity information from the control information storage module to generate a storage unit corresponding to the storage capacity, and the w _i -bit wide data is first written into the storage unit to perform cross-clock domain operation. The write clock frequency of the memory cell is f _i and the read clock frequency is f _o . The write enable of the memory cell is always valid after the data is valid. According to the relationship of w _i *N _i =w _o *N _o =LCM, The depth of the memory cell is 2*N _i +X, and the read enable is generated by the write enable delay N _i after the clock. This delay avoids read and write conflicts, and the read enable is continuously read and continuously read from the effective. N _i beat, then stop reading (N _o -N _i ) beat, and periodically read according to the law, complete the conversion of the clock domain; after that, the data bit width conversion buffer module obtains the buffer unit from the control information storage module The capacity information (w _i *(N _i -N _o +1) bits) generates a buffer unit that is minimally stored as w _i *(N _i -N _o +1) bits, and w _i bits wide after the clock The write buffer unit performs bit width conversion, and the minimum storage of the buffer unit is [w _i +(w _i -w _o )*(N _i -1) ], and the write enable of the buffer unit is the same as the read enable of the memory unit, both of which are consecutively written to N _i beats, then stop writing (N _o -N _i ) beats, and periodically follow the rule, and Since w _i >w _o , the buffer unit can start reading the w _o bit width data after writing a beat w _i , and the read enable remains valid after the data is valid, and the parallel data bit width conversion is completed.

When the cross-clock anti-shake processing is completed according to the control information, the cross-clock read/write period has a certain constraint relationship w _i *N _i *N=w _o *N _o *N=LCM*N, where N is anti-shake detection The number of traversal cycles of the storage unit is calculated by the software based on the constraint relationship described above and configured in the control information storage module and read and executed by the cross-clock anti-jitter module. At the interval of LCM*N, the read/write addresses of the memory cells of the inter-clock memory module should be in a one-to-one correspondence, so the anti-shake processing detects the read/write address of the memory cell as a read/write address at a periodic monitoring point. The address is restored, and the corresponding read/write address of the monitoring point is recorded in the control information storage module. If the deviation range of the detection address of the storage unit exceeds half of the depth of the storage unit, the read address of the storage unit is forcibly restored to the recorded Read and write recovery addresses to avoid read and write conflicts and complete cross-clock anti-shake processing.

Embodiment 2

A data bit width conversion device, as shown in Figure 5, comprising: a controller 51 and a data bit width conversion circuit 52;

The controller 51 includes a storage unit and a processing unit (not shown) configured to store a computer program, the processing unit configured to read the computer program to perform an operation of: converting according to parallel data Information, generating control information for data bit width conversion;

The data bit width conversion circuit 52 is configurable to perform parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing based on the control information.

In this embodiment, the processing unit is configured to read the computer program to perform an operation of: determining, according to the parallel data conversion information, whether data transmission rates before and after conversion are consistent; when data transmission rates before and after conversion are consistent, Control information for data bit width conversion is generated based on the parallel data conversion information.

In this embodiment, the processing unit is configured to read the computer program to perform an operation of: generating the control according to the parallel data conversion information and based on w _i *N _i =w _o *N _o =LCM Information; wherein LCM is the least common multiple of w _i and w _o , w _i represents the first parallel data bit width before conversion, w _o represents the converted second parallel data bit width, and N _i represents the first clock frequency write The number of cycles of data, N _o represents the number of cycles of reading data at the second clock frequency.

In this embodiment, the processing unit is configured to read the computer program to perform an operation of: generating an indication including the first when the first parallel data bit width before the conversion is smaller than the converted second parallel data bit width Control information of the routing information of the mode; generating control information including routing information indicating the second mode when the first parallel data bit width before the conversion is greater than the converted second parallel data bit width; wherein the first mode The parallel data bit width conversion is preceded by the cross clock domain operation; in the second mode, the cross clock domain operation is prior, and the parallel data bit width is converted later.

In this embodiment, the storage unit is further configured to store the control information; the data bit width conversion circuit is configured to read the control information from the storage unit, and perform the control information based on the control information. Parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing. In an implementation manner, the storage unit may include a control information storage module, and the control information storage module is configured to store the control information.

In this embodiment, the control information may include: routing information, where the routing information is used to indicate a first mode and a second mode of data bit width conversion, where the parallel data bit width is converted in the first mode First, the cross-clock domain operation is followed. In the second mode, the cross-clock domain operation is prior to the parallel data bit width conversion; the data bit width conversion circuit 52 is configured to: adopt The mode indicated by the routing information performs data bit width conversion, cross clock domain operation, and cross clock anti-shake processing.

As shown in FIG. 5, the data bit width conversion circuit 52 may include: a data bit width conversion buffer module 521, a cross clock domain storage module 522, and a cross clock anti-jitter module 523; wherein, the data bit width conversion buffer module is used. After the parallel data bit width conversion is completed, the cross clock domain storage module 522 is used to complete the cross clock domain operation, and the cross clock anti-jitter module 523 is used to complete the cross clock anti-shake processing. The data bit width conversion buffer module 521 and the cross-clock domain storage module 522 are intercommunicated, and the cross-clock domain storage module 522 and the cross-clock anti-shake module 523 are intercommunicated.

Specifically, when the first parallel data bit width before the conversion is smaller than the converted second parallel data bit width, the input data first enters the data bit width conversion buffer module 521, and the first parallel is completed at the first clock frequency. Data bit width to data width bit width conversion of the second parallel data bit width, and then converted into data of the second parallel data bit width into the cross clock domain memory module 522, performing conversion from the first clock frequency to the second clock frequency Inter-clock anti-shake processing is performed by the cross-clock anti-shake module 523 during operation across the clock domain and during operation across the clock domain.

Specifically, when the first parallel data bit width before the conversion is greater than the converted second parallel data bit width, the data of the first parallel data bit width is input to the cross-clock domain storage module 522, and the first clock frequency is first completed. Converting to a cross-clock domain operation of the second clock frequency, and performing cross-clock anti-shake processing by the cross-clock anti-jitter module 523 during operation across the clock domain, and then entering the data bit width conversion buffer module 521, The data width-to-width conversion of the first parallel data bit width to the second parallel data bit width is completed at the second clock frequency.

In this embodiment, the control information may include: buffer configuration information, where the buffer configuration information includes: capacity information of the buffer unit, and read and write configuration information; and the data bit width conversion buffer module 521 is specifically configured to use the capacity of the buffer unit. The information generates a buffer unit 5211 of the corresponding storage capacity, and completes the data bit width conversion according to the read/write configuration information of the buffer unit 5211.

In this embodiment, the control information may include: storage configuration information, where the storage configuration information includes: storage unit capacity information, read-write configuration information; the cross-clock domain storage module 522 is specifically configured to use the storage unit capacity information. The storage unit 5222 of the corresponding storage capacity is generated, and the cross-clock domain operation of the same data bit width is completed according to the read and write configuration information of the storage unit 5222.

In this embodiment, the control information may include: anti-shake configuration information, where the anti-jitter configuration information includes: anti-jitter monitoring period information and a read-write recovery address; the cross-clock anti-jitter module 523 may be specifically used for And monitoring the read/write address of the storage unit 5222 according to the period information of the anti-shake monitoring; if the relative offset of the read/write address is within the jitter range tolerance information, maintaining the read/write address; If the relative offset of the write address is not within the jitter range tolerance information, the read/write address is restored according to the read/write recovery address.

FIG. 6 is a schematic structural diagram of an exemplary embodiment of the foregoing apparatus according to the embodiment. The data bit width conversion device is arranged between the PCS and the Serdes to realize the conversion of any parallel data bit width between the PCS and the Serdes of the high speed serial port protocol.

In FIG. 6, for the controller, the input is the parallel data bit width w _i before conversion and the corresponding clock frequency f _i and the converted parallel data bit width w _o and the corresponding clock frequency f _o , according to these data controllers Automatically calculating control information required to generate an arbitrary bit width conversion, the control information including routing information, buffer unit capacity information, storage unit capacity information, buffer unit read and write configuration information, storage unit read and write configuration information, anti-shake The controller may store the calculated control information in a hardware control information storage module for use by the data bit width conversion circuit. Here, the control information storage module is responsible for storing the control information required for each step of the data bit width conversion, and converting the control information into the data bit width buffer module, the cross clock storage module, and the cross clock prevention. Jitter module.

In FIG. 6, if w _i <w _o , the controller generates routing information indicating the first mode, and if w _i >w _o , the controller generates routing information indicating the second mode. In the first mode, the input data first enters the data bit width conversion buffer module, completes the conversion of the data bit width from w _i to w _o at the clock frequency f _i , and then enters the converted data into the cross-clock storage module to complete w _o The bit width data is converted from the clock frequency f _i to the clock frequency f _o ; finally, the cross clock anti-jitter module is input for cross-clock anti-shake processing. In the second mode, the input data first enters the cross-clock storage module, and the data of the w _i -bit width is converted from the clock frequency f _i to the clock frequency f _o , and then the data after the cross-clock operation enters the cross-clock anti-jitter module for cross- The clock anti-shake processing finally enters the data bit width conversion buffer module to complete the conversion of the data bit width from w _i to w _o at the clock frequency f _o .

In FIG. 6, the data bit width conversion buffer module is responsible for obtaining the buffer unit of the corresponding storage capacity by acquiring the capacity information of the buffer unit from the control information storage module, and then completing the data bit width according to the buffer unit read/write control information and the specific read/write position information. Conversion.

In FIG. 6, the cross-clock storage module is responsible for acquiring the storage unit capacity information from the control information storage module to generate a storage unit corresponding to the storage capacity, and then completing the crossover of the same data bit width according to the read/write control information and the read-write address information of the storage unit. Clock domain function.

In Figure 6, the cross-clock anti-jitter module is responsible for obtaining the period information of the anti-jitter monitoring from the control information storage module, and monitoring the read/write address of the cross-clock storage unit according to the period, if the relative offset of the read-write address is In the jitter range tolerance information, the corresponding read/write address is maintained. Otherwise, the read address recovery is completed according to the recovery information of the read address, and the cross-clock anti-shake function is implemented.

The above device in this embodiment performs arbitrary data bit width conversion by cooperative processing of software and hardware. For other technical details of this embodiment, refer to the first embodiment.

The device of the embodiment can realize the parallel data bit width matching of different PCS and Serdes, and reduces the constraint of the design of the PCS and the Serdes; the software calculates the control information required for the data conversion, thereby greatly reducing the hardware logic resources. And greatly enrich the flexibility of hardware design; software controllable cross-clock anti-jitter design also has universal applicability, meet the anti-jitter requirements of different clock frequencies, and enhance the stability of the system.

The above device of the present embodiment can be widely applied to various protocol scenarios such as CPRI, Ethernet, PCIE and JESD204 in communication technologies and different transmission rate requirements. The method and device can support any parallel data between PCS and Serdes of high-speed serial port protocols. The bit width conversion function is extremely versatile and compatible.

Embodiment 3

A computer readable storage medium having stored thereon a computer program, the computer program being executed by a processor to perform an operation of: generating control information for data bit width conversion according to parallel data conversion information So that the data bit width conversion circuit performs parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing based on the control information.

In this embodiment, the parallel data conversion information includes: a first parallel data bit width and a first clock frequency before conversion, and a converted second parallel data bit width and a second clock frequency.

In this embodiment, when the computer program is executed by the processor, the following operations are performed: determining whether the data transmission rate before and after the conversion is consistent according to the parallel data conversion information; and converting the data according to the parallel data when the data transmission rates before and after the conversion are consistent Generate control information for data bit width conversion. In one implementation, the computer program is executed by the processor to: determine a product of a first parallel data bit width before conversion and a corresponding first clock frequency, and a second parallel data bit width after conversion Whether the product of the second clock frequency is the same, and the same is used to generate control information for data bit width conversion based on the parallel data conversion information. In addition, other methods can be used, and will not be described again.

In an implementation manner of this embodiment, when the computer program is executed by the processor, the following operations are performed: generating the control according to the parallel data conversion information and based on w _i *N _i =w _o *N _o =LCM Information; LCM is the least common multiple of w _i and w _o , w _i represents the first parallel data bit width before conversion, w _o represents the converted second parallel data bit width, and N _i represents the data written at the first clock frequency. number of cycles, N _o represents the number of read data at a second frequency clock cycle.

In this embodiment, when the computer program is executed by the processor, the following operations are performed: when the first parallel data bit width before the conversion is smaller than the converted second parallel data bit width, generating routing information indicating the first mode is generated. Control information; when the first parallel data bit width before the conversion is greater than the converted second parallel data bit width, generating control information including routing information indicating the second mode; wherein, in the first mode, the parallel The data bit width conversion is prior to the cross clock domain operation; in the second mode, the cross clock domain operation is prior, and the parallel data bit width is converted later.

In this embodiment, the control information includes one or more of the following:

Storage configuration information for the operation of the cross-clock domain, including: capacity information of the storage unit, and read and write configuration information;

Other technical details of this embodiment can be referred to the first embodiment, and details are not described herein again.

Other aspects will be apparent upon reading and understanding the drawings and detailed description.

One of ordinary skill in the art will appreciate that all or a portion of the above steps may be performed by a program to instruct related hardware, such as a processor, which may be stored in a computer readable storage medium, such as a read only memory, disk or optical disk. Wait. Alternatively, all or part of the steps of the above embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the above embodiment may be implemented in the form of hardware, for example, by implementing an integrated circuit to implement its corresponding function, or may be implemented in the form of a software function module, for example, executing a program stored in the memory by a processor. / instruction to achieve its corresponding function. This application is not limited to any specific combination of hardware and software.

The basic principles and main features of the present application and the advantages of the present application are shown and described above. The present application is not limited by the above-described embodiments, and the above-described embodiments and the description are only for explaining the principles of the present application, and various changes and modifications may be made to the present application without departing from the spirit and scope of the application. And improvements are within the scope of the claimed invention.

Claims

A method of data bit width conversion, comprising:

Generating control information for data bit width conversion according to parallel data conversion information;

Parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing are performed based on the control information.
The method of data bit width conversion according to claim 1, wherein:

The parallel data conversion information includes: a first parallel data bit width and a first clock frequency before conversion, and a converted second parallel data bit width and a second clock frequency.
A method of data bit width conversion according to claim 2, wherein

Before the step of generating the control information for the data bit width conversion according to the parallel data conversion information, the method further includes: determining, according to the parallel data conversion information, whether the data transmission rate before and after the conversion is consistent;

The step of generating control information for data bit width conversion according to the parallel data conversion information includes: generating control information for data bit width conversion according to the parallel data conversion information when the data transmission rates before and after the conversion are the same.
The data bit width conversion method according to claim 3, wherein the step of determining whether the data transmission rates before and after the conversion are consistent according to the parallel data conversion information comprises:

It is judged whether the product of the first parallel data bit width before conversion and its corresponding first clock frequency, and the product of the converted second parallel data bit width and its corresponding second clock frequency are the same.
The data bit width conversion method according to claim 3, wherein said step of generating control information for data bit width conversion based on said parallel data conversion information comprises:

Generating the control information according to the parallel data conversion information and based on w i *N i =w o *N o =LCM;

Where LCM is the least common multiple of w i and w o , w i represents the first parallel data bit width before conversion, w o represents the converted second parallel data bit width, and N i represents the data written at the first clock frequency. number of cycles, N o represents the number of read data at a second frequency clock cycle.
The data bit width conversion method according to claim 1, wherein said step of generating control information for data bit width conversion based on the parallel data conversion information comprises:

Generating control information including routing information indicating the first mode when the first parallel data bit width before the conversion is less than the converted second parallel data bit width;

Generating control information including routing information indicating the second mode when the first parallel data bit width before the conversion is greater than the converted second parallel data bit width;

Wherein, in the first mode, the parallel data bit width conversion is prior to the cross-clock domain operation; in the second mode, the cross-clock domain operation is prior to the parallel data bit width The conversion is after.
A method of data bit width conversion according to claim 1, wherein

The control information includes: routing information, the routing information is used to indicate a mode used for data bit width conversion, the mode is a first mode or a second mode, and the parallel data bit width conversion is performed in the first mode. After the first and the cross-clock domain operations are performed, in the second mode, the cross-clock domain operation is prior to the parallel data bit width conversion;

The step of performing data bit width conversion, cross-clock domain operation, and cross-clock anti-shake processing based on the control information includes: performing data bit width conversion, cross-clock domain operation, and cross-clock prevention by using a mode indicated by the routing information Jitter processing.
A method of data bit width conversion according to claim 7, wherein:

When the routing information included in the control information is indicated as the first mode, the input data first completes the data bit width conversion of the first parallel data bit width to the second parallel data bit width at the first clock frequency, and then The data of the two parallel data bit widths performs a cross-clock domain operation from the first clock frequency to the second clock frequency, and performs cross-clock anti-shake processing during the cross-clock operation.
A method of data bit width conversion according to claim 7, wherein:

When the routing information included in the control information is indicated as the second mode, the data of the first parallel data bit width first completes the cross-clock domain operation from the first clock frequency to the second clock frequency, and is performed during the cross-clock operation. Cross-clock anti-shake processing, and then completing the data bit width conversion of the first parallel data bit width to the second parallel data bit width at the second clock frequency.
A method of data bit width conversion according to any one of claims 1 to 9, wherein:

The control information includes: buffer configuration information, where the buffer configuration information includes: capacity information of the buffer unit, and read and write configuration information;

The step of performing parallel data bit width conversion based on the control information includes: generating a buffer unit corresponding to the storage capacity according to the capacity information of the buffer unit, and completing the parallel data bit according to the read/write configuration information of the buffer unit Wide conversion.
A method of data bit width conversion according to any one of claims 1 to 9, wherein:

The control information includes: storage configuration information, where the storage configuration information includes: capacity information of the storage unit, and read and write configuration information;

The step of performing cross-clock domain operation processing based on the control information includes: generating a storage unit of a corresponding storage capacity according to the capacity information of the storage unit, and completing the same data bit width according to the read/write configuration information of the storage unit The cross-clock domain operates.
A method of data bit width conversion according to claim 11 wherein:

The control information includes: anti-jitter configuration information, where the anti-jitter configuration information includes: period information of anti-shake monitoring and a read/write recovery address;

The step of performing cross-clock anti-shake processing based on the control information includes: monitoring a read/write address of the storage unit according to the period information of the anti-shake monitoring; if the relative offset of the read/write address is Within the jitter range tolerance information, the read/write address is maintained; if the relative offset of the read/write address is not within the jitter range tolerance information, the read/write address is restored according to the read/write recovery address.
A data bit width conversion device includes: a controller and a data bit width conversion circuit;

The controller includes: a storage unit configured to store a computer program, the processing unit configured to read the computer program to perform an operation of generating a data bit according to the parallel data conversion information Wide conversion control information;

The data bit width conversion circuit is configured to perform parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing based on the control information.
The data bit width conversion device according to claim 13, wherein:

The parallel data conversion information includes: a first parallel data bit width and a first clock frequency before conversion, and a converted second parallel data bit width and a second clock frequency.
The data bit width conversion device according to claim 14, wherein

The processing unit is configured to read the computer program to perform an operation of: determining whether data transmission rates before and after conversion are consistent according to the parallel data conversion information; and converting data according to parallel data when data transmission rates before and after conversion are consistent Generate control information for data bit width conversion.
The data bit width conversion device according to claim 13, wherein said processing section is configured to read said computer program to perform the following operations:

Generating the control information according to the parallel data conversion information and based on w i *N i =w o *N o =LCM;

Where LCM is the least common multiple of w i and w o , w i represents the first parallel data bit width before conversion, w o represents the converted second parallel data bit width, and N i represents the data written at the first clock frequency. number of cycles, N o represents the number of read data at a second frequency clock cycle.
The data bit width conversion device according to claim 13, wherein said processing section is configured to read said computer program to perform the following operations:

Generating control information including routing information indicating the first mode when the first parallel data bit width before the conversion is less than the converted second parallel data bit width;

Generating control information including routing information indicating the second mode when the first parallel data bit width before the conversion is greater than the converted second parallel data bit width;

Wherein, in the first mode, the parallel data bit width conversion is prior to the cross-clock domain operation; in the second mode, the cross-clock domain operation is prior to the parallel data bit width The conversion is after.
The data bit width conversion device according to claim 13, wherein:

The storage unit is further configured to store the control information;

The data bit width conversion circuit is configured to read the control information from the storage unit, and perform parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing based on the control information.
The data bit width conversion device according to claim 13, wherein

The control information includes: routing information, where the routing information is used to indicate a first mode and a second mode of data bit width conversion, and in the first mode, the parallel data bit width is prioritized, the cross clock is After the domain operation is performed, in the second mode, the cross-clock domain operation is preceded, and the parallel data bit width is converted later;

The data bit width conversion circuit is configured to perform data bit width conversion, cross clock domain operation, and cross clock anti-shake processing by using the mode indicated by the routing information.
The data bit width conversion device according to claim 13, wherein

The data bit width conversion circuit includes: a data bit width conversion buffer module, a cross clock domain storage module, and a cross clock anti-jitter module;

The data bit width conversion buffer module is configured to complete parallel data bit width conversion;

The cross-clock domain storage module is configured to perform cross-clock domain operations;

The cross-clock anti-jitter module is configured to complete cross-clock anti-shake processing;

The data bit width conversion buffer module and the cross-clock domain storage module communicate with each other, and the cross-clock domain storage module and the cross-clock anti-shake module communicate with each other.
A computer readable storage medium having stored thereon a computer program, the computer program being executed by a processor to perform the following operations:

Based on the parallel data conversion information, control information for data bit width conversion is generated such that the data bit width conversion circuit performs parallel data bit width conversion, cross clock domain operation, and cross clock anti-shake processing based on the control information.
The computer readable storage medium of claim 21 wherein:

The parallel data conversion information includes: a first parallel data bit width and a first clock frequency before conversion, and a converted second parallel data bit width and a second clock frequency.
The computer readable storage medium according to claim 21, wherein

The computer program is executed by the processor to perform the following operations:

Determining whether the data transmission rates before and after the conversion are consistent according to the parallel data conversion information; and generating control information for data bit width conversion according to the parallel data conversion information when the data transmission rates before and after the conversion are consistent.
A computer readable storage medium according to claim 21, wherein said computer program, when executed by the processor, performs the following operations:

Determining whether the product of the first parallel data bit width before conversion and its corresponding first clock frequency, and the product of the converted second parallel data bit width and the corresponding second clock frequency are the same, and according to the parallel data conversion information Generate control information for data bit width conversion.
A computer readable storage medium according to claim 21, wherein said computer program, when executed by a processor, performs the following operations:

Generating the control information according to the parallel data conversion information and based on w i *N i =w o *N o =LCM;

Where LCM is the least common multiple of w i and w o , w i represents the first parallel data bit width before conversion, w o represents the converted second parallel data bit width, and N i represents the data written at the first clock frequency. number of cycles, N o represents the number of read data at a second frequency clock cycle.
A computer readable storage medium according to claim 21, wherein said computer program, when executed by a processor, performs the following operations:

Generating control information including routing information indicating the first mode when the first parallel data bit width before the conversion is less than the converted second parallel data bit width;

Generating control information including routing information indicating the second mode when the first parallel data bit width before the conversion is greater than the converted second parallel data bit width;

Wherein, in the first mode, the parallel data bit width conversion is prior to the cross-clock domain operation; in the second mode, the cross-clock domain operation is prior to the parallel data bit width The conversion is after.
The computer readable storage medium according to any one of claims 21 to 26, wherein the control information comprises one or more of the following:

The routing information is used to indicate a mode used by the data bit width conversion, where the mode is a first mode or a second mode, and in the first mode, the parallel data bit width conversion is prior to the cross clock domain operation After the second mode, the cross-clock domain operation is prior to the parallel data bit width conversion;

The buffer configuration information used for the parallel data bit width conversion includes: capacity information of the buffer unit, and read and write configuration information;

Storage configuration information for the operation of the cross-clock domain, including: capacity information of the storage unit, and read and write configuration information;

The anti-jitter configuration information used for the cross-clock anti-shake processing includes: period information of anti-shake monitoring and a read/write recovery address.