CN111309653B - Data bus and method for reading data and writing data - Google Patents
Data bus and method for reading data and writing data Download PDFInfo
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- CN111309653B CN111309653B CN201811519993.8A CN201811519993A CN111309653B CN 111309653 B CN111309653 B CN 111309653B CN 201811519993 A CN201811519993 A CN 201811519993A CN 111309653 B CN111309653 B CN 111309653B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
Abstract
The invention relates to the field of nonvolatile memories, in particular to a data bus and a method for reading and writing data, wherein the data bus comprises a first data bus and a second data bus, the first data bus and the second data bus are arranged side by side, the two adjacent ends of the first data bus and the second data bus are respectively led out to a data processor, the physical quantity of the data bus is equal to that of the first data bus, the physical quantity of the data bus is equal to that of the second data bus, the data bus is led out to the data processor, the physical quantity of the data bus is equal to that of the first data bus, and the physical quantity of the data bus is equal to that of the second data bus, the data bus is led out to a data selector. The data bus and the data reading and writing method provided by the invention change the arrangement mode of the data bus, so that the occupied space of the data bus is reduced, and the space utilization rate of the nonvolatile memory is improved.
Description
Technical Field
The present invention relates to the field of non-volatile memories, and more particularly to a data bus and methods for reading and writing data.
Background
Data of the existing nonvolatile memory is transmitted through a data bus, the data throughput of a data bus signal is large logically, and the data bus occupies a large area physically.
The data buses in the nonvolatile memory are metal lines arranged from bottom to top in sequence, and the physical number of the metal lines is equal to the bit width of the nonvolatile memory, namely the physical number of the data buses of the 8-bit nonvolatile memory is 8, the physical number of the data buses of the 16-bit nonvolatile memory is 16, and the physical number of the data buses of the 32-bit nonvolatile memory is 32.
Fig. 1 shows a schematic diagram of a data bus in a nonvolatile memory in the prior art, when data is read, a bus controller 5 firstly performs arbitration, and determines that a data selector 3 uses a data bus 2, the data selector 3 reads data to be read out from a storage unit 4 and transmits the data to the data bus 2, the data bus 2 transmits the data to be read to a data processor 1, when data is written, the bus controller 5 firstly performs arbitration, determines that the data processor 1 uses the data bus 2, a data controller 6 transmits the data to be transmitted in the data processor 2 to the data bus 2, the data bus 2 transmits the data to be transmitted to the data selector 3, and the data selector 3 transmits the data to the storage unit 4 to complete data transmission.
The larger the physical number of data buses in the nonvolatile memory is, the larger the occupied area is, which greatly affects the miniaturization of the nonvolatile memory.
Disclosure of Invention
In view of the above problems, the present invention provides a data bus and a method for reading and writing data, which solve the problems of the prior art that the number of data buses is large physically and the occupied area is large.
The embodiment of the invention provides a data bus, which comprises metal wires which are arranged in a nonvolatile memory from bottom to top in sequence and used for data transmission, wherein the data bus is applied to the nonvolatile memory, and the nonvolatile memory comprises: a data processor and a data selector;
the data buses comprise a first data bus and a second data bus, the first data bus is half of the physical quantity of the data buses selected in sequence, and the second data bus is the other half of the physical quantity of the data buses selected in sequence;
arranging the first data bus and the second data bus side by side to ensure that the two parts of data buses are symmetrically arranged;
respectively leading out data buses with the same physical quantity as the first data buses and the same physical quantity as the second data buses to the data processor from two adjacent ends of the first data buses and the second data buses;
and respectively leading out data buses with the same physical quantity as the first data buses and the second data buses to the data selector.
Optionally, the width of the data bus in logic is consistent with the bit width of the nonvolatile memory;
the physical number of the data bus is consistent with the bit width size of the nonvolatile memory.
Optionally, the non-volatile memory further comprises: the memory cell, when the nonvolatile memory carries on the read operation, the flow direction of the data that need to be transmitted is: from the memory unit to the data selector, from the data selector to the data bus, from the data bus to the data processor.
Optionally, when the nonvolatile memory performs a write operation, a flow direction of data to be transferred is: from the data processor to the data bus, from the data bus to the data selector, from the data selector to the memory location.
The embodiment of the present invention further provides a method for reading data, where the method for reading data is applied to the data bus, and the nonvolatile memory further includes: the bus controller, when the nonvolatile memory performs a read operation, the method for reading data includes:
the bus controller carries out arbitration and determines that the data selector uses the data bus;
the data selector selects the data to be transmitted from the storage unit;
the data selector divides the data to be transmitted into a first part of data and a second part of data, wherein the first part of data is low-order data in the data to be transmitted, and the second part of data is high-order data in the data to be transmitted;
the data selector sends the first part of data to the first data bus and sends the second part of data to the second data bus;
and the first data bus and the second data bus transmit data to be transmitted to the data processor.
Optionally, after the data selector selects the data to be transmitted from the storage unit, the method further includes:
the data selector sends the first part of data to the second data bus and sends the second part of data to the first data bus.
The embodiment of the present invention further provides a method for writing data, where the method for writing data is applied to the data bus, and the nonvolatile memory further includes: the data controller, when the nonvolatile memory performs a write operation, the method of write transfer includes:
the bus controller carries out arbitration and determines that the data processor uses the data bus;
dividing data to be transmitted in the data processor into a third part of data and a fourth part of data by the data controller, wherein the third part of data is low-order data of the data to be transmitted in the data processor, and the fourth part of data is high-order data of the data to be transmitted in the data processor;
the data controller sends the third part of data to the first data bus and sends the fourth part of data to the second data bus;
the first data bus and the second data bus transmit data required to be transmitted in the data processor to the data selector;
and the data selector transmits the data required to be transmitted in the data processor to the storage unit.
Optionally, after the data controller divides the data to be transmitted into a third part of data and a fourth part of data in the data processor, the method further includes:
and the data controller sends the third part of data to the second data bus and sends the fourth part of data to the first data bus.
Compared with the prior art, the data bus provided by the invention has the advantages that the physical length of the data bus is reduced by half, the occupied height of the data bus in the physical space is reduced by half, the physical quantity of the data bus is not reduced, the data transmission efficiency is ensured, the utilization rate of the physical space in the nonvolatile memory is improved, and the miniaturization of the nonvolatile memory is facilitated.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of a data bus within a prior art non-volatile memory;
FIG. 2 is a schematic diagram of a data bus of the present invention;
FIG. 3 is a flow chart of a data reading method of the present invention;
fig. 4 is a flow chart of a data writing method of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Referring to fig. 2, a schematic diagram of a data bus for data transmission in a nonvolatile memory is shown, in contrast to the physical form of the data bus of the nonvolatile memory of fig. 1, the nonvolatile memory of the present invention includes: the data bus 10 proposed by the present invention is divided into two parts with equal physical quantity, which are respectively a first data bus 101 and a second data bus 102, if the bit width of the used nonvolatile memory is 8 bits, the physical quantity of the data bus 10 is 8, the physical quantity of the first data bus 101 is 4, the physical quantity of the second data bus 102 is 4, the two parts are placed side by side on the physical space, so that the first data bus 101 and the second data bus 102 are symmetrically placed side by side, so that the height occupied by the data bus 10 on the physical space is only half of that of the 8 data buses in the arrangement mode, but the physical quantity is consistent with the bit width of the nonvolatile memory, and the respective data buses are respectively led out to the data processor from the parts adjacent to the first data bus 101 and the second data bus 102 20, it is necessary to respectively lead out data buses to the data selector 30 on the first data bus 101 and the second data bus 102.
When the nonvolatile memory is read, the flow of the data to be transmitted is as follows: from the memory unit 40 to the data selector 30, from the data selector 30 to the data bus 10, and from the data bus 10 to the data processor 20, when the nonvolatile memory performs a write operation, the flow of the data to be transferred is: from the data processor 20 to the data bus 10, from the data bus 10 to the data selector 30, from the data selector 30 to the memory unit 40.
Therefore, the height occupied by the data bus 10 in the physical space is reduced while the normal transmission of the data of the nonvolatile memory is ensured, the space of the nonvolatile memory is saved, and the further miniaturization of the nonvolatile memory is facilitated.
Alternatively, referring to fig. 3, a method for reading data is shown, after the physical form of the data bus 10 is changed, the method for performing data transmission by the nonvolatile memory is also changed, and when a read operation is performed, the method for performing data transmission comprises the following steps:
step 101: the bus controller arbitrates to determine whether the data bus is used by the data selector.
In the embodiment of the present invention, because the nonvolatile memory has only one data bus 10 for data transmission, when data needs to be transmitted, it is necessary to determine who occupies the data bus 10, otherwise, data is simultaneously placed on the data bus 10, which may cause a transmission error of the data, so the bus controller 50 is used to determine which part occupies the data bus 10 for data transmission, so that data transmission is performed in order, and no error occurs, for example, a read operation needs to be performed, and the bus controller 50 firstly performs arbitration to determine that the data selector 30 occupies the data bus 10. The embodiment of the present invention does not specifically limit the selection manner of occupying the data bus.
Step 102: the data selector selects the data to be transmitted from the storage unit.
In the embodiment of the present invention, the data to be read all have unique addresses to correspond to the addresses in the storage unit 40, and after the data selector 30 receives the addresses, the data selector 30 reads the data corresponding to the addresses in the storage unit 40 according to the addresses of the data to be read, because the nonvolatile memory has a bit width of 8 bits, and the data read by the data selector 30 at a time is also 8 bits of data according to the characteristics of the nonvolatile memory. The embodiment of the present invention does not specifically limit the specific manner of reading data.
Step 103: and the data selector divides the data to be transmitted into a first part of data and a second part of data, wherein the first part of data is lower data in the data to be transmitted, and the second part of data is higher data in the data to be transmitted.
In the embodiment of the present invention, data in the nonvolatile memory is transmitted in an 8-bit format, and is divided into low-bit data and high-bit data according to characteristics of the data, and the data selector 30 divides the read 8-bit data into 4 bits of low-bit data and 4 bits of high-bit data. The embodiment of the present invention does not specifically limit the specific manner of dividing the high and low bits of the data.
Step 104: the data selector sends the first part of data to the first data bus and the second part of data to the second data bus.
In the embodiment of the present invention, the data selector 30 divides 4 bits of the low-order data and 4 bits of the high-order data, and then transmits the two bits to the data bus 10, where 4 bits of the low-order data may be transmitted to the first data bus 101, at this time, 4 bits of the high-order data are transmitted to the second data bus 102, and similarly, 4 bits of the low-order data may also be transmitted to the second data bus 102, and then 4 bits of the high-order data are transmitted to the first data bus 101. The embodiment of the present invention does not specifically limit the specific manner of transmitting high and low bits of data.
Step 105: the first data bus and the second data bus transmit the data to be transmitted to the data processor.
In the embodiment of the present invention, after receiving the data to be transmitted on the data bus 10, the data processor 20 transmits the low-order data 4 and the high-order data 4 at the same time. The embodiment of the present invention does not specifically limit the specific data transmission method.
For example, as shown in fig. 2, in the design scheme of this embodiment, when there is data to be read, the bus controller 50 firstly performs arbitration to determine that the data selector 30 occupies the data bus 10, the data to be read all have unique addresses to correspond to addresses in the storage unit 40, after the data selector 30 receives the addresses, the data selector 30 reads out the data corresponding to the addresses in the storage unit 40 according to the addresses of the data to be read, for example, the read-out data is 01000010, the data selector 30 divides the read-out 8-bit data into high and low bits 4 bit 0010 and high bit 4 bit 0100, and then the data selector 30 divides the low bit 4 bit 0010 and the high bit 4 bit 0100 and transmits the two bits to the data bus 10, where 0010 can be transmitted to the first data bus 101, and at this time 0100 is transmitted to the second data bus 102, 0010 can also be transmitted to the second data bus 102, 0100 is transmitted to the first data bus 101, after the data 01000010 to be transmitted is received on the data bus 10, the lower data 0010 and the upper data 0100 are simultaneously transmitted to the data processor 20, and the data processor 20 receives the complete data 01000010, so that the data is read at this time, and the reading operation is finished.
Alternatively, referring to fig. 4, a method for writing data is shown, after the physical form of the data bus 10 is changed, a method for performing data transmission by the nonvolatile memory is also changed, and when a write operation is performed, the method for performing data transmission includes the following steps:
step 201: the bus controller arbitrates to determine the data processor to use the data bus.
In the embodiment of the present invention, when a write operation is required, the bus controller 50 first performs arbitration to determine that the data processor 20 occupies the data bus 10. The embodiment of the present invention does not specifically limit the selection manner of occupying the data bus.
Step 202: the data controller divides the data to be transmitted in the data processor into a third part of data and a fourth part of data, wherein the third part of data is lower data of the data to be transmitted in the data processor, and the fourth part of data is upper data of the data to be transmitted in the data processor.
In the embodiment of the present invention, data needs to be transferred from the data processor 20 to the storage unit when data is written, since the nonvolatile memory has a bit width of 8 bits, the number of bits of data transferred at one time by the data processor 20 is also 8 bits according to the characteristics of the nonvolatile memory, and the data controller 60 divides the data in the data processor 20 into 4 bits of low data and 4 bits of high data according to the high and low bits of the data to be written. The embodiment of the present invention does not specifically limit the specific manner of dividing the high and low bits of the data.
Step 203: and the data controller is used for sending the third part of data to the first data bus and sending the fourth part of data to the second data bus.
In the embodiment of the present invention, the data controller 60 transmits 4 bits of low data and 4 bits of high data to the data bus 10, wherein 4 bits of the low data can be transmitted to the first data bus 101, at this time, 4 bits of the high data are transmitted to the second data bus 102, and similarly, 4 bits of the low data can be transmitted to the second data bus 102, and 4 bits of the high data are transmitted to the first data bus 101. The embodiment of the present invention does not specifically limit the specific manner of transmitting high and low bits of data.
Step 204: and the first data bus and the second data bus transmit the data required to be transmitted in the data processor to the data selector.
In the embodiment of the present invention, after receiving the data to be transmitted on the first data bus 101 and the second data bus 102, the data selector 30 transmits the 4 bits of the lower data and the 4 bits of the upper data simultaneously. The embodiment of the present invention does not specifically limit the data transmission method.
Step 205: the data selector transmits the data required to be transmitted in the data processor to the storage unit.
In the embodiment of the present invention, after receiving the data to be written, the data selector 30 addresses in the storage unit 40 according to the address of the data to be written, and writes the data into the corresponding storage unit. The embodiment of the present invention does not specifically limit the specific addressing and data writing modes.
For example, as shown in fig. 2, in the design scheme of this embodiment, when data needs to be written, the bus controller 50 first performs arbitration to determine that the data processor 20 occupies the data bus 10, for example, 10000001 is data to be written, the data controller 60 divides the 8-bit data that needs to be written in the data processor 20 into high and low bits, divides the 8-bit data into 4 low bits 0001 and 4 high bits 1000, divides the low bits 4 bits 0001 and the high bits 1000 into them, and transmits them to the data bus 10, wherein 0001 may be transmitted to the first data bus 101, and 1000 may be transmitted to the second data bus 102, and likewise, 0001 may be transmitted to the second data bus 102, and 1000 may be transmitted to the first data bus 101, and after receiving 10000001 data to be transmitted on the data bus 10, simultaneously transmit the low bits 0001 and the high bits 1000 to the data selector 30, the data selector 30 receives the complete data 10000001, and addresses in the memory cell 40 according to the address of the memory cell to which the data needs to be written, writes 10000001 in the corresponding memory cell, and the writing operation is ended until the data is written.
It should be noted that the above data are only simple data for better explaining the embodiments of the present invention, and do not represent data when all the nonvolatile memories perform data transmission. The embodiment of the present invention does not specifically limit the specific manner of data bus transmission, the data selection for executing different operations, and the low order division.
Through the embodiment, the occupied space area of the data bus of the nonvolatile memory is reduced in the physical space, and meanwhile, the normal data transmission of the nonvolatile memory is guaranteed, so that the nonvolatile memory is more convenient to miniaturize, and the space utilization rate of the nonvolatile memory is improved.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The data bus and the method for reading and writing data provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above examples is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. A data bus comprising metal lines for data transmission arranged in a nonvolatile memory in sequence from bottom to top, wherein the data bus is applied to the nonvolatile memory, and the nonvolatile memory comprises: a data processor and a data selector;
the data buses comprise a first data bus and a second data bus, the first data bus is half of the physical quantity of the data buses selected in sequence, and the second data bus is the other half of the physical quantity of the data buses selected in sequence;
arranging the first data bus and the second data bus side by side to ensure that the two parts of data buses are symmetrically arranged;
respectively leading out data buses with the same physical quantity as the first data buses and the same physical quantity as the second data buses to the data processor from two adjacent ends of the first data buses and the second data buses;
and respectively leading out data buses with the same physical quantity as the first data buses and the second data buses to the data selector.
2. The data bus of claim 1, wherein the data bus has a logical width that is consistent with a bit width of the non-volatile memory;
the physical number of the data bus is consistent with the bit width size of the nonvolatile memory.
3. The data bus of claim 1, wherein the non-volatile memory further comprises: the memory cell, when the nonvolatile memory carries on the read operation, the flow direction of the data that need to be transmitted is: from the memory unit to the data selector, from the data selector to the data bus, from the data bus to the data processor.
4. The data bus of claim 1, wherein when the nonvolatile memory performs a write operation, the flow of the data to be transferred is as follows: from the data processor to the data bus, from the data bus to the data selector, from the data selector to a memory location.
5. A method for reading data, applied to the data bus of any one of claims 1-4, wherein the nonvolatile memory further comprises: the bus controller, when the nonvolatile memory performs a read operation, the method for reading data includes:
the bus controller carries out arbitration and determines that the data selector uses the data bus;
the data selector selects data to be transmitted from the storage unit;
the data selector divides the data to be transmitted into a first part of data and a second part of data, wherein the first part of data is low-order data in the data to be transmitted, and the second part of data is high-order data in the data to be transmitted;
the data selector sends the first part of data to the first data bus and sends the second part of data to the second data bus;
and the first data bus and the second data bus transmit data to be transmitted to the data processor.
6. The method of claim 5, wherein after the data selector selects the desired transmission data from the storage unit, the method further comprises:
the data selector sends the first part of data to the second data bus and sends the second part of data to the first data bus.
7. A method for writing data, applied to the data bus of any one of claims 1-4, wherein the nonvolatile memory further comprises: the data controller, when the nonvolatile memory performs a write operation, the method for writing data includes:
the bus controller carries out arbitration and determines that the data processor uses the data bus;
dividing data to be transmitted in the data processor into a third part of data and a fourth part of data by the data controller, wherein the third part of data is low-order data of the data to be transmitted in the data processor, and the fourth part of data is high-order data of the data to be transmitted in the data processor;
the data controller sends the third part of data to the first data bus and sends the fourth part of data to the second data bus;
the first data bus and the second data bus transmit data required to be transmitted in the data processor to the data selector;
and the data selector transmits the data required to be transmitted in the data processor to a storage unit.
8. The method of claim 7, wherein after the data controller divides the data to be transmitted into a third portion of data and a fourth portion of data in the data processor, the method further comprises:
and the data controller sends the third part of data to the second data bus and sends the fourth part of data to the first data bus.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102289421A (en) * | 2011-07-26 | 2011-12-21 | 西安电子科技大学 | On-chip interconnection method based on crossbar switch structure |
| CN102981801A (en) * | 2012-11-07 | 2013-03-20 | 迈普通信技术股份有限公司 | Conversion method and device of local bus data bit wide |
| CN103412848A (en) * | 2013-05-11 | 2013-11-27 | 中国科学技术大学 | Method for sharing single program memory by four-core processor system |
| CN103810130A (en) * | 2012-11-13 | 2014-05-21 | 亚旭电脑股份有限公司 | Data transmission selection circuit and data transmission selection method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8341303B2 (en) * | 2008-06-30 | 2012-12-25 | Intel Corporation | Asymmetrical universal serial bus communications |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102289421A (en) * | 2011-07-26 | 2011-12-21 | 西安电子科技大学 | On-chip interconnection method based on crossbar switch structure |
| CN102981801A (en) * | 2012-11-07 | 2013-03-20 | 迈普通信技术股份有限公司 | Conversion method and device of local bus data bit wide |
| CN103810130A (en) * | 2012-11-13 | 2014-05-21 | 亚旭电脑股份有限公司 | Data transmission selection circuit and data transmission selection method |
| CN103412848A (en) * | 2013-05-11 | 2013-11-27 | 中国科学技术大学 | Method for sharing single program memory by four-core processor system |
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