JP2007241619A - Memory controller, nonvolatile storage device, nonvolatile storage system and data write method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller capable of optimizing a write speed and peak current suppression corresponding to the kind of a flash memory to be mounted, a nonvolatile storage device and a nonvolatile storage system. <P>SOLUTION: A logical/physical conversion mode determination means 125 determines the logical/physical conversion mode of a logical/physical conversion means 126 according to the kind of mounted nonvolatile memories 130 and 140. Thus, whether to parallelly write data to the nonvolatile memories 130 and 140 or to serially write them to one of the nonvolatile memories is selected. Write is simultaneously performed to the nonvolatile memories 130 and 140 when the nonvolatile memories 130 and 140 are of a low speed type and write is serially performed to one of the nonvolatile memories when they are of a high speed type. Thus, a peak current is suppressed while maintaining a target write speed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device such as a semiconductor memory card having a nonvolatile memory, a memory controller built in the nonvolatile memory device, a nonvolatile memory system in which an access device is added to the nonvolatile memory device as a component, and The present invention relates to a data writing method.

  The demand for a nonvolatile memory device including a rewritable nonvolatile main memory is increasing mainly for semiconductor memory cards. This nonvolatile storage device includes a flash memory as a nonvolatile memory and has a memory controller for controlling the flash memory. The memory controller controls reading and writing of file data such as images to and from the flash memory in accordance with a read / write instruction and a logical address designation from an access device such as a digital still camera or a personal computer main body.

  When writing one file data from the access device to the flash memory, it is usually written once by a write instruction in some cases, and in some cases, written in the order of successive logical addresses.

  There are various types of flash memory. The performance varies depending on the type of memory cell such as a binary NAND flash memory, a multi-level NAND flash memory, and an AND flash memory, a difference in capacity, or a difference in manufacturer. For example, with regard to writing, a binary NAND flash memory has a faster writing time than a multi-level NAND flash memory. Note that the write time is a time required for writing (programming) data received from the memory controller into a memory cell of the flash memory.

In recent years, applications for writing a large-capacity file such as a moving image in real time, that is, at high speed, to a nonvolatile storage device are increasing. For this reason, various devices have been devised, such as incorporating flash memory of a plurality of chips, connecting the flash memory and a memory controller with a plurality of memory buses, and performing writing in parallel (for example, see Patent Document 1). However, when writing is performed in parallel on a plurality of flash memories, the writing speed is improved, but the peak current is also increased.
JP-A-6-119128

  However, in the conventional nonvolatile memory device described above, regardless of the type of flash memory, normal writing, that is, writing to consecutive logical addresses, is always performed in parallel in a plurality of flash memories. For this reason, in a nonvolatile memory device equipped with a flash memory having a very fast writing time, a writing speed far exceeding the target writing speed as the nonvolatile memory device is obtained, resulting in overspec. In the case of parallel writing, since the peak current is larger than that in normal writing, it is impossible to achieve both the writing speed and the suppression of the peak current. In other words, both the writing speed and the suppression of the peak current cannot be optimized. Here, the optimization means that the minimum peak current is sufficient under the condition if the writing speed is equal to or higher than the target value.

  For normal non-volatile storage devices, it is sufficient that a writing speed capable of recording moving image data in real time is sufficient, and depending on the type of flash memory used, the necessary writing speed may be realized without parallel writing. . In that case, it is possible to suppress the peak current while ensuring the target speed by writing only one flash memory without writing in parallel to the plurality of flash memories.

  Therefore, in view of the above problems, the present invention provides a memory controller, a nonvolatile memory device, a nonvolatile memory system capable of optimizing both the writing speed and the suppression of the peak current corresponding to the type of the flash memory to be mounted. An object is to provide a data writing method.

  In order to solve this problem, a memory controller of the present invention is a memory controller that is connected to a plurality of nonvolatile memories, writes data according to a logical address designated from the outside, and reads data from the nonvolatile memory, The number of non-volatile memories determined by the simultaneous write memory number determining means for determining the number of memories to simultaneously write data to the plurality of non-volatile memories according to the type of the non-volatile memory, and the number of non-volatile memories determined by the simultaneous write memory number determining means And a read / write control unit that simultaneously writes data and reads data from the nonvolatile memory.

  Here, the simultaneous write memory number determination means reduces the number of memories to be written simultaneously when the write performance of the nonvolatile memory is a high speed type, and simultaneously writes when the write performance of the nonvolatile memory is a low speed type. The number may be increased.

  Here, the simultaneous writing memory number determining means determines the number of memories to be simultaneously written according to the type of the nonvolatile memory, and determines the logical-physical conversion mode determining means corresponding to the number of memories, According to the logical-physical conversion mode determined by the logical-physical conversion mode determining means, logical-physical conversion means for associating the logical address with the physical address of the nonvolatile memory may be provided.

  Here, the non-volatile memory holds an ID code for identifying the type thereof, and the simultaneous write memory number determining means determines the data according to the write speed of data recognized by the ID code of the non-volatile memory. The logical / physical conversion mode of the logical / physical conversion means may be determined.

  Here, the nonvolatile memory holds a mode table that associates an ID code for identifying the nonvolatile memory with a logical-physical conversion mode, and the logical-physical conversion mode determination means refers to the mode table. The logical-physical conversion mode may be determined by

  Here, the memory controller may be composed of a plurality of controller chips, and the controller chip and one or more nonvolatile memories may be connected by a single bus.

  In order to solve this problem, a non-volatile memory device of the present invention includes a plurality of non-volatile memories and a memory that writes data to the non-volatile memory according to a logical address designated from the outside and reads data from the non-volatile memory A non-volatile storage device comprising a controller, wherein the memory controller determines the number of memories that simultaneously write data to the plurality of non-volatile memories according to the type of the non-volatile memory; And a read / write control unit for simultaneously writing data to the number of nonvolatile memories determined by the simultaneous writing memory number determining means and reading the data of the nonvolatile memory.

  Here, the simultaneous write memory number determination means reduces the number of memories to be written simultaneously when the write performance of the nonvolatile memory is a high speed type, and simultaneously writes when the write performance of the nonvolatile memory is a low speed type. The number may be increased.

  Here, the simultaneous writing memory number determining means determines the number of memories to be simultaneously written according to the type of the nonvolatile memory, and determines the logical-physical conversion mode determining means corresponding to the number of memories, According to the logical-physical conversion mode determined by the logical-physical conversion mode determining means, logical-physical conversion means for associating the logical address with the physical address of the nonvolatile memory may be provided.

  Here, the non-volatile memory holds an ID code for identifying the type thereof, and the simultaneous write memory number determining means determines the data according to the write speed of data recognized by the ID code of the non-volatile memory. The logical / physical conversion mode of the logical / physical conversion means may be determined.

  Here, the nonvolatile memory holds a mode table that associates an ID code for identifying the nonvolatile memory with a logical-physical conversion mode, and the logical-physical conversion mode determination means refers to the mode table. The logical-physical conversion mode may be determined by

  Here, the memory controller may be composed of two or more controller chips, and each of the controller chips and one or more nonvolatile memories may be connected by a single bus.

  In order to solve this problem, a nonvolatile memory system according to the present invention includes the nonvolatile memory device described above, and an access device that writes data to the nonvolatile memory device and reads data from the nonvolatile memory device. It is characterized by this.

  In order to solve this problem, a data writing method of the present invention is a data writing method that is connected to a plurality of nonvolatile memories, writes data according to a logical address designated from the outside, and reads data from the nonvolatile memory. Thus, the number of memories in which data is simultaneously written in the plurality of nonvolatile memories is determined according to the type of the nonvolatile memory, and the data is simultaneously written in the determined number of nonvolatile memories.

  Here, the determination of the number of simultaneous write memories is performed by reducing the number of memories to be written simultaneously when the write performance of the nonvolatile memory is a high-speed type, and reducing the number of memories when the write performance of the nonvolatile memory is a low-speed type. You may make it enlarge.

  Here, the determination of the number of simultaneous write memories determines the number of memories to be simultaneously written according to the type of the nonvolatile memory, determines a logical-physical conversion mode corresponding to the number of memories, and determines the determined logical-physical conversion mode. Accordingly, the logical address may be associated with the physical address of the nonvolatile memory.

  Here, the non-volatile memory holds an ID code for identifying the type, and the determination of the number of simultaneous write memories depends on the write speed of data recognized by the ID code of the non-volatile memory. The logical / physical conversion mode of the logical / physical conversion means may be determined.

  Here, the non-volatile memory holds a mode table that associates an ID code for identifying the non-volatile memory with a logical-physical conversion mode, and the logical-physical conversion mode is determined by referring to the mode table. The logical-physical conversion mode may be determined by

  According to the present invention, the logical / physical conversion mode determination means determines the logical / physical conversion mode of the logical / physical conversion means according to the type of the mounted nonvolatile memory, thereby providing data to the plurality of nonvolatile memories. Can be selected in parallel or in a single nonvolatile memory in series. Specifically, when the non-volatile memory is a low speed type, the number of non-volatile memories that are simultaneously written is increased, and when the non-volatile memory is a high speed type, the number of non-volatile memories that are simultaneously written is reduced. The peak current can be suppressed while maintaining.

(First embodiment)
The nonvolatile memory system according to the first embodiment of the present invention will be described below. FIG. 1 is a block diagram showing a nonvolatile memory system according to the first embodiment. In FIG. 1, the nonvolatile storage system includes an access device 100 and a nonvolatile storage device 110. The nonvolatile storage device 110 includes a memory controller 120 and nonvolatile memories 130 and 140. The memory controller 120 includes a host interface 121, a buffer 122, a read / write control unit 123, a CPU unit 124, a logical / physical conversion mode determination unit 125, and a logical / physical conversion unit 126. A block in which the logical / physical conversion mode determination unit 125 and the logical / physical conversion unit 126 are combined is referred to as a simultaneous write memory number determination unit 127.

  The host interface 121 receives a logical address and data to be written from the access device 100 when writing data, holds the data in the buffer 122, and gives the logical address to the CPU unit and logical-physical conversion unit.

  The buffer 122 temporarily stores data when data is written to or read from the nonvolatile memory 130 or 140 from the access device 100, and the page size (for example, 2 kbytes) that is a writing unit of the nonvolatile memory 130 or 140. ) Larger size buffer.

  The read / write control unit 123 is a block for writing data temporarily stored in the buffer 122 to the non-volatile memories 130 and 140 and reading data stored in the non-volatile memory 110 to the buffer 122. At that time, the physical addresses of the nonvolatile memories 130 and 140 are received from the CPU unit 124.

  The CPU unit 124 controls the entire memory controller 120 or generates a physical address of the nonvolatile memory 130 or 140 based on the conversion process of the logical-physical conversion unit 126 based on the logical address received from the access device 100. is there. Note that the host interface 121, the buffer 122, the read / write control unit 123, and the CPU unit 124 can be realized using generally known techniques, and thus detailed description thereof is omitted.

  The logical-physical conversion mode determination unit 125 determines a mode by referring to a mode table described later based on the ID code read from the nonvolatile memory 130 or 140. Here, there are two logical-physical conversion modes, mode A and mode B.

  The logical / physical conversion unit 126 is a block that converts the logical address specified by the access device 100 into a physical address in accordance with the mode specified by the logical / physical conversion mode determination unit 125. Mode A is a serial write mode used for a high-speed flash memory, and the number of memories to be simultaneously written is one. On the other hand, mode B is a parallel writing mode used for a low-speed nonvolatile memory, and the number of memories to be simultaneously written is 2 here. The bits to be converted in the target logical address are changed depending on these modes as described later.

  In this embodiment, a plurality of, here two, nonvolatile memories 130 and 140 are provided. These nonvolatile memories 130 and 140 are the same type of flash memory, and have the same ID code. Hereinafter, it is assumed that the memory is 0 and the memory 1, respectively. The size of each flash memory is, for example, 1 Gbyte.

  FIG. 2 is a memory map of physical blocks. Each physical block is composed of a plurality of pages which are write units. Here, each physical block is composed of 128 pages with page numbers PN0 to PN127. Each page can store data for four sectors. The size of one page is 2 kbytes, and the size of one physical block is 256 kbytes.

  FIG. 3 is an explanatory diagram illustrating a mode table referred to by the logical-physical conversion mode determination unit 125. A non-volatile memory or ROM may be provided in the logical-physical conversion mode determination unit 121, and the mode table may be held here, or the mode table may be held in the non-volatile memory 130 or 140, and this may be stored at initialization. The mode table may be read into the RAM of the logical-physical conversion mode determination unit 125. As shown in FIG. 3, an ID code is recorded in the mode table for each flash memory manufacturer, the type of binary NAND flash memory or multi-level NAND flash memory, and the capacity. Information indicating the physical conversion mode, that is, which logical-physical conversion mode is used is stored. In general, the binary NAND flash memory is faster than the multi-level NAND flash memory. Even with the same type of flash memory, the speed varies slightly depending on the flash memory manufacturer, product type, and capacity. Therefore, as shown in FIG. 3, either mode A or mode B is set according to the type of flash memory. When there are a larger number of flash memories, a conversion mode for simultaneously writing to four flash memories, such as mode C, can be provided.

Next, the operation of the present embodiment, particularly the operation of the nonvolatile memory device 110 when a write command is issued from the access device 100 will be described.
[Initialization at power-on]
First, after the access device 100 supplies power to the nonvolatile storage device 110, the memory controller 120 reads an ID code from one of the nonvolatile memories, for example 130, via the read / write control unit 123.

The CPU unit 124 transfers the read ID code to the logical-physical conversion mode determination unit 125, and the logical-physical conversion mode determination unit 125 performs the logical-physical conversion mode based on the mode table (FIG. 3) stored in the internal ROM. Decide. In the present embodiment, both the non-volatile memories 130 and 140 are the A company binary flash memory (1 Gbyte product) and the ID code is “0”, and the A company multilevel flash memory (1 Gbyte). And the ID code is “1”. The former is mode A and the latter is mode B. The mode information is transferred to the logical / physical conversion unit 126, and the logical / physical conversion mode in the logical / physical conversion unit 126 is determined to be either mode A or B, and the state transitions to the access waiting state (normal operation) from the access device 100 To do.
[Processing during normal operation]
First, a case where mode A is set in the initialization process when the power is turned on will be described. For example, when a binary flash memory (1 Gbyte product) manufactured by company A is used, mode A is set.

  FIG. 4 is a diagram showing a logical address space and a physical address space in the case of mode A. For the sake of simplicity, the management information area such as FAT is omitted, and the entire logical address space is considered as an area (normal area) in which data is written. In this figure, among the logical addresses 0 to 2 GB (logical block addresses LBA0 to 8191), the first half LBA0 to 4095 are allocated to the nonvolatile memory having the memory number 0, that is, the nonvolatile memory 130, and the second half LBAs 4096 to 8191 are memory. It is assigned to the non-volatile memory number 1, that is, the non-volatile memory 140. The nonvolatile memory side has physical block addresses (PBA) 0 to 4095 for each of 130 and 140, and is distinguished by the memory number. The physical block address and the logical block address are converted by wear leveling.

  Assume that the access device 100 has transferred a 1 Mbyte data write command to logical addresses continuous from logical address 0. The host interface 121 receives a write command, a logical address, and data, and temporarily stores the data in the buffer 122. On the other hand, the logical address is transferred to the logical-physical conversion unit 126, and the logical-physical conversion unit 126 performs logical-physical conversion processing based on FIG.

  In the logical-physical conversion process, b20 and b8 to b0 of the logical address format are copied as they are to the corresponding bits of the physical address format, but b19 to b9 (logical block address) of the logical address format are directly b19 to b of the physical address format. The wear leveling process is performed so that the physical block addresses PBA0 to PBA4095 are used evenly without copying to b9 (physical block address). Since wear leveling is a generally known technique, description thereof is omitted.

Since the data to be written is 1 Mbyte from the logical address 0, assuming that the sector size is 512 bytes, the data is written in 2048 sectors according to equation (1). That is, in the logical address format of FIG. 5, 11 bits from b10 to b0 are bits that change according to the logical address, and b20 to b11 always have the value 0. Therefore, in this case, data is written in four physical blocks only on the nonvolatile memory 130 side.
1 Mbyte / 512 bytes = 2048 = 2 ¹¹ (1)

  The physical address determined as described above is transferred to the read / write control unit 123. The read / write control unit 123 transfers the physical address and data temporarily stored in the buffer 122 to the nonvolatile memory 130 (FIG. 6A).

  6A and 6B are time charts showing writing in a high-speed nonvolatile memory. The transfer period TT is a period in which data is transferred from the memory controller 120 to the nonvolatile memories 130 and 140 via the memory bus. The write time WT is a memory array after the nonvolatile memories 130 and 140 receive data. This is the period for writing data to The target time is a time corresponding to the write speed targeted by the nonvolatile memory device 110.

In FIG. 6A, a physical address and data are transferred for each page size which is a writing unit in the transfer period TT. Writing is performed to the memory cells of the nonvolatile memory 130 in the writing period WT immediately after that. In FIG. 6A, the target time is the time required for the nonvolatile storage device 110 to complete the writing. For example, in the case of MPEG2 moving image recording, a writing speed of 2 Mbytes / second to 4 Mbytes / second is used. is necessary. In the following description, for the sake of simplicity, the target writing speed is 4 Mbytes / second. When this is converted into a target time for writing per 4 kbytes according to the following equation (2), 1 ms is obtained.
4 kbytes / 4 Mbyte seconds = 1 msec (2)

  Next, the writing time to the nonvolatile memory 130 will be described. The binary NAND flash memory has a higher writing speed than the multi-level NAND. For example, the writing time (WT) of the binary flash memory (1 Gbyte product) manufactured by Company A is 300 μsec. Further, the time (TT) required for transfer varies depending on the design, but it is sufficient if 100 μsec is secured.

Therefore, as shown in FIG. 6A and the following expression (3), it can be seen that the time required to write data of 2 kbytes (one page) continuously twice is 800 μsec.
(300 μsec + 100 μsec) × 2 = 800 μsec (3)
In other words, 4 kbytes of data can be written within the target time of 1 ms. In other words, if the flash memory has a combined write time and transfer time of 500 μsec or less, the target speed can be satisfied even with the serial write (mode A) shown in FIG. 6A. Although it is necessary to erase a physical block (for 256 kbytes) which becomes unnecessary by rewriting or the like at a certain timing, the erasure is omitted here for simplicity.

  In a relatively high-speed flash memory such as this flash memory, when parallel writing is performed as shown in FIG. 6B, writing is completed in half or less of the target time. However, the peak current generated in the writing period is doubled, and the life of the battery mounted on the access device 100 is shortened. That is, it can be said that it is more reasonable to perform the serial writing as shown in FIG. 6A if the optimization is made so that the lifetime is extended while satisfying the target speed.

  Next, the case where the mode B is set in the initialization process when the power is turned on will be described. For example, when a multi-value flash memory (1 Gbyte product) manufactured by company A is used, mode B is set.

  FIG. 7 is a diagram showing a logical address space and a physical address space corresponding to this in the mode B. In this case, one logical block address has a capacity of 512 kB in the logical block addresses 0 to 4095, and two physical blocks of the nonvolatile memory are allocated to one logical block address. Each physical block is 256 kB.

  FIG. 8 is an explanatory diagram showing a logical-physical conversion method between a logical address and a physical address in mode B. Since the memory number is assigned to b2 of the logical address format, the non-volatile memories 130 and 140 are alternately designated every 2 kbytes for the continuous logical address.

  As in the case of mode A described above, only the difference will be described in the case where a write command for data of 1 Mbytes is transferred from the access device 100 to logical addresses continuous from logical address 0.

  In the logical-physical conversion unit 126, in the logical-physical conversion process, b9 to b0 of the logical address format are directly copied to the corresponding bits of the physical address format, but b20 to b10 (logical block address) of the logical address format are directly physical addresses. A wear leveling process is performed in which the space between the physical block addresses PBA0 to PBA4095 is used evenly without being copied to the format b19 to b9 (physical block address).

  Since the logical address of the data to be written is from 0 to 1 Mbytes, 11 bits from b10 to b0 in the logical address format of FIG. 8 are changed according to the logical address according to the equation (1), and b20 to b11 are The value is always 0. Since the bit to which the memory number is assigned is b2, as shown in FIG. 7, data is alternately written in the nonvolatile memories 130 and 140 every 2 kbytes.

  The physical address determined as described above is transferred to the read / write controller 123, and the read / write controller 123 transfers the physical address and the data temporarily stored in the buffer 122 to the nonvolatile memories 130 and 140.

In FIG. 9B, the transfer time and the target time are the same as those in FIG. The write time is longer than that in FIG. 6A because the multi-level NAND flash memory is used. For example, the write time WT of the multi-value flash memory (1 Gbyte product) manufactured by Company A is 800 μsec. Therefore, as shown in FIG. 9B, it can be seen that the time required for writing 2 kbytes of data in parallel is 900 μsec according to the following equation (4) with the transfer time TT (100 μsec) added.
800 μsec + 100 μsec = 900 μsec (4)
That is, data of 4 kbytes can be written within the target time of 1 ms. In other words, if the flash memory has a combined write time and transfer time of 1000 μsec or less, the parallel writing (mode B) shown in FIG. 9B can satisfy the target speed. In this case, it can be seen that the target time cannot be satisfied when serial writing is performed as shown in FIG. 9A.

  In other words, in the serial write mode A, as shown in FIG. 5, by setting the memory number at the higher rank of the physical block address, data can be written to either one of the non-volatile memories as shown in FIG. it can. In the parallel write processing in mode B, by setting the address used as the memory number as shown in FIG. 8 to be equal to or less than the page unit which is the minimum write unit, a plurality of nonvolatile memories are stored in the minimum write unit as shown in FIG. On the other hand, data can be written in parallel.

  As described above, by switching the logical-physical conversion mode according to the writing speed of the nonvolatile memory to be used, rationalization at the peak current can be achieved while maintaining the target speed. The contents of the mode table shown in FIG. 3 may be determined at the design stage of the nonvolatile memory device 110. However, it is desirable that the mode table can be easily changed in order to be compatible with future nonvolatile memories. For this purpose, for example, a mode table is stored in a part of the non-volatile memory 130 or 140, and is read out to a RAM provided in the logical-physical conversion mode determination unit 125 in the initialization process when the power is turned on. do it. When the mode table is changed, the mode table may be rewritten during the manufacturing process of the nonvolatile memory device.

(Second Embodiment)
Hereinafter, a nonvolatile memory system according to the second embodiment of the present invention will be described. FIG. 10 is a block diagram of a nonvolatile memory system according to the second embodiment. The basic configuration is the same as that of the nonvolatile memory system according to the first embodiment shown in FIG. The nonvolatile memory device 810 of this embodiment includes a memory controller 820 and nonvolatile memories 130 and 140, but the number of memory buses connected to these memories is one. The read / write controller 823 outputs chip enable signals CE0 and CE1 for switching between the nonvolatile memories 130 and 140.

Next, the operation of the present embodiment will be described. Note that the initialization process when the power is turned on is the same as in the first embodiment, and a description thereof will be omitted.
[Processing during normal operation]
When the selected nonvolatile memory is a high-speed nonvolatile memory, data transmission and writing are performed in series as shown in FIG. 11A. In this way, in the case of a binary NAND flash memory similar to that described above, the write time of two times falls within the target time, and the write can be completed within this time. In this case, if the parallel writing process is performed, only the transfer time is shifted as shown in FIG. In this case, it becomes about ½ of the target time, which is overspec.

  If the selected non-volatile memory is low speed, serial writing in the A mode will exceed the target time as shown in FIG. 12A. In this case, parallel write processing is performed in mode B as shown in FIG. In this way, the writing process can be completed within the target time.

  Unlike the non-volatile storage system according to the first embodiment, since the memory bus is shared, the data transfer period for the non-volatile memory 130 and the data transfer period for the non-volatile memory 140 are timed so that memory bus contention does not occur. Need to be shifted. For this purpose, the read / write control unit 823 switches between data transfer and a chip enable signal in units of 2 kbytes. Other operations are the same as those of the nonvolatile memory system according to the first embodiment.

  As described above, as described in the first embodiment and the second embodiment, the logical-physical conversion mode determination unit 125 performs the logical-physical conversion unit 126 according to the mode table according to the type of nonvolatile memory to be used. Since the logical-physical conversion mode is switched as shown in FIG. 4 or FIG. 7, it is possible to rationalize the power while maintaining the target performance. Also in the first embodiment, the transfer period may be shifted as shown in FIGS.

  In the first and second embodiments, the read / write control unit 123 or 823 performs write control on both the nonvolatile memories 130 and 140. Alternatively, two sets of memory controllers 120 or 820 may be provided, and one memory controller may perform read / write control of the nonvolatile memory 130 and the other memory controller may perform read / write control of the nonvolatile memory 140. More generally, the memory controller is composed of a plurality of controller chips, and each controller chip and one or more nonvolatile memories are connected by one bus. However, in that case, it is necessary for one of the memory controllers to serve as a master controller, and the master controller distributes data. Further, the present invention is not limited to the above embodiment.

  The memory controller, the nonvolatile memory device, the nonvolatile memory system, and the data writing method according to the present invention can optimize the writing speed and the peak current in a device using a nonvolatile memory such as a flash memory. The apparatus according to the present invention can be used as a recording medium of a portable AV device such as a still image recording / reproducing device or a moving image recording / reproducing device, or a portable communication device such as a mobile phone.

1 is a block diagram of a nonvolatile storage system according to a first embodiment of the present invention. It is a memory map of the physical block in this Embodiment. It is explanatory drawing which shows an example of the mode table in this Embodiment. It is a figure which shows the relationship between the logical address by mode A, and a physical address. It is explanatory drawing which shows the logical-physical conversion method at the time of using a high-speed non-volatile memory. It is a time chart showing the writing in the mode A with respect to a high-speed non-volatile memory. It is a time chart showing the writing in the mode B with respect to a high-speed non-volatile memory. It is a figure which shows the relationship between the logical address by mode B, and a physical address. It is explanatory drawing which shows the logical-physical conversion method at the time of using a low-speed non-volatile memory. It is a time chart showing the writing in the mode A with respect to a low-speed non-volatile memory. It is a time chart showing the writing in the mode B with respect to a low-speed nonvolatile memory. It is a block diagram of the non-volatile storage system in 2nd Embodiment. It is a time chart showing the writing in the mode A with respect to a high-speed non-volatile memory. It is a time chart showing the writing in the mode B with respect to a high-speed non-volatile memory. It is a time chart showing the writing of mode A with respect to a low-speed non-volatile memory. It is a time chart showing the writing of the mode B with respect to a low-speed non-volatile memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Access apparatus 110,810 Nonvolatile storage device 120,820 Memory controller 121 Host interface 122 Buffer 123,823 Read / write control part 124 CPU part 125 Logical-physical conversion mode determination part 126 Logical-physical conversion part 130 Nonvolatile memory (flash memory 0)
140 Nonvolatile memory (flash memory 1)

Claims (18)

A memory controller connected to a plurality of nonvolatile memories, writing data according to a logical address designated from the outside, and reading data from the nonvolatile memory,
Simultaneous write memory number determining means for determining the number of memories for simultaneously writing data to the plurality of nonvolatile memories according to the type of the nonvolatile memory;
A memory controller comprising: a read / write control unit that simultaneously writes data to the number of nonvolatile memories determined by the simultaneous write memory number determination unit and reads data from the nonvolatile memory. The simultaneous writing memory number determining means includes:
2. The memory according to claim 1, wherein when the writing performance of the nonvolatile memory is a high-speed type, the number of memories to be written simultaneously is reduced, and when the writing performance of the nonvolatile memory is a low-speed type, the number of memories to be written simultaneously is increased. controller. The simultaneous writing memory number determining means includes:
A logical-physical conversion mode determining means for determining the number of memories to be simultaneously written according to the type of the nonvolatile memory, and determining a logical-physical conversion mode corresponding to the number of memories;
The logical-physical conversion unit that associates the logical address with a physical address of the nonvolatile memory according to the logical-physical conversion mode determined by the logical-physical conversion mode determination unit. Memory controller. The non-volatile memory holds an ID code that identifies its type,
The said simultaneous writing memory number determination means determines the logical-physical conversion mode of the said logical-physical conversion means according to the writing speed of the data recognized by the ID code of the said non-volatile memory. Memory controller. The non-volatile memory holds a mode table that associates an ID code for identifying the non-volatile memory with a logical-physical conversion mode,
5. The memory controller according to claim 3, wherein the logical-physical conversion mode determination unit determines the logical-physical conversion mode by referring to the mode table.   The memory controller according to claim 1, wherein the memory controller includes a plurality of controller chips, and the controller chip and one or more nonvolatile memories are connected by a single bus. A plurality of nonvolatile memories;
A non-volatile storage device comprising a memory controller that writes data to the non-volatile memory according to a logical address designated from the outside and reads data from the non-volatile memory,
The memory controller is
Simultaneous write memory number determining means for determining the number of memories for simultaneously writing data to the plurality of nonvolatile memories according to the type of the nonvolatile memory;
A non-volatile storage device comprising: a read / write control unit that simultaneously writes data to the number of non-volatile memories determined by the simultaneous write memory number determining unit and reads data from the non-volatile memory. The simultaneous writing memory number determining means includes:
The nonvolatile memory according to claim 7, wherein when the writing performance of the nonvolatile memory is a high-speed type, the number of memories to be written simultaneously is reduced, and when the writing performance of the nonvolatile memory is a low-speed type, the number of memories to be written simultaneously is increased. Sex memory device. The simultaneous writing memory number determining means includes:
A logical-physical conversion mode determining means for determining the number of memories to be simultaneously written according to the type of the nonvolatile memory, and determining a logical-physical conversion mode corresponding to the number of memories;
9. The logical-physical conversion unit that associates the logical address with a physical address of the nonvolatile memory according to the logical-physical conversion mode determined by the logical-physical conversion mode determination unit. Non-volatile storage device. The non-volatile memory holds an ID code that identifies its type,
The said simultaneous writing memory number determination means determines the logical-physical conversion mode of the said logical-physical conversion means according to the writing speed of the data recognized by the ID code of the said non-volatile memory. Nonvolatile storage device. The non-volatile memory holds a mode table that associates an ID code for identifying the non-volatile memory with a logical-physical conversion mode,
The non-volatile storage device according to claim 9, wherein the logical-physical conversion mode determination unit determines the logical-physical conversion mode by referring to the mode table.   The nonvolatile memory according to claim 7, wherein the memory controller includes two or more controller chips, and each of the controller chips and one or more nonvolatile memories are connected by one bus. Storage device. The nonvolatile memory device according to any one of claims 7 to 12,
A non-volatile storage system comprising: an access device that writes data to the non-volatile storage device and reads data from the non-volatile storage device. A data writing method that is connected to a plurality of nonvolatile memories, writes data according to a logical address designated from the outside, and reads data from the nonvolatile memory,
Determine the number of memories that simultaneously write data to the plurality of nonvolatile memories according to the type of the nonvolatile memory,
A data writing method for simultaneously writing data to a determined number of nonvolatile memories. The determination of the number of simultaneous write memories is as follows:
15. The data writing method according to claim 14, wherein when the writing performance of the nonvolatile memory is a high-speed type, the number of memories to be simultaneously written is reduced, and when the writing performance of the nonvolatile memory is a low-speed type, the number of memories is increased. . The determination of the number of simultaneous write memories is as follows:
Determine the number of memories to be simultaneously written according to the type of the nonvolatile memory,
Determine the logical-physical conversion mode corresponding to the number of memories,
16. The data writing method according to claim 14, wherein the logical address is associated with a physical address of the nonvolatile memory according to the determined logical-physical conversion mode. The non-volatile memory holds an ID code that identifies its type,
17. The determination of the number of simultaneous write memories determines a logical-physical conversion mode of the logical-physical conversion unit according to a data writing speed recognized by an ID code of the nonvolatile memory. Data writing method. The non-volatile memory holds a mode table that associates an ID code for identifying the non-volatile memory with a logical-physical conversion mode,
18. The data writing method according to claim 16, wherein the logical-physical conversion mode is determined by referring to the mode table.

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