CN105137903A - Method for realizing PLC operation environment in SocFPGA - Google Patents
Method for realizing PLC operation environment in SocFPGA Download PDFInfo
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- CN105137903A CN105137903A CN201510365185.0A CN201510365185A CN105137903A CN 105137903 A CN105137903 A CN 105137903A CN 201510365185 A CN201510365185 A CN 201510365185A CN 105137903 A CN105137903 A CN 105137903A
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- socfpga
- fpga
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- plc
- running environment
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/052—Linking several PLC's
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25268—PLD programmable logic device
Abstract
The invention discloses a method for realizing PLC operation environment in a SocFPGA, belongs to the technical field of PLC operation environment, and solves the problem of how to realize the PLC operation environment in the SocFPGA. The method comprises that the PLC operation environment is divided into a logic operation portion and a real-time signal processing portion; the logic operation portion is realized in an ARM core of the SocFPGA, a real-time linux operating system is utilized to explain a ladder diagram algorithm; the real-time signal processing portion is realized by an FPGS in the SocFPGA and used to package and transmit data; and communication between the ARM core and the FPGA is realized by a high-speed bus in the SocFPGA.
Description
Technical field
The present invention relates to a kind of PLC running technology field, specifically a kind of method realizing PLC running environment on SocFPGA.
Background technology
Programmable logic controller (PLC) (English full name ProgrammableLogicController, be called for short PLC) be a kind of be specially industry automatic control and the general automaton developed, it adopts a class programmable memory, for its internally stored program, actuating logic computing, sequential control, regularly, counting and the user oriented instruction such as arithmetical operation, and by numeral or analog pattern input/output various types of machinery of control or production run.The feature such as it has that reliability is high, simple, easy to use, the perfect in shape and function of programming, versatility are good, and there is online modification function, bring good flexibility to control system.It can adapt to the requirement of different control object, magnitude control and controlling functions neatly with different configurations, be to realize " electromechanical integration " comparatively ideal opertaing device.General PLC control system is divided into two parts, and a part is programmed environment: comprise ladder diagram editor display, variable edit, engineering configures, program compilation etc.; Another part is running environment: mainly programmed environment compiling is generated project file and explain and perform.
PLC running environment domestic at present general in special PLC chip, adopt the profibus bus of the system integration, special PLC chip does not generally comprise operating system, the multitask realizing PLC switches very complicated, file store and Internet Transmission very loaded down with trivial details, the bandwidth of profibus bus only has 12M, and the logical operation part of conventional P LC and control signal transmission all carry out computing and transmission by special chip or single-chip microcomputer, and overall execution efficiency is lower.
SoC, English full name SystemonaChip, is translated as SOC (system on a chip).Refer to an integrated complete system on a single chip, the technology of wrapping grouping is carried out to the electronic circuit of all or part necessity.So-called complete system generally comprises central processing unit (CPU), storer and peripheral circuit etc.SoC and other technology Parallel Development, as Silicon-On-Insulator (SOI), it can provide the clock frequency of enhancing, thus reduces the power consumption of microchip.Due to unique efficient integrated performance, SOC (system on a chip) is the primary solutions of alternative integrated circuit.SoC has become the inexorable trend of current microelectronic chip development.
FPGA is the abbreviation of English Field-ProgrammableGateArray, i.e. field programmable gate array, and it is the product further developed on the basis of the programming devices such as PAL, GAL, EPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, overcomes again the shortcoming that original programming device gate circuit number is limited.
SocFPGA is a high-end FPGA of Altera, and an embedded double-core ARMCortex-A9 processor, this processor occurs in stone mode.How making this SocFPGA realize the running environment of programmable logic controller (PLC), is current those skilled in the art problems in the urgent need to address.
summary of the invention
Technical assignment of the present invention is for above weak point, provides a kind of method realizing PLC running environment on SocFPGA.Solve the problem how realizing the running environment of programmable logic controller (PLC) at SocFPGA.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of method realizing PLC running environment on SocFPGA, the running environment of PLC is divided into logical operation part and real time signal processing part, logical operation part adopts the ARM core on SocFPGA to realize, and adopts real-time linux operating system, is used for explaining ladder diagram algorithm; Real time signal processing part, adopts the FPGA on SocFPGA to realize, is used for packing to data and transmitting; Communicated by the high-speed bus of SocFPGA inside between ARM core and FPGA.
Communication protocol between ARM core and FPGA is Avalon communication protocol, addressing space 960M.
Specifically comprise the steps:
(1), the running environment of PLC is divided into logical operation part and real time signal processing part;
(2), logical operation part adopts the ARM core on SocFPGA to realize, and by the ARM core of linux operating system transplantation to SocFPGA, then transplanted by PLC running environment code, can run in the linux operating system of SocFPGA;
(3), write SocFPGA high-speed communication bus driver, the control routine between PLC master station and slave station is transplanted;
(4), real time signal processing part, adopt the FPGA on SocFPGA to realize;
(5), by the high-speed communication bus between the Qsys software editing ARM core of Altera and FPGA;
(6), avalon communication protocol is adopted, RAM on the sheet of FPGA is mapped to one section of internal memory of linux operating system, the control routine of master station and follow station is write this internal memory by PLC running environment, FPGA end writes memory read-write program, control routine packing is exported by outside real-time bus and controls other slave stations and IO board, realize high-speed real-time communication.
The realization of (SuSE) Linux OS on SocFPGA, comprises the steps:
(1), the upper preloader of SocFPGA transplants: Preloader is one section of initial boot that SocFPGA system starts, and this boot is recompilated and is loaded into chip external memory;
(2), the upper uboot of SocFPGA transplants: Uboot is the boot of linux operating system, and amendment Uboot configuration parameter, makes its adaptive SocFPGA, guide from SocFPGA chip external memory; The bsp-edit instrument of Ateral is utilized to generate Uboot source code, configure crossstool arm-linux-gnueabihf-gcc under a linux operating system, perform Makeuboot and produce u-boot.img file, by USB-blaster by this file programming to the 0x60000 address of the chip external memory of SocFPGA;
(3), the upper kernel of SocFPGA transplants: Kernel is linux operating system kernel code, the core source code bag solution of kernel is depressed into ~/SOC file under, configuration crossstool, perform makeARCH=armLOADADDR=0x8000uImage and can generate the source code zImage of kernel, by tftpd by zImage programming to the 0xa0000 address of the chip external memory of SocFPGA;
(4), the upper rootfs of SocFPGA transplants: Rootfs is the root file system of linux operating system, the source code bag solution with file system is depressed into ~/buildroot file under;
Configuration crossstool arm-linux-gnueabihf-gcc, perform makeARCH=ARMBR2_TOOLCHAIN_EXTERNAL_PATH=/opt/gcc-linaro-arm-linux-gnueabihf-4.8-2013.12_linux/all, rootfs.jffs2 file can be generated, by tftpd by rootfs.jffs2 programming to the 0x800000 address of the chip external memory of SocFPGA;
(5), the upper PLC running environment of SocFPGA realizes: amendment PLC running environment program, uses cross compile chain to recompilate running environment program, write SocFPGA bus driver and IO Labcard driver program; Finally generating run environment executable program is copied to the linux operating system environment of SocFPGA, arrange and automatically start.
The upper high-speed bus editor of SocFPGA, comprises the steps:
(1), SocFPGA upper FPGA bus editor: communicated by inner high speed bus between the upper ARM core of SocFPGA and FPGA, communication protocol is Avalon, the bus between ARM core and FPGA on-chip memory is set up by Qsys bus edit tool, communication data is write this storer by ARM core, FPGA is from this memory read data simultaneously, carries out arbitration read-write sequence between ARM core and FPGA by Avalon bus;
(2), the upper ARM core of SocFPGA and FPGA high-speed communication: Avalon communication bus proposes with altera corp, for connecting in ARM core and sheet, a kind of high-speed bus of the outer peripheral hardware of sheet;
(3), bus program loads: by compiled bus program file soc_system.rbf, be loaded into FPGA by uboot.
Compared to the prior art a kind of method realizing PLC running environment on SocFPGA of the present invention, has the following advantages:
1, PLC running environment realized being divided into two parts, logical operation part realizes on ARM core, and real time signal processing part realizes on FPGA; Adopt the logical operation capability of ARM core and the real time signal processing ability of FPGA on SocFPGA, improve PLC logical operation capability and real time signal processing ability;
2, PLC running environment logical operation part realizes communicating by high-speed internal bus with real time signal processing part, and PLC running environment logical operation part and real time signal processing section communication adopt Avalon communication protocol;
3, both meet the logical operation capability of PLC complexity, meet again the real time signal processing ability of PLC.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the present invention is further described.
Accompanying drawing 1 is that a kind of SocFPGA realizing the method for PLC running environment on SocFPGA realizes PLC running environment legend;
Accompanying drawing 2 is that a kind of Preloader realizing the method for PLC running environment on SocFPGA transplants legend;
Accompanying drawing 3 is a kind of Avalon bus legend realizing the method for PLC running environment on SocFPGA.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
Embodiment 1:
A kind of method realizing PLC running environment on SocFPGA of the present invention, the running environment of PLC is divided into logical operation part and real time signal processing part, logical operation part adopts the ARM core on SocFPGA to realize, and adopts real-time linux operating system, is used for explaining ladder diagram algorithm; Real time signal processing part, adopts the FPGA on SocFPGA to realize, is used for packing to data and transmitting; Communicated by the high-speed bus of SocFPGA inside between ARM core and FPGA.
Embodiment 2:
A kind of method realizing PLC running environment on SocFPGA of the present invention, the running environment of PLC is divided into logical operation part and real time signal processing part, logical operation part adopts the ARM core on SocFPGA to realize, and adopts real-time linux operating system, is used for explaining ladder diagram algorithm; Real time signal processing part, adopts the FPGA on SocFPGA to realize, is used for packing to data and transmitting; Communicated by the high-speed bus of SocFPGA inside between ARM core and FPGA.
Communication protocol between ARM core and FPGA is Avalon communication protocol, addressing space 960M.
Specifically comprise the steps:
(1), the running environment of PLC is divided into logical operation part and real time signal processing part;
(2), logical operation part adopts the ARM core on SocFPGA to realize, and by the ARM core of linux operating system transplantation to SocFPGA, then transplanted by PLC running environment code, can run in the linux operating system of SocFPGA;
(3), write SocFPGA high-speed communication bus driver, the control routine between PLC master station and slave station is transplanted;
(4), real time signal processing part, adopt the FPGA on SocFPGA to realize;
(5), by the high-speed communication bus between the Qsys software editing ARM core of Altera and FPGA;
(6), avalon communication protocol is adopted, RAM on the sheet of FPGA is mapped to one section of internal memory of linux operating system, the control routine of master station and follow station is write this internal memory by PLC running environment, FPGA end writes memory read-write program, control routine packing is exported by outside real-time bus and controls other slave stations and IO board, realize high-speed real-time communication.
Embodiment 3:
A kind of method realizing PLC running environment on SocFPGA of the present invention, the running environment of PLC is divided into logical operation part and real time signal processing part, logical operation part adopts the ARM core on SocFPGA to realize, and adopts real-time linux operating system, is used for explaining ladder diagram algorithm; Real time signal processing part, adopts the FPGA on SocFPGA to realize, is used for packing to data and transmitting; Communicated by the high-speed bus of SocFPGA inside between ARM core and FPGA.
Communication protocol between ARM core and FPGA is Avalon communication protocol, addressing space 960M.
Specifically comprise the steps:
(1), the running environment of PLC is divided into logical operation part and real time signal processing part;
(2), logical operation part adopts the ARM core on SocFPGA to realize, and by the ARM core of linux operating system transplantation to SocFPGA, then transplanted by PLC running environment code, can run in the linux operating system of SocFPGA;
(3), write SocFPGA high-speed communication bus driver, the control routine between PLC master station and slave station is transplanted;
(4), real time signal processing part, adopt the FPGA on SocFPGA to realize;
(5), by the high-speed communication bus between the Qsys software editing ARM core of Altera and FPGA;
(6), avalon communication protocol is adopted, RAM on the sheet of FPGA is mapped to one section of internal memory of linux operating system, the control routine of master station and follow station is write this internal memory by PLC running environment, FPGA end writes memory read-write program, control routine packing is exported by outside real-time bus and controls other slave stations and IO board, realize high-speed real-time communication.
The realization of (SuSE) Linux OS on SocFPGA, comprises the steps:
(1), the upper preloader of SocFPGA transplants: Preloader is one section of initial boot that SocFPGA system starts, and this boot is recompilated and is loaded into chip external memory; Fig. 1 is the transplanting legend of Preloader, the bsp-edit instrument of Ateral is utilized to generate Preloader source code, crossstool arm-linux-gnueabihf-gcc is configured under linux operating system, perform Make and produce preloader-mkpimage.bin file, by USB-blaster by this file programming to the 0x00000000 address of the chip external memory of SocFPGA, Fig. 2 is SocFPGA chip external memory address assignment;
(2), the upper uboot of SocFPGA transplants: Uboot is the boot of linux operating system, and amendment Uboot configuration parameter, makes its adaptive SocFPGA, guide from SocFPGA chip external memory; The bsp-edit instrument of Ateral is utilized to generate Uboot source code, configure crossstool arm-linux-gnueabihf-gcc under a linux operating system, perform Makeuboot and produce u-boot.img file, by USB-blaster by this file programming to the 0x60000 address of the chip external memory of SocFPGA;
(3), the upper kernel of SocFPGA transplants: Kernel is linux operating system kernel code, the core source code bag solution of kernel is depressed into ~/SOC file under, configuration crossstool, perform makeARCH=armLOADADDR=0x8000uImage and can generate the source code zImage of kernel, by tftpd by zImage programming to the 0xa0000 address of the chip external memory of SocFPGA;
(4), the upper rootfs of SocFPGA transplants: Rootfs is the root file system of linux operating system, the source code bag solution with file system is depressed into ~/buildroot file under;
Configuration crossstool arm-linux-gnueabihf-gcc, perform makeARCH=ARMBR2_TOOLCHAIN_EXTERNAL_PATH=/opt/gcc-linaro-arm-linux-gnueabihf-4.8-2013.12_linux/all, rootfs.jffs2 file can be generated, by tftpd by rootfs.jffs2 programming to the 0x800000 address of the chip external memory of SocFPGA;
(5), the upper PLC running environment of SocFPGA realizes: amendment PLC running environment program, uses cross compile chain to recompilate running environment program, write SocFPGA bus driver and IO Labcard driver program; Finally generating run environment executable program is copied to the linux operating system environment of SocFPGA, arrange and automatically start.
The upper high-speed bus editor of SocFPGA, comprises the steps:
(1), SocFPGA upper FPGA bus editor: communicated by inner high speed bus between the upper ARM core of SocFPGA and FPGA, communication protocol is Avalon, the bus between ARM core and FPGA on-chip memory is set up by Qsys bus edit tool, communication data is write this storer by ARM core, FPGA is from this memory read data simultaneously, carries out arbitration read-write sequence between ARM core and FPGA by Avalon bus;
(2), the upper ARM core of SocFPGA and FPGA high-speed communication: Avalon communication bus proposes with altera corp, for connecting in ARM core and sheet, a kind of high-speed bus of the outer peripheral hardware of sheet; Itself be a digital logic system, while realization " signal wire tandem " this conventional bus function, add the functional module of much inside, as: from end arbitration mode, many main sides working method, delay data transmission etc., as shown in Figure 3;
(3), bus program loads: by compiled bus program file soc_system.rbf, be loaded into FPGA by uboot.Namely PLC running environment program communicates with FPGA by Avalon bus after starting; As shown in Figure 1.
Above-mentioned embodiment is only concrete case of the present invention; scope of patent protection of the present invention includes but not limited to above-mentioned embodiment; any according to the invention a kind of on SocFPGA, realize claims of the method for PLC running environment and any person of an ordinary skill in the technical field to its suitable change done or replacement, all should fall into scope of patent protection of the present invention.
Claims (5)
1. one kind realizes the method for PLC running environment on SocFPGA, the running environment of PLC is it is characterized in that to be divided into logical operation part and real time signal processing part, logical operation part adopts the ARM core on SocFPGA to realize, adopt real-time linux operating system, be used for explaining ladder diagram algorithm; Real time signal processing part, adopts the FPGA on SocFPGA to realize, is used for packing to data and transmitting; Communicated by the high-speed bus of SocFPGA inside between ARM core and FPGA.
2. a kind of method realizing PLC running environment on SocFPGA according to claim 1, is characterized in that the communication protocol between ARM core and FPGA is Avalon communication protocol, addressing space 960M.
3. a kind of method realizing PLC running environment on SocFPGA according to claim 1, is characterized in that specifically comprising the steps:
(1), the running environment of PLC is divided into logical operation part and real time signal processing part;
(2), logical operation part adopts the ARM core on SocFPGA to realize, and by the ARM core of linux operating system transplantation to SocFPGA, then transplanted by PLC running environment code, can run in the linux operating system of SocFPGA;
(3), write SocFPGA high-speed communication bus driver, the control routine between PLC master station and slave station is transplanted;
(4), real time signal processing part, adopt the FPGA on SocFPGA to realize;
(5), by the high-speed communication bus between the Qsys software editing ARM core of Altera and FPGA;
(6), avalon communication protocol is adopted, RAM on the sheet of FPGA is mapped to one section of internal memory of linux operating system, the control routine of master station and follow station is write this internal memory by PLC running environment, FPGA end writes memory read-write program, control routine packing is exported by outside real-time bus and controls other slave stations and IO board, realize high-speed real-time communication.
4. a kind of method realizing PLC running environment on SocFPGA according to claim 1, is characterized in that the realization of (SuSE) Linux OS on SocFPGA, comprises the steps:
(1), the upper preloader of SocFPGA transplants: Preloader is one section of initial boot that SocFPGA system starts, and this boot is recompilated and is loaded into chip external memory;
(2), the upper uboot of SocFPGA transplants: Uboot is the boot of linux operating system, and amendment Uboot configuration parameter, makes its adaptive SocFPGA, guide from SocFPGA chip external memory; The bsp-edit instrument of Ateral is utilized to generate Uboot source code, configure crossstool arm-linux-gnueabihf-gcc under a linux operating system, perform Makeuboot and produce u-boot.img file, by USB-blaster by this file programming to the 0x60000 address of the chip external memory of SocFPGA;
(3), the upper kernel of SocFPGA transplants: Kernel is linux operating system kernel code, the core source code bag solution of kernel is depressed into ~/SOC file under, configuration crossstool, perform makeARCH=armLOADADDR=0x8000uImage and can generate the source code zImage of kernel, by tftpd by zImage programming to the 0xa0000 address of the chip external memory of SocFPGA;
(4), the upper rootfs of SocFPGA transplants: Rootfs is the root file system of linux operating system, the source code bag solution with file system is depressed into ~/buildroot file under;
Configuration crossstool arm-linux-gnueabihf-gcc, perform makeARCH=ARMBR2_TOOLCHAIN_EXTERNAL_PATH=/opt/gcc-linaro-arm-linux-gnueabihf-4.8-2013.12_linux/all, rootfs.jffs2 file can be generated, by tftpd by rootfs.jffs2 programming to the 0x800000 address of the chip external memory of SocFPGA;
(5), the upper PLC running environment of SocFPGA realizes: amendment PLC running environment program, uses cross compile chain to recompilate running environment program, write SocFPGA bus driver and IO Labcard driver program; Finally generating run environment executable program is copied to the linux operating system environment of SocFPGA, arrange and automatically start.
5. a kind of method realizing PLC running environment on SocFPGA according to claim 1, is characterized in that high-speed bus editor on SocFPGA, comprises the steps:
(1), SocFPGA upper FPGA bus editor: communicated by inner high speed bus between the upper ARM core of SocFPGA and FPGA, communication protocol is Avalon, the bus between ARM core and FPGA on-chip memory is set up by Qsys bus edit tool, communication data is write this storer by ARM core, FPGA is from this memory read data simultaneously, carries out arbitration read-write sequence between ARM core and FPGA by Avalon bus;
(2), the upper ARM core of SocFPGA and FPGA high-speed communication: Avalon communication bus proposes with altera corp, for connecting in ARM core and sheet, a kind of high-speed bus of the outer peripheral hardware of sheet;
(3), bus program loads: by compiled bus program file soc_system.rbf, be loaded into FPGA by uboot.
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| CN106843127A (en) * | 2017-02-28 | 2017-06-13 | 深圳市麦格米特控制技术有限公司 | A kind of Medium PLC system |
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| CN108153226A (en) * | 2017-12-22 | 2018-06-12 | 安徽杰智智能科技有限公司 | A kind of PLC device of novel real-time, interactive |
| CN108845537A (en) * | 2018-06-08 | 2018-11-20 | 山东超越数控电子股份有限公司 | The communication means of CPU and digital logic module in PLC system based on SOC FPGA |
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| CN108845537A (en) * | 2018-06-08 | 2018-11-20 | 山东超越数控电子股份有限公司 | The communication means of CPU and digital logic module in PLC system based on SOC FPGA |
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