CN1956540A - Control system of audio-video transmission based on optical fibre transmission - Google Patents

Control system of audio-video transmission based on optical fibre transmission Download PDF

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CN1956540A
CN1956540A CNA2006101134441A CN200610113444A CN1956540A CN 1956540 A CN1956540 A CN 1956540A CN A2006101134441 A CNA2006101134441 A CN A2006101134441A CN 200610113444 A CN200610113444 A CN 200610113444A CN 1956540 A CN1956540 A CN 1956540A
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chip
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CN100461857C (en
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张春熹
史洁琴
段靖远
马迎建
刘惠兰
杨玉生
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Beihang University
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Beihang University
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Abstract

This invention discloses a control system for the audio and video transmission based on fiber transmission composed of a central processor, a collector, a signal receiving and distributing device, a photoelectric converter and a protocol interface unit, in which, said central processor is used in realizing the buffer storage of digital audio and video signals, the transmission of audio and video format signals of said collector, the response of signals of merged enquiry audio and video device kind and the operation mode of said signal receiving and distributing unit, said central processor includes a DSP processor, a FPGA programmable gate array and a program storage unit, said signal receiving and distributing device is used in realizing the distribution of the processed signals and merging of the electric signals of the protocol enquiry audio and video device kind, said protocol device is used in realizing photoelectric conversion of light signals and outputting signals of high bandwidth and high resolution to a controller and the photoelectric conversion of electric signals of the device kind.

Description

A kind of control system of transmitting based on the audio frequency and video of Optical Fiber Transmission
Technical field
The present invention relates to a kind of control device that is used for the audio frequency and video transmission, more particularly say, be meant that a kind of employing optical fiber connects each audio ﹠ video equipment, and to audio/video information utilization Optical Fiber Transmission and a kind of novel audio frequency and video transmission control system that meets communication IEEE1394b protocol transmission.
Background technology
Since 1970, avionics system develops rapidly from model configuration independently becomes the integrated digital structure.On this basis, the comprehensive and distributed frame of traditional association type system forward develops.In the association type system, each subsystem occurs with the form of black box, and is continuous by the MIL-STD-1553B or the ARINC-429 of low speed.Yet, according to 1 times of per 18 monthly increment of Moore's Law processing speed.Therefore, following avionics system needs the data channel of high bandwidth, to satisfy the more transmission of more information between the multiple subsystem, reduces the delay of transfer of data between the high speed processor simultaneously.
Fiber optic network possesses the potentiality of innovation avionics system, and high bandwidth and high-caliber comprehensive can be provided.It is simpler and healthy and strong that the sourceless characteristic of its optics makes that network connects.In addition, commercial Fibre Optical Communication Technology because be subjected to soft widely, hardware supports and upgrading fast, be applied in the aerospace field gradually.Optical-fiber network has potential to make up the new vehicle electronic comprehensive system of big capacity, anti-interference, flexible configuration.Follow the development of aviation field, the data transmission media of vehicle electric system just is upgraded to optical fiber from copper.
At present, the general cable that adopts connects between the audio ﹠ video equipment of main flow, and its transmission bandwidth is lower than 200Mbps, and time-delay reaches about 5s, and transmission range is that audio, video data is subject to electromagnetic interference in the 10m.Interface between the audio ﹠ video equipment adopts USB or the output of direct modeling signal, causes the defective that time-delay is high, bandwidth is low.
In order to obtain the high real-time audio, video data of long transmission distance, clear picture, the present invention proposes a kind of control system of transmitting based on the audio frequency and video of Optical Fiber Transmission.
Summary of the invention
The objective of the invention is to propose a kind of control system of transmitting based on the audio frequency and video of Optical Fiber Transmission, this audio frequency and video transmission control system is to go up transmission of video, audio frequency and packet simultaneously at same circuit (each audio-video device adopts the physical connection of optical fiber).Possesses the structure of easy expansion, the deterministic communication of peer-to-peer network topological sum high speed flexibly.With respect to dielectric, the sourceless characteristic of light medium makes the audio frequency and video transmission control system simpler, more strong and more low-cost, is convenient to realize high bandwidth and high-caliber comprehensive.Adopt the mode of operation of center processor control distributor and collector, adopt physical chip, the discrete structure of link layer chip that audio-video signal is received distribution, adopt optical-electrical converter to realize the support of physical chip, realized audio, video data transmission with high bandwidth, low delay, high-resolution, high noise immunity on optical fiber link optical fiber transmission medium.
The present invention is a kind of control system of transmitting based on the audio frequency and video of Optical Fiber Transmission, receives distributor, optical-electrical converter and protocol interface device by center processor, collector, signal and forms.Described collector is used to receive the audio-video signal of audio-video device output, and described audio-video signal is carried out analog digital conversion back export digital audio-video signal f 0Give center processor; Described center processor is used for (a) and realizes digital audio-video signal f 0Buffer memory, (b) realize the audio frequency and video format configuration signal h of described collector 0Transmission, (c) the inquiry audio ﹠ video equipment type signal g after realizing merging 2Response and (d) realize that described signal receives the configuration of the operational mode of distributor; Described center processor comprises dsp processor, FPGA programmable gate array and program storage; Described signal receives distributor, is used for the audio-video signal f after (a) realization is handled 1Distribution, (b) realize agreement inquiry audio ﹠ video equipment type of electrical signal g 1Fusion; Described optical-electrical converter is used for (a) and realizes protocol audio-video photosignal f 3Electric light conversion, (b) realize agreement inquiry audio ﹠ video equipment type light signal g 0Opto-electronic conversion; Described protocol interface device is used for (a) and realizes protocol audio-video light signal f 4Opto-electronic conversion, and output high bandwidth, high-resolution audio-video signal realize the electric light conversion of inquiry audio ﹠ video equipment type of electrical signal for watch-dog, (b).
The advantage of control system that the present invention is based on the audio frequency and video transmission of Optical Fiber Transmission is:
(1) adopt the multimode silica fiber to connect each audio ﹠ video equipment, improved the rate of information throughput, bandwidth can reach 1.25Gbps, can adapt to the adverse circumstances that the temperature difference is big, electromagnetic interference is strong;
(2) communications protocol (IEEE1394b agreement) that adopts of audio frequency and video transmission control system of the present invention can realize that peer-to-peer network connects, support that transmission parameter can dynamically adjust wait the time transmission, and support Moving Picture Experts Group-2.Network node is supported hot plug corresponding to the Storage Mapping network address of automatically distributing, and application program that need not Central Control Module is disturbed;
(3) adopt the configuration ROM structural model that meets the SBP-2 agreement, need not write driver specially, can discern different audio-video devices;
The collector of standards such as (4) adopting can compatible PAL, NTSC, SECOM, can be on the monitor of supporting different systems display video signal;
(5) adopt the optical-electrical converter of supporting 850nm multimode silica fiber, reduced cost effectively, realized the photoelectricity/electro-optical signal conversion of high reliability;
(6) adopt high performance floating type DSP, realize the high speed processing of audio-video signal, when waiting and asynchronous transmission means, guarantee the low delay of the wide and control command of height that audio frequency and video transmit;
Description of drawings
Fig. 1 is a control structure block diagram of the present invention.
Fig. 2 is the circuit theory diagrams of dsp processor.
Fig. 2 A is the circuit theory diagrams of memory.
Fig. 2 B is the circuit theory diagrams of FPGA.
Fig. 3 A is the circuit theory diagrams that signal receives the physical chip of distributor.
Fig. 3 B is the circuit theory diagrams that signal receives the link layer chip of distributor.
Fig. 3 C is the interface of signal reception distributor, the circuit theory diagrams of optical-electrical converter.
Fig. 4 is the circuit theory diagrams of collector.
Fig. 5 A is the circuit theory diagrams of the link layer chip of protocol interface device.
Fig. 5 B is the circuit theory diagrams of the physical chip of protocol interface device.
Fig. 5 C is the interface of protocol interface device, the circuit theory diagrams of optical-electrical converter.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
The present invention is a kind of control system of transmitting based on the audio frequency and video of Optical Fiber Transmission, and it receives distributor, optical-electrical converter and protocol interface device by center processor, collector, signal and forms.The required power supply of control system of the present invention is provided by conventional power supply, and its output voltage has+1.2V ,+1.8V ,+2.5V ,+3.3V ,+5V ,+12V.
Described collector is used to receive the audio-video signal of audio-video device output, and described audio-video signal is carried out analog digital conversion back export digital audio-video signal f 0Give center processor; Described collector is the SAA7114 chip of Philips company;
Described center processor is used for (a) and realizes digital audio-video signal f 0Buffer memory, (b) realize the audio frequency and video format configuration signal h of described collector 0Transmission, (c) the inquiry audio ﹠ video equipment type signal g after realizing merging 2Response and (d) realize that described signal receives the configuration of the operational mode of distributor; Described center processor comprises dsp processor, FPGA programmable gate array and program storage, dsp processor is the TMS320C6713 chip of Texas Instruments, the FPGA programmable gate array is the EP1K100QC208 chip, and program storage is the MBM29LV800 chip;
Described signal receives distributor, is used for the audio-video signal f after (a) realization is handled 1Distribution, (b) realize agreement inquiry audio ﹠ video equipment type of electrical signal g 1Fusion; Described signal receives distributor and comprises physical chip, link layer chip, and physical chip is the TSB81BA3 chip of Texas Instruments, and the link layer chip is the TSB12LV32 chip of Texas Instruments;
Described optical-electrical converter is used for (a) and realizes protocol audio-video photosignal f 3Electric light conversion, (b) realize agreement inquiry audio ﹠ video equipment type light signal g 0Opto-electronic conversion; Described optical-electrical converter is the HFBR-53D5 optical module;
Described protocol interface device is used for (a) and realizes protocol audio-video light signal f 4Opto-electronic conversion, and the output high bandwidth (audio-video signal of 100M～1.25G), high-resolution (the audio frequency and video transmission meets Moving Picture Experts Group-2) realizes the electric light conversion of inquiry audio ﹠ video equipment type of electrical signal for watch-dog, (b).Described protocol interface device comprises physical chip, link layer chip, and physical chip is the TSB81BA3 chip of Texas Instruments, and the link layer chip is the TSB82AA2 chip of Texas Instruments;
Electronic information between the electronic chip that will adopt the present invention connects and is elaborated below:
(1) center processor
In the present invention, center processor is made up of dsp chip (model TMS320C6713), fpga chip, memory chip.
The power input 5,9,25,44,47,55,58,65,72,84,87,98,107,114,126,141,162,183,188,206 of dsp processor U8 connects+the 3.3V power supply;
The power input 3,11,14,22,29,35,40,43,46,50,51,53,60,67,80,89,96,104,105,116,124,133,149,157,169,171,177,190,195,196,201,208 of dsp processor U8 connects+the 1.2V power supply;
Ground input 4,10,15,23,26,30,34,39,45,48,49,52,54,59,66,73,81,85,88,97,106,115,125,134,142,148,158,163,170,182,189,194,199,203,207 ground connection of dsp processor U8;
20 (EA2-EA21) address output ends of dsp processor U8 connect with address 45,25,24,23,22,21,20,19,18,8,7,6,5,4,3,2,1,48,17,16 ends of program storage U7 respectively; Its 5 (EA2-EA6) address output ends connect respectively on 5 I/O pins of fpga chip U20; Its 7 (EA2-EA8) address output ends connect with address 17,18,19,21,22,23,24 ends that signal receives the link layer chip U3 of distributor respectively;
8 (ED0-ED7) data input/output terminals of dsp processor U8 connect with data 29,31,33,35,38,40,42,44 ends of program storage U7 respectively; And 8 (ED0-ED7) data input/output terminal connects respectively on 8 I/O pins of fpga chip U20; And 8 (ED0-ED7) data input/output terminal connects with data 81,82,83,84,86,87,88,89 ends that signal receives the link layer chip U3 of distributor respectively; The power supply of program storage U7 is imported 37 terminations+3.3V power supply, and input 27,46 end ground connection in ground are connected to capacitor C 26 between+3.3V power supply and the ground, and the byte double word is selected to be connected to resistance R 59 between input 47 ends and the ground; Gating 26 ends of program storage U7 connect with space gating 103 ends of dsp processor U8, write and enable 11 ends and connect with write gate 83 ends of dsp processor U8, output enable 28 ends connect with output gating 75 ends of dsp processor U8, and 12 ends that reset connect with the reset terminal 176 of dsp processor U8;
Memory space gating 102,61,57 ends of dsp processor U8 connect respectively on 3 I/O pins of fpga chip U20, and the 4th external interrupt 1 end, write gate 83 ends, read gate 79 ends, output gating 75 ends, 176 ends that reset connect respectively on 5 I/O pins of fpga chip U20;
The 4th external interrupt of dsp processor U8 imported 1 end and met power supply+3.3V by a resistance R 49; General input and output 2,6,7,173 ends meet power supply+3.3V by resistance R 48, resistance R 50, resistance R 53, resistance R 43 respectively; Multichannel buffer serial port external clock reference is imported 8 ends and is met power supply+3.3V by resistance R 54; Asynchronous storage is prepared input 56 ends and is met power supply+3.3V by resistance R 60; The exterior storage interface clock is imported 78 ends and is exported 82 ends with clock 2 frequency divisions of DSP and connect; Exterior storage interface bus arbitration input 138 ends meet power supply+3.3V by resistance R 55; The analog high-pass clock is exported 159 ends and is met power supply+3.3V by resistance R 45; General input and output 172 end ground connection; Non-shielding is interrupted input 175 ends by resistance R 47 ground connection; Input 176 ends that reset meet power supply+3.3V by resistance R 42; Clock is imported the clock of 204 ends connection crystal oscillator U25 and is exported 3 ends; Clock generator input clock source selects input 205 ends to meet power supply+3.3V by resistance R 44;
Among the fpga chip U20 required power supply be+2.5V and+3.3V, the ground input is conventional ground connection; 116 ends are imported 7 ends with the gating of the link layer chip U3 of signal reception distributor and are connected, and 140 ends connect with read/write gating 8 ends; 160 ends of fpga chip U20 are effectively exported 46 ends with the image mouth dateout of collector U5 and are connected, 163 ends are exported 45 ends with image mouth clock and are connected, 169 ends connect with I2C interface data 32 ends, 170 ends are exported 31 ends with the I2C interface clock and are connected, 172 ends connect with 36 ends of control output in real time, 173 ends are exported 28 ends with the wire lock system clock and are connected, 174 ends are exported 53 ends with many purposes horizontal reference and are connected, 175 ends are exported 52 ends with many purposes vertical reference and are connected, 176 ends connect with general output signal 0 output 49 ends, 177 ends connect with general output signal 1 output 48 ends, 189,190,187,191,192,193,195,196 ends export 62 with image mouth data respectively, 61,60,59,57,56,55,54 ends connect, and 197,198,199,179,200,202,203,205 ends export 72 with image mouth color signal data respectively, 71,70,69,67,66,65,64 ends connect; Clock is imported the clock of 98 ends connection crystal oscillating circuit U24 and is exported 3 ends.
(2) collector
In the present invention, the power supply of collector U5 input 1,8,11,17,23,25,33,43,51,58,68,75,83,93 terminations+3.3V power supply;
Ground input 5,9,15,21,24,26,38,50,63,76,88, the 100 end ground connection of collector U5;
The gating of collector U5 is imported 27 ends and is connect+3.3V by resistance R 87;
The real-time control of collector U5 is exported 36 ends by resistance R 86 ground connection;
The image mouth target of collector U5 is ready to import 42 ends and connects+3.3V by resistance R 83;
Image mouth output control signal 47 ends of collector U5 connect+3.3V by resistance R 85;
The simulation test of collector U5 is exported 22 ends and is connected by 2 ends that resistance R 77 exports simulation output interface J2 to;
Crystal oscillator input 6, the 7 termination crystal oscillating circuits of collector U5;
The left and right acoustic channels audio frequency of collector U5 is exported 40 ends by resistance R 76 ground connection;
Analog input 10,12,14,16,13, the 18 end ground connection of collector U5;
Analog input 20 ends of collector U5 connect with 2 ends of analog input interface J1 by capacitor C 180, resistance R 84, are connected to resistance R 82 between 2 ends of analog input interface J1 and the ground;
Analog input 19 ends of collector U5 are by capacitor C 181 ground connection;
(3) signal receives distributor
In the present invention, signal reception distributor comprises TSB81BA3 physical chip U2, TSB12LV32 link layer chip U3, protocol interface chip P1, SN74CBT3125D bus switch U12, HFBR-53D5 opto-electronic conversion chip U13.
The power supply input 10,15,20,35,40,47,68,71,80,85 of link layer chip U3,95 terminations+3.3V;
Ground input 5,25,30,45,57,73,78,90, the 100 end ground connection of link layer chip U3;
The mode of operation of link layer chip U3 is selected input 12 end ground connection;
The big small end model selection of link layer chip U3 is imported 75 ends and is connect+3.3V by resistance R 7;
The microcontroller interface data-transmission mode of link layer chip U3 selects input 11 ends to connect+3.3V by resistance R 8;
The micro controller transfer of data bit wide of link layer chip selects input 13 ends to connect+3.3V by resistance R 4;
The microcontroller interface model selection of link layer chip is imported 14 ends and is connect+3.3V by resistance R 5;
The physics of link layer chip-LI(link interface) data input and output 67,66,63,62,61,60,59,58 ends connect with physics-LI(link interface) data input and output 11,12,13,15,16,17,19,20 ends that signal receives the physical chip U2 of distributor respectively;
The link layer of link layer chip wakes link layer wake-up signal that input 64 ends and signal receive the physical chip U2 of distributor up and exports 2 ends and connect, and 2 ends pass through resistance R 25 ground connection;
The link layer power supply status of link layer chip is exported 53 ends and is imported 80 ends with the link layer power supply status of physical chip U2 and connect, and 80 ends are by resistance R 26 ground connection;
The physical layer request signal of link layer chip is exported 74 ends and is imported 3 ends with the physical layer request signal of physical chip U2 and connect;
The system clock of link layer chip is imported 72 ends and is exported 5 ends by resistance R 31 with the link layer clock of physical chip U2 and connect;
The physics of link layer chip-LI(link interface) control signal 70,69 ends connect with physics-LI(link interface) control signal 9,10 ends of physical chip U2 respectively;
The race condition of link layer chip is selected 65 end ground connection;
The circulation clock of link layer chip is imported 76 ends and is connect+3.3V by resistance R 2;
The test pattern of link layer chip is imported 16 end ground connection;
The data of link layer chip move a mouthful ready signal and import 77 ends and connect+3.3V by resistance R 22;
The data of link layer chip move mouthful output clock 46 ends by resistance R 6 ground connection;
9 ends that reset of link layer chip connect with 176 ends that reset of dsp processor U8;
The clock of link layer chip is imported 6 ends and is exported 77 ends with the clock of dsp processor U8 and connect.
The power supply input 6,18,24,31,39,44,51,57,63,69 of physical chip U2,70 terminations+3.3V;
The power supply input 8,29,30,37,65 of physical chip, 71 terminations+1.8V;
Ground input 4,14,21,25,28,38,40,43,50,61,62,64,72, the 76 end ground connection of physical chip;
75 ends that reset of physical chip are by capacitor C 3 ground connection;
77 end ground connection are imported in the power down of physical chip;
The electric source modes of physical chip selects to be connected between 66 ends and the ground resistance R 17, electric source modes select 67 ends and+be connected to resistance R 18 between the 3.3V power supply, electric source modes select 68 ends and+be connected to resistance R 19 between the 3.3V power supply;
Current arrangements 22,23 ends of physical chip link to each other by resistance R 27;
Test control input 78 ends of physical chip connect+3.3V by resistance R 20;
Reservation 26 ends of physical chip are by resistance R 3 ground connection;
The crystal oscillator of physical chip is imported 27 termination crystal oscillating circuits, simultaneously by resistance R 30 ground connection;
The link layer clock of physical chip is imported 7 ends by resistance R 24 ground connection;
Test control input 73 ends of physical chip connect+3.3V by resistance R 21;
Test control input 35, the 36 end ground connection of physical chip;
The cable power supply status of physical chip is imported 34 ends and is connect+12V by resistance R 32;
The data strobe model selection of physical chip is imported 32 ends and is connect+3.3V by resistance R 23, and 33 end ground connection are imported in the data strobe model selection;
74 end ground connection are imported in the Beta model selection of physical chip;
Port 0 data output 42,41 ends of physical chip connect data output 8,7 ends of optical-electrical converter U13 respectively by capacitor C 12, capacitor C 14; The power supply input 5 of optical-electrical converter U13,6 terminations+5V, ground input 1,9 end ground connection;
Port 0 data input 46,45 ends of agreement physical chip connect data output 3,6 ends of bus switch U 12 respectively; The power supply of bus switch U12 is imported 14 terminations+5V, and 7 end ground connection are imported on ground; Data input 2,5 ends of bus switch U12 are connected data input 2,3 ends of optical-electrical converter U13 respectively with matched impedance by capacitor C 15, capacitor C 16; 1,4 ends that enable of bus switch U12 pass through output 7 ends that resistance R 83 connects level transferring chip U14;
Port 0 bias voltage of physical chip is exported 47 ends and is connected with impedance matching network, and impedance matching network resistance R 13 imports 45 ends with data and connect, and resistance R 14 is imported 46 ends with data and connected;
Port one data output 48, the 49 end ground connection of physical chip;
The port one bias voltage of physical chip is exported 54 ends by capacitor C 19 ground connection;
Port 2 data output 56,55 ends of physical chip connect with impedance matching network, and port 2 data output 56,55 ends connect with 2,1 end of protocol interface P1 respectively; Port 2 data input 59,58 ends connect with impedance matching network, and port 2 data input 59,58 ends connect with 4,3 ends of protocol interface P1 respectively;
The port 2 bias voltage outputs 60 of physical chip are by data input 59,58 ends of impedance matching network connection port 2;
Acquisition of signal 4 ends of optical-electrical converter U13 connect the data of level transferring chip U14 and import 2 ends, and data are imported 2 ends by resistance R 82 ground connection; The differential data of level transferring chip U14 is imported 3 ends connection reference voltage and is exported 4 ends, and by capacitor C 202 ground connection; The power supply of level transferring chip U14 is imported 8 terminations+5V, and 5 end ground connection are imported on ground;
The power supply of protocol interface P1 is imported 8 terminations+12V, ground input 6,9,10,11,12,13 end ground connection; The input signal of protocol interface P1 passes through capacitor C 1, capacitor C 7 and resistance R 28 ground connection with reference to ground 5 ends.
(4) protocol interface device
In the present invention, the protocol interface device comprises pci bus, interface chip and optical-electrical converter, because of the pci bus slot is 64 of standards, so do not provide accompanying drawing.Interface chip is made up of TSB81BA3 physical chip U9 and TSB82AA2 link layer chip U6 again, protocol interface chip P2, SN74CBT3125D bus switch U22, HFBR-53D5 opto-electronic conversion chip U23.
The power supply input 8,15,31,42,62,75,86,102,126,135 of link layer chip U6,139 terminations+3.3V;
Ground input 9,22,32,43,52,63,76,81,93,103,112,122,127,137, the 140 end ground connection of link layer chip U6;
64 bit address of link layer chip/data/address bus input/output terminal is connected on the pci bus respectively, 4 pci bus signals are clamped down on voltage 21,55,91,117 ends, 8 pci bus orders and byte enable end are connected in respectively on the pci bus, and clock is imported 10 ends, gating 45 ends, PCI cycle frame input and output 40 ends, the pci bus approval signal is imported 12 ends, the pci bus initialization apparatus is selected input 28 ends, pci bus interrupt signal output 5 ends, initial ready signal input and output 41 ends, pci bus parity check 49,80 ends, pci bus parity error 47 ends, pci bus is waken 14 ends up, 13 ends are exported in the pci bus request, 48 ends are exported in the pci bus system mistake, pci bus circulation stop signal input and output 46 ends, target is ready to input and output 44 ends, 64 corresponding input 72 ends of transmission of pci bus, 64 request inputs of pci bus, 73 ends, pci bus 6 ends that reset connect the respective end of pci bus respectively;
1.8 V bypass resistance 16,87 ends of link layer chip U6 pass through capacitor C 147, capacitor C 148 ground connection of a 0.1uF respectively;
Multi-functional selection 1 end of link layer chip meets 3.3V by a 4.7K resistance R 145;
The resistance R 144 of 7 ends that reset by a 43K of link layer chip connects+3.3V, simultaneously capacitor C 146 ground connection by a 1uF;
The normalizer of link layer chip U6 enables resistance R 146 ground connection of 2 ends by one 220 Europe;
I2C bus interface 3,4 ends of link layer chip U6 connect I2C interface 6,5 ends of memory EEPROM (AT24C02) chip U6-1 respectively, and I2C interface 6,5 ends of memory connect+3.3V by resistance R 142, resistance R 143 respectively; The power supply of memory is imported 8 terminations+3.3V, and 4 end ground connection are imported on ground, address choice 1,2,3 end ground connection, and write-protect 7 ends connect+3.3V by the resistance R 141 of a 1K, connect 1 end of wire jumper JP1 simultaneously;
8 physics of link layer chip U6-LI(link interface) data input and output 132,131,130,129,128,125,124,123 ends connect 8 physics-LI(link interface) data input and output 11 of the physical chip U9 of protocol interface device respectively, 12,13,15,16,17,19,20 ends, link layer wakes input 142 ends connection link layer wake-up signal up and exports 2 ends, simultaneously by 1K resistance R 125 ground connection, the link layer power supply status is exported 144 ends connection link layer power supply status and is imported 80 ends, simultaneously by 1K resistance R 126 ground connection, the physical layer request signal is exported 141 ends connection physical layer request signal and is imported 3 ends, system clock is imported 138 ends and is exported 5 ends by one 22 Europe resistance R 131 connection link layer clocks, the link layer clock is exported 136 ends connection link layer clock and is imported 7 ends, physical layer is interrupted input 143 ends and is connected physical layer interruption output 1 end, physics-LI(link interface) control signal 134,133 ends connect physics-LI(link interface) control signal 9 respectively, 10 ends;
The power supply input 6,18,24,31,39,44,51,57,63,69 of physical chip U9,70 terminations+3.3V;
The power supply input 8,29,30,37,65 of physical chip, 71 terminations+1.8V;
Ground input 4,14,21,25,28,38,40,43,50,61,62,64,72, the 76 end ground connection of physical chip;
75 ends that reset of physical chip are by capacitor C 213 ground connection;
77 end ground connection are imported in the power down of physical chip;
The electric source modes of physical chip selects to be connected between 66 ends and the ground resistance R 117, electric source modes select 67 ends and+be connected to resistance R 118 between the 3.3V power supply, electric source modes select 68 ends and+be connected to resistance R 119 between the 3.3V power supply;
Current arrangements 22,23 ends of physical chip link to each other by resistance R 127;
Test control input 78 ends of physical chip connect+3.3V by resistance R 120;
Reservation 26 ends of physical chip are by resistance R 103 ground connection;
The crystal oscillator of physical chip is imported 27 termination crystal oscillating circuits, simultaneously by resistance R 130 ground connection;
Test control input 73 ends of physical chip connect+3.3V by resistance R 121;
Test control input 35, the 36 end ground connection of physical chip;
The cable power supply status of physical chip is imported 34 ends and is connect+12V by resistance R 132;
The data strobe model selection of physical chip is imported 32 ends and is connect+3.3V by resistance R 123, and 33 end ground connection are imported in the data strobe model selection;
74 end ground connection are imported in the Beta model selection of physical chip;
Port 0 data output 42,41 ends of physical chip connect data output 8,7 ends of optical-electrical converter U23 respectively by capacitor C 222, capacitor C 224; The power supply input 5 of optical-electrical converter U23,6 terminations+5V, ground input 1,9 end ground connection;
Port 0 data input 46,45 ends of physical chip connect data output 3,6 ends of bus switch U22 respectively; The power supply of bus switch U22 is imported 14 terminations+5V, and 7 end ground connection are imported on ground; Data input 2,5 ends of bus switch U22 are connected data input 2,3 ends of optical-electrical converter U23 respectively with matched impedance by capacitor C 15, capacitor C 16; 1,4 ends that enable of bus switch U22 pass through output 7 ends that resistance R 183 connects level transferring chip U24;
Port 0 bias voltage of physical chip is exported 47 ends and is connected with impedance matching network, and impedance matching network resistance R 113 imports 45 ends with data and connect, and resistance R 114 is imported 46 ends with data and connected;
Port one data output 48, the 49 end ground connection of physical chip;
The port one bias voltage of physical chip is exported 54 ends by capacitor C 229 ground connection;
Port 2 data output 56,55 ends of physical chip connect with impedance matching network, and port 2 data output 56,55 ends connect with 2,1 end of protocol interface P2 respectively; Port 2 data input 59,58 ends connect with impedance matching network, and port 2 data input 59,58 ends connect with 4,3 ends of protocol interface P2 respectively;
Port 2 bias voltages of physical chip are exported data input 59,58 ends of 60 ends by impedance matching network connection port 2;
Acquisition of signal 4 ends of optical-electrical converter U23 connect the data of level transferring chip U11 and import 2 ends, and data are imported 2 ends by resistance R 182 ground connection; The differential data of level transferring chip U11 is imported 3 ends connection reference voltage and is exported 4 ends, and by capacitor C 242 ground connection; The power supply of level transferring chip U11 is imported 8 terminations+5V, and 5 end ground connection are imported on ground;
The power supply of protocol interface P2 is imported 8 terminations+12V, ground input 6,9,10,11,12,13 end ground connection; The input signal of protocol interface P2 passes through capacitor C 211, capacitor C 217 and resistance R 128 ground connection with reference to ground 5 ends.
It is to introduce aiding system for driving to provide the foundation that the present invention adopts distributed network.Application requirements is realized the distributed control of motor component in real time, and distributed network is distributed to computing capability in the node that needs.Cheap and powerful microcontroller is bought easily and is made the application of distributed network become possibility.Setting up reliable distribution type fiber-optic link is to realize that Optical Fiber Transmission substitutes the prerequisite of copper cash transmission.Fiber optic network Boeing 777 in successful Application show that optical fiber is not fragile can not be used for abominable operating environment.

Claims (3)

1, a kind of control system of transmitting based on the audio frequency and video of Optical Fiber Transmission is characterized in that: receives distributor, optical-electrical converter and protocol interface device by center processor, collector, signal and forms,
Described collector is used to receive the audio-video signal of audio-video device output, and described audio-video signal is carried out analog digital conversion back export digital audio-video signal f 0Give center processor;
Described center processor is used for (a) and realizes digital audio-video signal f 0Buffer memory, (b) realize the audio frequency and video format configuration signal h of described collector 0Transmission, (c) the inquiry audio ﹠ video equipment type signal g after realizing merging 2Response and (d) realize that described signal receives the configuration of the operational mode of distributor; Described center processor comprises dsp processor, FPGA programmable gate array and program storage;
Described signal receives distributor, is used for the audio-video signal f after (a) realization is handled 1Distribution, (b) realize agreement inquiry audio ﹠ video equipment type of electrical signal g 1Fusion; Described signal receives distributor and comprises physical chip, link layer chip;
Described optical-electrical converter is used for (a) and realizes protocol audio-video photosignal f 3Electric light conversion, (b) realize agreement inquiry audio ﹠ video equipment type light signal g 0Opto-electronic conversion;
Described protocol interface device is used for (a) and realizes protocol audio-video light signal f 4Opto-electronic conversion, and the output audio-video signal realizes the electric light conversion of inquiry audio ﹠ video equipment type of electrical signal for watch-dog, (b); Described protocol interface device comprises physical chip, link layer chip.
2, the control system of audio frequency and video transmission according to claim 1, it is characterized in that: described collector is chosen the SAA7114 chip, dsp processor is chosen the TMS320C6713 chip, the FPGA programmable gate array is chosen the EP1K100QC208 chip, program storage is chosen the MBM29LV800 chip, the physical layer of signal reception distributor is chosen the TSB81BA3 chip, link layer is chosen the TSB12LV32 chip, and the physical layer of protocol interface device is chosen the TSB81BA3 chip, link layer is chosen the TSB82AA2 chip.
3, the control system of audio frequency and video according to claim 1 transmission is characterized in that: the connection of electronic information is,
The power input 5,9,25,44,47,55,58,65,72,84,87,98,107,114,126,141,162,183,188,206 of dsp processor U8 connects+the 3.3V power supply;
The power input 3,11,14,22,29,35,40,43,46,50,51,53,60,67,80,89,96,104,105,116,124,133,149,157,169,171,177,190,195,196,201,208 of dsp processor U8 connects+the 1.2V power supply;
Ground input 4,10,15,23,26,30,34,39,45,48,49,52,54,59,66,73,81,85,88,97,106,115,125,134,142,148,158,163,170,182,189,194,199,203,207 ground connection of dsp processor U8;
The EA2-EA21 address output end of dsp processor U8 connects with address 45,25,24,23,22,21,20,19,18,8,7,6,5,4,3,2,1,48,17,16 ends of program storage U7 respectively; Its EA2-EA6 address output end connects respectively on 5 I/O pins of fpga chip U20; Its EA2-EA8 address output end connects with address 17,18,19,21,22,23,24 ends that signal receives the link layer chip U3 of distributor respectively;
The ED0-ED7 data input/output terminal of dsp processor U8 connects with data 29,31,33,35,38,40,42,44 ends of program storage U7 respectively; And ED0-ED7 data input/output terminal connects respectively on 8 I/O pins of fpga chip U20; And ED0-ED7 data input/output terminal connects with data 81,82,83,84,86,87,88,89 ends that signal receives the link layer chip U3 of distributor respectively; The power supply of program storage U7 is imported 37 terminations+3.3V power supply, and input 27,46 end ground connection in ground are connected to capacitor C 26 between+3.3V power supply and the ground, and the byte double word is selected to be connected to resistance R 59 between input 47 ends and the ground; Gating 26 ends of program storage U7 connect with space gating 103 ends of dsp processor U8, write and enable 11 ends and connect with write gate 83 ends of dsp processor U8, output enable 28 ends connect with output gating 75 ends of dsp processor U8, and 12 ends that reset connect with the reset terminal 176 of dsp processor U8;
Memory space gating 102,61,57 ends of dsp processor U8 connect respectively on 3 I/O pins of fpga chip U20, and the 4th external interrupt 1 end, write gate 83 ends, read gate 79 ends, output gating 75 ends, 176 ends that reset connect respectively on 5 I/O pins of fpga chip U20A;
The 4th external interrupt of dsp processor U8 imported 1 end and met power supply+3.3V by a resistance R 49; General input and output 2,6,7,173 ends meet power supply+3.3V by resistance R 48, resistance R 50, resistance R 53, resistance R 43 respectively; Multichannel buffer serial port external clock reference is imported 8 ends and is met power supply+3.3V by resistance R 54; Asynchronous storage is prepared input 56 ends and is met power supply+3.3V by resistance R 60; The exterior storage interface clock is imported 78 ends and is exported 82 ends with clock 2 frequency divisions of DSP and connect; Exterior storage interface bus arbitration input 138 ends meet power supply+3.3V by resistance R 55; The analog high-pass clock is exported 159 ends and is met power supply+3.3V by resistance R 45; General input and output 172 end ground connection; Non-shielding is interrupted input 175 ends by resistance R 47 ground connection; Input 176 ends that reset meet power supply+3.3V by resistance R 42; Clock is imported the clock of 204 ends connection crystal oscillator U25 and is exported 3 ends; Clock generator input clock source selects input 205 ends to meet power supply+3.3V by resistance R 44;
Among the fpga chip U20 required power supply be+2.5V and+3.3V, the ground input is conventional ground connection; 116 ends are imported 7 ends with the gating of the link layer chip U3 of signal reception distributor and are connected, and 140 ends connect with read/write gating 8 ends; 160 ends of fpga chip U20 are effectively exported 46 ends with the image mouth dateout of collector U5 and are connected, 163 ends are exported 45 ends with image mouth clock and are connected, 169 ends connect with I2C interface data 32 ends, 170 ends are exported 31 ends with the I2C interface clock and are connected, 172 ends connect with 36 ends of control output in real time, 173 ends are exported 28 ends with the wire lock system clock and are connected, 174 ends are exported 53 ends with many purposes horizontal reference and are connected, 175 ends are exported 52 ends with many purposes vertical reference and are connected, 176 ends connect with general output signal 0 output 49 ends, 177 ends connect with general output signal 1 output 48 ends, 189,190,187,191,192,193,195,196 ends export 62 with image mouth data respectively, 61,60,59,57,56,55,54 ends connect, and 197,198,199,179,200,202,203,205 ends export 72 with image mouth color signal data respectively, 71,70,69,67,66,65,64 ends connect; Clock is imported the clock of 98 ends connection crystal oscillating circuit U24 and is exported 3 ends;
The power supply input 1,8,11,17,23,25,33,43,51,58,68,75,83 of collector U5,93 terminations+3.3V power supply;
Ground input 5,9,15,21,24,26,38,50,63,76,88, the 100 end ground connection of collector U5;
The gating of collector U5 is imported 27 ends and is connect+3.3V by resistance R 87;
The real-time control of collector U5 is exported 36 ends by resistance R 86 ground connection;
The image mouth target of collector U5 is ready to import 42 ends and connects+3.3V by resistance R 83;
Image mouth output control signal 47 ends of collector U5 connect+3.3V by resistance R 85;
The simulation test of collector U5 is exported 22 ends and is connected by 2 ends that resistance R 77 exports simulation output interface J2 to;
Crystal oscillator input 6, the 7 termination crystal oscillating circuits of collector U5;
The left and right acoustic channels audio frequency of collector U5 is exported 40 ends by resistance R 76 ground connection;
Analog input 10,12,14,16,13, the 18 end ground connection of collector U5;
Analog input 20 ends of collector U5 connect with 2 ends of analog input interface J1 by capacitor C 180, resistance R 84, are connected to resistance R 82 between 2 ends of analog input interface J1 and the ground;
Analog input 19 ends of collector U5 are by capacitor C 181 ground connection;
Signal receives power supply input 10,15,20,35,40,47,68,71,80,85,95 terminations+3.3V of the link layer chip U3 of distributor;
Ground input 5,25,30,45,57,73,78,90, the 100 end ground connection of link layer chip U3;
The mode of operation of link layer chip U3 is selected input 12 end ground connection;
The big small end model selection of link layer chip U3 is imported 75 ends and is connect+3.3V by resistance R 7;
The microcontroller interface data-transmission mode of link layer chip U3 selects input 11 ends to connect+3.3V by resistance R 8;
The micro controller transfer of data bit wide of link layer chip selects input 13 ends to connect+3.3V by resistance R 4;
The microcontroller interface model selection of link layer chip is imported 14 ends and is connect+3.3V by resistance R 5;
The physics of link layer chip-LI(link interface) data input and output 67,66,63,62,61,60,59,58 ends connect with physics-LI(link interface) data input and output 11,12,13,15,16,17,19,20 ends that signal receives the physical chip U2 of distributor respectively;
The link layer of link layer chip wakes link layer wake-up signal that input 64 ends and signal receive the physical chip U2 of distributor up and exports 2 ends and connect, and 2 ends pass through resistance R 25 ground connection;
The link layer power supply status of link layer chip is exported 53 ends and is imported 80 ends with the link layer power supply status of physical chip U2 and connect, and 80 ends are by resistance R 26 ground connection;
The physical layer request signal of link layer chip is exported 74 ends and is imported 3 ends with the physical layer request signal of physical chip U2 and connect;
The system clock of link layer chip is imported 72 ends and is exported 5 ends by resistance R 31 with the link layer clock of physical chip U2 and connect;
The physics of link layer chip-LI(link interface) control signal 70,69 ends connect with physics-LI(link interface) control signal 9,10 ends of physical chip U2 respectively;
The race condition of link layer chip is selected 65 end ground connection;
The circulation clock of link layer chip is imported 76 ends and is connect+3.3V by resistance R 2;
The test pattern of link layer chip is imported 16 end ground connection;
The data of link layer chip move a mouthful ready signal and import 77 ends and connect+3.3V by resistance R 22;
The data of link layer chip move mouthful output clock 46 ends by resistance R 6 ground connection;
9 ends that reset of link layer chip connect with 176 ends that reset of dsp processor U8;
The clock of link layer chip is imported 6 ends and is exported 77 ends with the clock of dsp processor U8 and connect.
The power supply input 6,18,24,31,39,44,51,57,63,69 of physical chip U2,70 terminations+3.3V;
The power supply input 8,29,30,37,65 of physical chip, 71 terminations+1.8V;
Ground input 4,14,21,25,28,38,40,43,50,61,62,64,72, the 76 end ground connection of physical chip;
75 ends that reset of physical chip are by capacitor C 3 ground connection;
77 end ground connection are imported in the power down of physical chip;
The electric source modes of physical chip selects to be connected between 66 ends and the ground resistance R 17, electric source modes select 67 ends and+be connected to resistance R 18 between the 3.3V power supply, electric source modes select 68 ends and+be connected to resistance R 19 between the 3.3V power supply;
Current arrangements 22,23 ends of physical chip link to each other by resistance R 27;
Test control input 78 ends of physical chip connect+3.3V by resistance R 20;
Reservation 26 ends of physical chip are by resistance R 3 ground connection;
The crystal oscillator of physical chip is imported 27 termination crystal oscillating circuits, simultaneously by resistance R 30 ground connection;
The link layer clock of physical chip is imported 7 ends by resistance R 24 ground connection;
Test control input 73 ends of physical chip connect+3.3V by resistance R 21;
Test control input 35, the 36 end ground connection of physical chip;
The cable power supply status of physical chip is imported 34 ends and is connect+12V by resistance R 32;
The data strobe model selection of physical chip is imported 32 ends and is connect+3.3V by resistance R 23, and 33 end ground connection are imported in the data strobe model selection;
74 end ground connection are imported in the Beta model selection of physical chip;
Port 0 data output 42,41 ends of physical chip connect data output 8,7 ends of optical-electrical converter U13 respectively by capacitor C 12, capacitor C 14; The power supply input 5 of optical-electrical converter U13,6 terminations+5V, ground input 1,9 end ground connection;
Port 0 data input 46,45 ends of agreement physical chip connect data output 3,6 ends of bus switch U12 respectively; The power supply of bus switch U12 is imported 14 terminations+5V, and 7 end ground connection are imported on ground; Data input 2,5 ends of bus switch U12 are connected data input 2,3 ends of optical-electrical converter U13 respectively with matched impedance by capacitor C 15, capacitor C 16; 1,4 ends that enable of bus switch U12 pass through output 7 ends that resistance R 83 connects level transferring chip U14;
Port 0 bias voltage of physical chip is exported 47 ends and is connected with impedance matching network, and impedance matching network resistance R 13 imports 45 ends with data and connect, and resistance R 14 is imported 46 ends with data and connected;
Port one data output 48, the 49 end ground connection of physical chip;
The port one bias voltage of physical chip is exported 54 ends by capacitor C 19 ground connection;
Port 2 data output 56,55 ends of physical chip connect with impedance matching network, and port 2 data output 56,55 ends connect with 2,1 end of protocol interface P1 respectively; Port 2 data input 59,58 ends connect with impedance matching network, and port 2 data input 59,58 ends connect with 4,3 ends of protocol interface P1 respectively;
The port 2 bias voltage outputs 60 of physical chip are by data input 59,58 ends of impedance matching network connection port 2;
Acquisition of signal 4 ends of optical-electrical converter U13 connect the data of level transferring chip U14 and import 2 ends, and data are imported 2 ends by resistance R 82 ground connection; The differential data of level transferring chip U14 is imported 3 ends connection reference voltage and is exported 4 ends, and by capacitor C 202 ground connection; The power supply of level transferring chip U14 is imported 8 terminations+5V, and 5 end ground connection are imported on ground;
The power supply of protocol interface P1 is imported 8 terminations+12V, ground input 6,9,10,11,12,13 end ground connection; The input signal of protocol interface P1 passes through capacitor C 1, capacitor C 7 and resistance R 28 ground connection with reference to ground 5 ends;
The power supply input 8,15,31,42,62,75,86,102,126,135 of the link layer chip U6 of protocol interface device, 139 terminations+3.3V;
Ground input 9,22,32,43,52,63,76,81,93,103,112,122,127,137, the 140 end ground connection of link layer chip U6;
64 bit address of link layer chip/data/address bus input/output terminal is connected on the pci bus respectively, 4 pci bus signals are clamped down on voltage 21,55,91,117 ends, 8 pci bus orders and byte enable end are connected in respectively on the pci bus, and clock is imported 10 ends, gating 45 ends, PCI cycle frame input and output 40 ends, the pci bus approval signal is imported 12 ends, the pci bus initialization apparatus is selected input 28 ends, pci bus interrupt signal output 5 ends, initial ready signal input and output 41 ends, pci bus parity check 49,80 ends, pci bus parity error 47 ends, pci bus is waken 14 ends up, 13 ends are exported in the pci bus request, 48 ends are exported in the pci bus system mistake, pci bus circulation stop signal input and output 46 ends, target is ready to input and output 44 ends, 64 corresponding input 72 ends of transmission of pci bus, 64 request inputs of pci bus, 73 ends, pci bus 6 ends that reset connect the respective end of pci bus respectively;
1.8V bypass resistance 16,87 ends of link layer chip U6 pass through capacitor C 147, capacitor C 148 ground connection of a 0.1uF respectively;
Multi-functional selection 1 end of link layer chip meets 3.3V by a 4.7K resistance R 145;
The resistance R 144 of 7 ends that reset by a 43K of link layer chip connects+3.3V, simultaneously capacitor C 146 ground connection by a 1uF;
The normalizer of link layer chip U6 enables resistance R 146 ground connection of 2 ends by one 220 Europe;
I2C bus interface 3,4 ends of link layer chip U6 connect I2C interface 6,5 ends of memory EEPROM (AT24C02) chip U6-1 respectively, and I2C interface 6,5 ends of memory connect+3.3V by resistance R 142, resistance R 143 respectively; The power supply of memory is imported 8 terminations+3.3V, and 4 end ground connection are imported on ground, address choice 1,2,3 end ground connection, and write-protect 7 ends connect+3.3V by the resistance R 141 of a 1K, connect 1 end of wire jumper JP1 simultaneously;
8 physics of link layer chip U6-LI(link interface) data input and output 132,131,130,129,128,125,124,123 ends connect 8 physics-LI(link interface) data input and output 11 of the physical chip U9 of protocol interface device respectively, 12,13,15,16,17,19,20 ends, link layer wakes input 142 ends connection link layer wake-up signal up and exports 2 ends, simultaneously by 1K resistance R 125 ground connection, the link layer power supply status is exported 144 ends connection link layer power supply status and is imported 80 ends, simultaneously by 1K resistance R 126 ground connection, the physical layer request signal is exported 141 ends connection physical layer request signal and is imported 3 ends, system clock is imported 138 ends and is exported 5 ends by one 22 Europe resistance R 131 connection link layer clocks, the link layer clock is exported 136 ends connection link layer clock and is imported 7 ends, physical layer is interrupted input 143 ends and is connected physical layer interruption output 1 end, physics-LI(link interface) control signal 134,133 ends connect physics-LI(link interface) control signal 9 respectively, 10 ends;
The power supply input 6,18,24,31,39,44,51,57,63,69 of physical chip U9,70 terminations+3.3V;
The power supply input 8,29,30,37,65 of physical chip, 71 terminations+1.8V;
Ground input 4,14,21,25,28,38,40,43,50,61,62,64,72, the 76 end ground connection of physical chip;
75 ends that reset of physical chip are by capacitor C 213 ground connection;
77 end ground connection are imported in the power down of physical chip;
The electric source modes of physical chip selects to be connected between 66 ends and the ground resistance R 117, electric source modes select 67 ends and+be connected to resistance R 118 between the 3.3V power supply, electric source modes select 68 ends and+be connected to resistance R 119 between the 3.3V power supply;
Current arrangements 22,23 ends of physical chip link to each other by resistance R 127;
Test control input 78 ends of physical chip connect+3.3V by resistance R 120;
Reservation 26 ends of physical chip are by resistance R 103 ground connection;
The crystal oscillator of physical chip is imported 27 termination crystal oscillating circuits, simultaneously by resistance R 130 ground connection;
Test control input 73 ends of physical chip connect+3.3V by resistance R 121;
Test control input 35, the 36 end ground connection of physical chip;
The cable power supply status of physical chip is imported 34 ends and is connect+12V by resistance R 132;
The data strobe model selection of physical chip is imported 32 ends and is connect+3.3V by resistance R 123, and 33 end ground connection are imported in the data strobe model selection;
74 end ground connection are imported in the Beta model selection of physical chip;
Port 0 data output 42,41 ends of physical chip connect data output 8,7 ends of optical-electrical converter U23 respectively by capacitor C 222, capacitor C 224; The power supply input 5 of optical-electrical converter U23,6 terminations+5V, ground input 1,9 end ground connection;
Port 0 data input 46,45 ends of physical chip connect data output 3,6 ends of bus switch U22 respectively; The power supply of bus switch U22 is imported 14 terminations+5V, and 7 end ground connection are imported on ground; Data input 2,5 ends of bus switch U22 are connected data input 2,3 ends of optical-electrical converter U23 respectively with matched impedance by capacitor C 15, capacitor C 16; 1,4 ends that enable of bus switch U22 pass through output 7 ends that resistance R 183 connects level transferring chip U24;
Port 0 bias voltage of physical chip is exported 47 ends and is connected with impedance matching network, and impedance matching network resistance R 113 imports 45 ends with data and connect, and resistance R 114 is imported 46 ends with data and connected;
Port one data output 48, the 49 end ground connection of physical chip;
The port one bias voltage of physical chip is exported 54 ends by capacitor C 229 ground connection;
Port 2 data output 56,55 ends of physical chip connect with impedance matching network, and port 2 data output 56,55 ends connect with 2,1 end of protocol interface P2 respectively; Port 2 data input 59,58 ends connect with impedance matching network, and port 2 data input 59,58 ends connect with 4,3 ends of protocol interface P2 respectively;
Port 2 bias voltages of physical chip are exported data input 59,58 ends of 60 ends by impedance matching network connection port 2;
Acquisition of signal 4 ends of optical-electrical converter U23 connect the data of level transferring chip U11 and import 2 ends, and data are imported 2 ends by resistance R 182 ground connection; The differential data of level transferring chip U11 is imported 3 ends connection reference voltage and is exported 4 ends, and by capacitor C 242 ground connection; The power supply of level transferring chip U11 is imported 8 terminations+5V, and 5 end ground connection are imported on ground;
The power supply of protocol interface P2 is imported 8 terminations+12V, ground input 6,9,10,11,12,13 end ground connection; The input signal of protocol interface P2 passes through capacitor C 211, capacitor C 217 and resistance R 128 ground connection with reference to ground 5 ends.
CNB2006101134441A 2006-09-28 2006-09-28 Control system of audio-video transmission based on optical fibre transmission Expired - Fee Related CN100461857C (en)

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CN103259600A (en) * 2013-05-20 2013-08-21 国家电网公司 Voice communication interface device for debugging stable control system
CN106656333A (en) * 2016-11-17 2017-05-10 合肥铭锶伟途信息科技有限公司 Fiber-based embedded real-time image exchange processing system
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US20030101458A1 (en) * 2001-11-25 2003-05-29 Jacobson Stephen Robert Audio/video distribution system
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CN102567280A (en) * 2010-12-17 2012-07-11 西安奇维测控科技有限公司 Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array)
CN102567280B (en) * 2010-12-17 2015-01-21 西安奇维科技股份有限公司 Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array)
CN103259600A (en) * 2013-05-20 2013-08-21 国家电网公司 Voice communication interface device for debugging stable control system
CN106656333A (en) * 2016-11-17 2017-05-10 合肥铭锶伟途信息科技有限公司 Fiber-based embedded real-time image exchange processing system
CN110413042A (en) * 2019-07-30 2019-11-05 上海东土远景工业科技有限公司 A kind of clock server, punctual frequency compensation method and device
CN110413042B (en) * 2019-07-30 2020-08-14 上海东土远景工业科技有限公司 Clock server, and time keeping frequency compensation method and device
CN116193057A (en) * 2023-04-26 2023-05-30 广东视腾电子科技有限公司 Multi-port transmission optical fiber video extension method and system

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