CN111679995B - Embedded management execution unit of space computer based on 1553B bus - Google Patents
Embedded management execution unit of space computer based on 1553B bus Download PDFInfo
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- CN111679995B CN111679995B CN202010567433.0A CN202010567433A CN111679995B CN 111679995 B CN111679995 B CN 111679995B CN 202010567433 A CN202010567433 A CN 202010567433A CN 111679995 B CN111679995 B CN 111679995B
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
The invention discloses a 1553B bus-based embedded management execution unit of a space computer, which comprises a processor, a FLASH memory, a 1553B bus processor and a 1553B bus transceiver, wherein the processor is provided with an analog quantity acquisition channel, a DA output channel and a command sending channel; the 1553B bus processor is connected with the 1553B bus transceiver through a serial bus; a first level shifter is arranged between the 1553B bus processor and the processor; the instruction sending channel is realized through an instruction driver, and the instruction driver is connected with the processor through a data bus; the 1553B bus processor is used for protocol conversion of a 1553B bus, and the 1553B bus transceiver is used for transceiving drive of the 1553B bus; the module integrated processor minimum system, the 1553B bus controller, the analog quantity acquisition and instruction output interface are standard designs applied to space computers in the field of large satellites, can be used as a core processing module, and can be matched with interface circuits at the periphery to form a complete space computer, so that the design period and the design cost are reduced.
Description
Technical Field
The invention belongs to the field of application of space embedded computers, and particularly relates to a 1553B bus-based embedded management execution unit of a space computer.
Background
Miniaturization is a development trend of a space embedded computer, and a processor system and a functional module in the computer are built by adopting discrete devices at present, so that the computer is large in size, heavy in weight and high in cost. The development and application of the SIP technology provide technical support for the miniaturization design of the space embedded computer. The embedded execution management unit LSMEU01, the instruction execution unit LMSIU64 and the like which are applied and fly successfully on the space computer at present enable the size, the weight, the power consumption and the like of the computer to be greatly reduced, and the SIP module works stably, is good in performance and mature in technology.
The current space embedded computer system level communication bus forms mainly include two types: 1553B bus and CAN bus, and the instruction interface forms are also two: an OC (Open Collector) instruction interface and an OE (Open Emitter) instruction interface. The currently applied LSMEU01 module of the embedded execution management unit is based on a CAN bus and an OC instruction output interface, cannot meet the requirements of 1553B bus and OE instruction interface forms, CAN be realized only by externally expanding a 1553B bus protocol chip and an OE instruction interface chip, CAN increase the volume and weight of the embedded execution management unit, cannot embody the advantage of miniaturization of an SIP module, and limits the application and popularization of the embedded execution management unit to a certain extent.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a 1553B bus-based embedded management execution unit for a space computer, wherein an integrated minimum processor system, a 1553B bus controller, an analog quantity acquisition and instruction output interface are standard designs applied in the space computer in the field of big satellites, the requirements of 1553B bus and OE instruction interface forms are met, and the design standardization, miniaturization and localization requirements of the space computer can be met.
In order to achieve the purpose, the technical scheme adopted by the invention is that a 1553B bus-based embedded management execution unit of a space computer comprises a processor, a FLASH memory, a 1553B bus processor and a 1553B bus transceiver, wherein the processor is provided with an analog quantity acquisition channel, an analog loop channel, a DA output channel and a command sending channel; the 1553B bus processor is connected with the 1553B bus transceiver through a serial bus; a first level shifter is arranged between the 1553B bus processor and the processor; the 1553B bus processor is connected with the first level shifter through a data bus and an address bus, and the FLASH memory is connected with the processor through the address bus, the data bus and a control bus; the instruction sending channel is realized through an instruction driver, the instruction driver is used for OE instruction output, and the instruction driver is connected with the processor through a data bus;
the 1553B bus processor is used for protocol conversion of a 1553B bus, and the 1553B bus transceiver is used for transceiving drive of the 1553B bus.
A second level shifter and a latch are arranged between the instruction driver and the processor, the second level shifter is connected with the processor through an address bus, a data bus and a control bus, the latch is connected with the second level shifter through the control bus, and the instruction driver and the latch are connected through the control bus.
The command driver 20 routes the output with the command.
The analog quantity acquisition channel is realized by a first analog switch, a first operational amplifier and a third level converter, the third level converter is respectively connected with the first analog switch and the processor by a control bus, and the analog quantity selectively output by the first analog switch is processed by the first operational amplifier and then is sent to the processor;
the analog loop channel is realized by a second analog switch, a second operational amplifier and a fourth level converter, the fourth level converter is connected with the second analog switch and the processor by a control bus, and analog quantity selectively output by the second analog switch is processed by the second operational amplifier and then is sent to the processor;
the first analog switch and the second analog switch are used for selecting an input analog quantity channel, and the first operational amplifier and the second operational amplifier are used for carrying out follow-up amplification on the input analog quantity after the analog quantity channel is selected.
The ratio of the analog quantity acquisition channel to the analog return line channel is 4: 1.
The FLASH memory is in bidirectional data transmission with the processor, and the processor allocates addresses to the FLASH memory and sends control instructions to the FLASH memory.
Level shifters are used for internal 3.3V and 5V level signal conversion.
The processor is also connected with a decoder through an address bus, and the decoder is used for outputting chip selection.
The processor is also provided with four paths of DA outputs, four paths of UART full duplex interfaces, one path of external interrupt, one path of SPI bus, a JTAG debugging interface, three paths of PWM, three paths of timer interfaces, eight paths of GPIO interfaces and a power supply interface.
Compared with the prior art, the invention has at least the following beneficial effects:
the 1553B bus is one of main buses of a space embedded computer in the field of large satellites, the application of OE instructions is gradually and widely applied, the invention integrates the 1553B bus and the OE instruction function with a processor system to form an embedded management execution unit under the condition of not changing the size of the existing module, integrates a standardized design circuit for acquiring and controlling the terminal information of the space computer into a package by adopting a high-integration SIP technology, and embeds the standardized design circuit into a control management computer or each load terminal device,
the module-integrated minimum processor system, the 1553B bus controller, the analog quantity acquisition and instruction output interface are standard designs applied in space computers in the field of large satellites, can be used as a core processing module, and can form a complete space computer by matching interface circuits at the periphery, so that the design period and the design cost are reduced.
Drawings
Fig. 1 is a schematic block diagram of an embedded management execution unit SIP module.
Fig. 2 is a CPU board of a space computer based on an SIP module of an embedded management execution unit according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, an embedded management execution unit of a space computer based on a 1553B bus comprises a processor 1, wherein the processor 1 is used for controlling other functional circuits to work, and external interfaces of the processor 1 comprise four paths of DA outputs, four paths of UART full duplex interfaces, eight paths of GPIO interfaces, one path of external interrupts, one path of SPI buses, a JTAG debugging interface, three paths of PWM, three paths of timer interfaces, a power interface, one path of external interrupts and a clock input; the analog switch 2 is used for selecting an analog quantity channel input by the module, and the ratio of the analog quantity channel to a return line is 4: 1; the level shifter 3 is used for the level signal conversion of 3.3V and 5V inside the module; the operational amplifier 4 is used for follow-up amplification after analog quantity channel selection; the FLASH memory 5 serves as a program memory of the processor; the level shifter 3 includes a first level shifter 31, a second level shifter 32, a third level shifter 33, and a fourth level shifter 34; the operational amplifier 4 includes a first operational amplifier 41 and a second operational amplifier 42, and the analog switch 2 includes a first analog switch 21 and a second analog switch 22.
The 1553B bus processor 6 is used for protocol conversion of a 1553B bus; the 1553B bus transceiver 7 is used for transceiving drive of a 1553B bus.
The latch 8 is used for data latching; the instruction driver 9 is used for OE instruction output; the decoder 10 is used for outputting chip selection externally.
The first level shifter 31 is connected with the 1553B bus processor 6 through a data bus and a control bus; the 1553B bus processor 6 is connected with the 1553B bus transceiver 7 through a serial bus,
the second level shifter 32 is connected to the latch 8 via a control bus, the latch 8 is connected to the command driver 9 via a control bus, the command driver 9 is connected to the processor 1 via a data bus,
the third level shifter 33 is connected with the processor through a data bus, and the third level shifter 33 is connected with the first analog switch 21 through the data bus; the analog quantity selectively output by the first analog switch 21 is processed by the first operational amplifier 41 and then sent to the processor 1;
the fourth level shifter 34 is connected with the processor through a data bus, and the fourth level shifter 34 is connected with the second analog switch 22 through the data bus; the second analog switch 22 is connected with the second operational amplifier 42 through a control bus, and analog quantity selectively output by the second analog switch 22 is processed by the second operational amplifier 42 and then is sent to the processor 1;
the FLASH memory 5 is connected with the processor 1 through an address bus, a data bus and a control bus, the FLASH memory 5 is in bidirectional data transmission with the processor 1, and the processor 1 allocates addresses to the FLASH memory 5 and sends control instructions to the FLASH memory 5.
The invention provides a 1553B bus-based embedded management execution unit of a space computer, which takes a processor as a core, and comprises an external expansion program memory, a data memory, a 1553B bus, a Universal Asynchronous Receiver Transmitter (UART), an analog quantity acquisition channel, a DA output channel and an instruction sending channel; as shown in fig. 1, the technical indexes are as follows:
(1) kernel: a processor 1; model number LC801E
(2) A program memory: 64KB FLASH can be used for externally expanding PROM;
(3) a data memory: 32KB, external SRAM;
(4) bus: 1553B bus, and 2 paths of dual redundancy of 1553_ A and 1553_ B bus are designed;
(5) UART 4-path full duplex, with 256B receiving FIFO and transmitting FIFO;
(6) analog quantity acquisition channel: 32 paths of ADC with the acquisition range of 0-5V and 12 bits;
(7) the DA outputs 4 paths of 11-bit DACs;
(8) an instruction sending channel: 20-way emission follow;
(9) packaging form and size: PGA192 high-temperature ceramic housing;
(10) the external dimension is as follows: 46mm by 10.6 mm;
the embodiment of the invention provides a space computer CPU board taking an embedded management execution unit based on a 1553B bus as a processor, the design block diagram is shown in figure 2, the space computer CPU board of the embedded management execution unit based on the 1553B bus adopts a main machine and a cold standby machine, the main machine and the standby machine are completely consistent in design and comprise an SIP module 11, a crystal oscillator 12, a watchdog and reset circuit 13, a tertiary power supply conversion chip 14, an address line and chip selection driver 15, a data line driver 16, a transformer 17, connectors 18, 1553B connectors 19 and an inter-board connector 20, the SIP module 11 is used as a processing core to carry out information interaction and protocol analysis with other single machines through the 1553B bus, the crystal oscillator 12 is used for providing a clock necessary for the work of an internal processor of the SIP module 11 and a 1553B controller, the watchdog and reset circuit 13 is used for a power-on reset of the whole board circuit and a watchdog circuit of the processor, an external power supply is accessed through the tertiary power conversion chip 14, and the tertiary power conversion chip 14 is used for the tertiary power supply of the board; the inter-board plug connector 20 is used for connecting external equipment and a CPU board, a JTAG debugging interface is connected with the outside through a plug connector 18, a transformer 17 is arranged between a 1553B plug connector 19 and the SIP module 11, the SIP module 11 outputs an address selection instruction and a chip selection instruction to the outside through an address line and a chip selection driver 15, and the SIP module 11 and a data line driver 16 realize bidirectional data communication with the outside. The third power conversion chip 14 is used for providing 5V, 3.3V and 1.8V power of the CPU board.
The embodiments of the present invention are merely illustrative of the spirit of the present invention, and those skilled in the art can modify the described embodiments or substitute them with similar ones without departing from the spirit of the present invention.
Claims (8)
1. A1553B bus-based embedded management execution unit of a space computer is characterized by comprising a processor (1), a FLASH memory (5), a 1553B bus processor (6) and a 1553B bus transceiver (7), wherein the processor (1) is provided with an analog quantity acquisition channel, an analog loop channel, a DA output channel and a command sending channel; the 1553B bus processor (6) is connected with the 1553B bus transceiver (7) through a serial bus; a first level shifter (31) is arranged between the 1553B bus processor (6) and the processor (1); the 1553B bus processor (6) is connected with the first level shifter (31) through a data bus and an address bus, and the FLASH memory (5) is connected with the processor (1) through the address bus, the data bus and a control bus; the instruction sending channel is realized through an instruction driver (9), the instruction driver (9) is used for OE instruction output, and the instruction driver (9) is connected with the processor (1) through a data bus;
the 1553B bus processor (6) is used for protocol conversion of a 1553B bus, and the 1553B bus transceiver (7) is used for transceiving drive of the 1553B bus; the analog quantity acquisition channel is realized by a first analog switch (21), a first operational amplifier (41) and a third level shifter (33), the third level shifter (33) is respectively connected with the first analog switch (21) and the processor (1) through a control bus, and the analog quantity selectively output by the first analog switch (21) is processed by the first operational amplifier (41) and then is sent to the processor (1);
the analog loop channel is realized by a second analog switch (22), a second operational amplifier (42) and a fourth level shifter (34), the fourth level shifter (34) is connected with the second analog switch (22) and the processor (1) through a control bus, and analog quantity selectively output by the second analog switch (22) is processed by the second operational amplifier (42) and then is sent to the processor (1);
the first analog switch (21) and the second analog switch (22) are used for selecting an input analog quantity channel, and the first operational amplifier (41) and the second operational amplifier (42) are used for carrying out follow-up amplification on an input analog quantity after the analog quantity channel is selected.
2. A 1553B-bus-based spatial computer embedded management execution unit according to claim 1, characterized in that a second level shifter (32) and a latch (8) are arranged between the instruction driver (9) and the processor (1), the second level shifter (32) is connected with the processor (1) through an address bus, a data bus and a control bus, the latch (8) is connected with the second level shifter (32) through the control bus, and the instruction driver (9) is connected with the latch (8) through the control bus.
3. A 1553B-bus-based space computer embedded management execution unit (emcu) according to claim 1, characterized by that, the command driver (9) sets 20 routes the output with the command.
4. The spatial computer embedded management execution unit based on 1553B bus as claimed in claim 1, wherein the ratio of analog acquisition channel to analog loop channel is 4: 1.
5. A 1553B-bus-based space computer embedded management execution unit according to claim 1, characterized in that, the FLASH memory (5) and the processor (1) are in bidirectional data transmission, the processor (1) assigns addresses to the FLASH memory (5) and issues control commands to the FLASH memory (5).
6. A 1553B bus based spatial computer embedded management execution unit, according to claim 1, characterized by that, level shifters are used for internal 3.3V and 5V level signal conversion.
7. The spatial computer embedded management execution unit based on 1553B bus as claimed in claim 1, wherein the processor (1) is further connected with a decoder (10) through an address bus, and the decoder (10) is used for outputting the chip selection to the outside.
8. The embedded management execution unit of a space computer based on 1553B bus as claimed in claim 1, wherein the processor (1) is further provided with four DA outputs, four UART full duplex interfaces, one external interrupt, one SPI bus, JTAG debug interface, three PWM, three timer interfaces, eight GPIO interfaces and power interface.
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