CN101706762A - Intelligent type signal transfer system - Google Patents
Intelligent type signal transfer system Download PDFInfo
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- CN101706762A CN101706762A CN200910241564A CN200910241564A CN101706762A CN 101706762 A CN101706762 A CN 101706762A CN 200910241564 A CN200910241564 A CN 200910241564A CN 200910241564 A CN200910241564 A CN 200910241564A CN 101706762 A CN101706762 A CN 101706762A
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Abstract
The invention provides an intelligent type signal transfer system. The intelligent type signal transfer system consists of two main parts: an operating system and an embedding type detection system. The operating system is formed by an operating panel, and a user can complete corresponding on-line operations on the operating panel according to signal transfer relations and various needs; and the embedding type detection system is formed by an ARM+FPGA embedding type system, wherein the ARM serving as a CPU(central processing unit) is a main control chip of the system, the FPGA has rich I/O(input/output)resources and is suitably used as a peripheral circuit of the CPU, and the ARM and the FPGA exchange data by an SPI(Serial Peripheral Interface) bus. The intelligent type signal transfer system is characterized by large amount of transfer signal, simplicity and practicability, low cost, strong generality and the like, thoroughly solves the problems of difficult wiring and detection existing in the automatic detection equipment and various units to be detected, and is widely applied to a large-scaled automatic detection system. In the technical field of signal transfer-class devices, the intelligent type signal transfer system has a use value and a wide application prospect.
Description
Technical field:
The present invention relates to a kind of intelligent type signal transfer system, it is relevant with embedded system development technology, hardware system detection technique and software testing technology, belongs to signal converting class device technique field.
Background technology:
Along with science and technology development, automatic test equipment (ATE) in utilizations such as military affairs, Aero-Space and industrial sectors more and more widely, yet because the unit under test kind is a lot, often an ATE (automatic test equipment) will be tested hundreds of even several thousand kinds of unit under tests, and this is with regard to the problem adaptive between ATE that standard occurred and the unit under test, that wiring is difficult.
Aspect the research of intelligent type signal transfer system, still belong to blank at present both at home and abroad, market does not have formation system, and existing Related product, as the switch matrix integrated circuit board, maximum-norm is 8 * 32, system testing many, the wiring complicated situation of counting for ATE, and it is counted and can't meet the demands far away, and mostly be imported product greatly, price is expensive, and the cost height can't large tracts of land be promoted the use of.
Summary of the invention:
1, purpose: the purpose of this invention is to provide a kind of intelligent type signal transfer system, it has overcome the deficiencies in the prior art, have big, simple and practical, the characteristics such as cost is low, highly versatile of tandem signal quantity size, it will thoroughly solve ATE (automatic test equipment) and various unit under test wiring, test difficult problem, be widely used in the extensive Auto-Test System.The concrete effect of this intelligent type signal transfer system is a signal converting of realizing ATE (automatic test equipment) and various tested target machine.This intelligent type signal transfer system is mainly finished following function:
1) signal converting that the ATE (automatic test equipment) submodule is exported is to the interface of the submodule of target machine requirement;
2) signal converting that the target machine submodule is exported is to the suitable measurement channel interface of ATE (automatic test equipment) submodule;
3) system provides necessary testing circuit, and total system is carried out self check, state demonstration etc. to built-up circuit before starting test, guarantees that the signal converting relation works on power after accurate.
2, technical scheme:
As shown in Figure 2, a kind of intelligent type signal transfer system of the present invention, it is made up of operating system and embedded detection system two large divisions.
Described operating system is to be made of guidance panel, and the user can finish the respective gut operation according to signal converting relation and various needs on guidance panel.
Described embedded detection system is by ARM+FPGA (ARM-Advanced RISC Machines, the common name of a class microprocessor; FPGA-Field Programmable Gate Array, field programmable gate array) embedded system constitutes, ARM is as CPU (central processing unit), it is the main control chip of system, and FPGA has abundant I/O (input and output) resource, be suitable for use as the peripheral circuit of CPU, carry out data interaction by SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) bus between the two.
This ARM central processing unit, adopt the LPC2148 (ARM chip model) of PHILIPS (Philip) company, it is 32 ARM7 microcontrollers supporting real-time simulation and embedded tracking, have high speed FLASH (flash) storer that 32KB and 512KB embed, the memory interface of 128 bit widths and unique accelerating structure, 32 codes can be moved under maximum clock speed, and have spi bus; Select for use this processor mainly to consider the aboundresources that it is inner, need not extended memory and spi bus, and excellent performance, antijamming capability is strong, and is cheap, has high performance price ratio.
This FPGA adopts the mainstream chip Cyclone EP1C6Q240C8 (fpga chip model) of Altera (A Ertela) company; There is the logical resource that is equivalent to more than 100,000 this FPGA inside, 5980 logical blocks, 20 M4K pieces (256 * 18bit), can be used to generate on-chip memory, as RAM (Random Access Memory, random access memory), ROM (ReadOnlyMemory, ROM (read-only memory)), dual port RAM and FIFO (FirstInFirstOut, first-in first-out register) etc.; Two analog phase-locked looks that inside is integrated can be used for the clock of input is carried out frequency multiplication and phase shift, and maximum available I/O is 185.
More than two chips be low cost, low-power consumption chip, need not consider the heat dissipation problem of chip.
Because ARM directly affects the performance of controller with intercoming mutually of FPGA, the design of its spi bus communication just becomes a very crucial problem.
SPI is a kind of high speed, full duplex, synchronous communication bus, and on the pin of chip, only take four lines, saved the pin of chip, simultaneously on the layout of circuit board, save the space, provide convenience, just for this characteristic that is simple and easy to usefulness, this communication protocol that the communication between ARM and the FPGA is integrated.SPI is a ring bus structure, constitute by ss (cs) (slave selection wire), sck (serial time clock line), sdi (main frame output slave incoming line), sdo (main frame input slave output line), its sequential is simple, mainly be under the control of sck, two bidirectional shift registers carry out exchanges data.
ARM is as central processing unit, external power supply module, program load-on module, expansion RS-232 (serial binary data exchange interface technical standard between data terminal equipment (DTE) and the data communications equipment (DCE)) serial line interface, the main control computer testing software is attached thereto by serial ports, carries out control operation.ARM sheet stored module is made up of SRAM (static RAM (SRAM)) and NOR type FLASH (a kind of typical non-volatile FLASH), SRAM is as the internal memory of ARM, deposit the dynamic data of ARM at working procedure, FLASH storage ARM program and some constant parameter, content is not lost after the power down.Carry out data communication by spi bus ARM and FPGA.
FPGA regards the high-speed peripheral of ARM as, and EP1C6Q240C8 constitutes by multi-disc, and it mainly comprises data output and load module.Testing software sends enabling signal, through RS232 serial ports input ARM, ARM produces source data, issue FPGA by spi bus, by the I/O mouth output of output module, source data drives each the line path of operating system of flowing through through chip for driving, generate target data by chip for driving, the FPGA load module reads in target data by each chip for driving input of scanning, by spi bus input ARM.ARM handles, resolves target data, and the line relation of decision operation system by serial ports, sends to testing software with the line relation data that generates, and shows testing result on the main control computer screen.
System has made full use of the very high speed logic processing power of FPGA large-scale data amount signal is exported and imported, and it is sent among the ARM to be for data processing again, has improved the real-time of controller.
The online programming interface of ARM and fpga chip is directly connected to whether operate as normal of entire controller, and the design of this interface must be guaranteed errorless.The ARM microprocessor the detail programming interface adopt JTAG (Joint Test Action Group, a kind of international standard test protocol) debugging interface meet IEEE1149.1-1990 (IEEE, U.S. electric and electronics engineers) standard.
Configuration mode for fpga chip, can FPGA be configured by the I/O pin of ARM, this method can be omitted the FPGA configuring chip but also reduce some costs simultaneously, strengthened the coupling between FPGA and the ARM, in case but some pin damage of ARM chip will cause FPGA to dispose, cisco unity malfunction, thereby reduced system reliability, therefore system adopts AS pattern (Active SerialConfiguration, the active series arrangement) the EPIC6Q240C8 type FPGA of configuration Cyclone series, this pattern selects for use EPCS4 type Altera FPGA configuring chip by ByteBlasterII (model) download cable FPGA to be configured, but repeated configuration 100,000 times.This mode circuit is simple, easy to use, with low cost, is highly suitable for industry spot and uses.
(3) software flow
1) embedded detection system software
As shown in Figure 4, after embedded detection system receives the enabling signal of main control computer testing software by serial ports, at first carry out the initialization setting, start then, send the detection resources data from detecting.Source traffic is made of string number signal " 1 ", node one end input from corresponding each module of ATE (automatic test equipment), transfer to node one end of corresponding target machine by the respective gut of operating system, this moment, FPGA carried out scan round to each node of target machine, there is the passage of line to receive signal " 1 ", and the channel signal that does not have line hold mode " 0 " still, FPGA receives this target data, send to ARM by spi bus, carry out data processing, resolve, with valid data---promptly there are the data of line relation to generate relation data by communication protocol, send to the main control computer testing software by 232 serial ports, data are further handled by testing software.
2) main control computer testing software:
As shown in Figure 5, the main control computer testing software finishes: the serial ports configuration, to embedded detection system transmitting control commands, handle, show by communication protocol receiving the relation data of uploading, and measured line relation data spanned file is preserved several big functions from serial ports.
3, advantage and effect:
This invention changes the traditional operation mode during ATE (automatic test equipment) is used for a long time based on advanced person's ARM and the exploitation of FPGA embedded system technology, is a kind of novel solution prioritization scheme of field of automatic testing.It uses simple, convenient, especially possesses the function of High-Speed Automatic detection, and whether the decision signal switching is accurate, wrongly then warns the user, and avoiding pitfalls brings about great losses, and has improved user's work efficiency greatly, saves cost of labor.
Its outstanding advantage imbody is in the following areas:
(1) contact scale super large
Can satisfy 650 I/O independent contacts (shown in the following tabulation 1), 400 output/input independent contacts (shown in the following tabulation 2), and reusable satisfy ultra-large several signal converting.
Table 1 ATE (automatic test equipment) signaling module interface
Table 2 target machine inserts the Signal Switching System module
(2) highly versatile
System is extensive use of in Geste2.1 (general-purpose built-in type STE system is developed jointly by new space networks computing machine Ltd of BJ University of Aeronautics ﹠ Astronautics and Beijing) test now.Its standard interface is for ATE (automatic test equipment) general (as above tabulating shown in 1) now, and for tested target machine general (as above tabulating shown in 2).If any special, change the joint model of tie conductor before only needing to use.
(3) simple to operate
As long as on the operating system panel, simply plug the line operation, simplified operations such as original loaded down with trivial details bonding wire, line.
(4) human oriented design
System height is moderate, and the user can select station/seat type operation voluntarily
Description of drawings:
Fig. 1 intelligent type signal transfer system synoptic diagram
Fig. 2 intelligent type signal transfer system work system is formed synoptic diagram
Fig. 3 intelligent type signal transfer system hardware configuration synoptic diagram
Fig. 4 detection system software flow synoptic diagram
Fig. 5 main control computer testing software functional block diagram
Symbol description is as follows among the figure:
Fig. 1 (1) signalling channel 1～m1; (2) signalling channel 1～m2; (n) signalling channel 1～mn
Fig. 2 (1) system line; (2) p-wire; (3) pilot wire
Embodiment:
See Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, a kind of intelligent type signal transfer system of the present invention, its concrete effect is a signal converting of realizing ATE (automatic test equipment) and various tested target machine, and as shown in Figure 1, it is made up of operating system and embedded detection system two large divisions.
Described operating system is to be made of guidance panel, and the user can finish the respective gut operation according to signal converting relation and various needs on guidance panel.ATE (automatic test equipment) is connected with guidance panel by the corresponding interface, and is as shown in table 1; And tested target machine also is attached thereto by the corresponding interface, as above tabulates shown in 2.
Described embedded detection system, be to constitute by the ARM+FPGA embedded system, ARM is a central processing unit as CPU, it is the main control chip of system, and FPGA has abundant I/O is the input and output resources, be suitable for use as the peripheral circuit of CPU, carry out data interaction by SPI (Serial Peripheral Interface) bus between the two.
This ARM central processing unit, adopt the LPC2148 of PHILIPS company, it is 32 ARM7 microcontrollers supporting real-time simulation and embedded tracking, have the high speed FLASH storer that 32KB and 512KB embed, the memory interface of 128 bit widths and unique accelerating structure, 32 codes can be moved under maximum clock speed, and have spi bus; Select for use this processor mainly to consider the aboundresources that it is inner, need not extended memory and spi bus, and excellent performance, antijamming capability is strong, and is cheap, has high performance price ratio.
This FPGA adopts the mainstream chip Cyclone EP1C6Q240C8 of altera corp; There is the logical resource that is equivalent to more than 100,000 this FPGA inside, 5980 logical blocks, 20 M4K pieces (256 * 18bit), can be used to generate on-chip memory, as RAM, ROM, dual port RAM and FIFO etc.; Two analog phase-locked looks that inside is integrated can be used for the clock of input is carried out frequency multiplication and phase shift, and maximum available I/O is 185.
More than two chips be low cost, low-power consumption chip, need not consider the heat dissipation problem of chip.
Because ARM directly affects the performance of controller with intercoming mutually of FPGA, the design of its spi bus communication just becomes a very crucial problem.
SPI is a kind of high speed, full duplex, synchronous communication bus, and on the pin of chip, only take four lines, saved the pin of chip, simultaneously on the layout of circuit board, save the space, provide convenience, just for this characteristic that is simple and easy to usefulness, this communication protocol that the communication between ARM and the FPGA is integrated.SPI is a ring bus structure, constitute by ss (cs) (slave selection wire), sck (serial time clock line), sdi (main frame output slave incoming line), sdo (main frame input slave output line), its sequential is simple, mainly be under the control of sck, two bidirectional shift registers carry out exchanges data.
ARM is as central processing unit, external power supply module, program load-on module, expansion RS-232 serial line interface, the main control computer testing software is attached thereto by serial ports, carry out control operation .ARM sheet stored module and be made up of SRAM and NOR type FLASH, SRAM deposits the dynamic data of ARM at working procedure as the internal memory of ARM, FLASH storage ARM program and some constant parameter, content is not lost after the power down. carry out data communication by spi bus ARM and FPGA.
FPGA regards the high-speed peripheral of ARM as, and EP1C6Q240C8 constitutes by multi-disc, and it mainly comprises data output and load module.Testing software sends enabling signal, through RS232 serial ports input ARM, ARM produces source data, issue FPGA by spi bus, by the I/O mouth output of output module, source data drives each the line path of operating system of flowing through through chip for driving, generate target data by chip for driving, the FPGA load module reads in target data by each chip for driving input of scanning, by spi bus input ARM.ARM handles, resolves target data, and the line relation of decision operation system by serial ports, sends to testing software with the line relation data that generates, and shows testing result on the main control computer screen.
System has made full use of the very high speed logic processing power of FPGA large-scale data amount signal is exported and imported, and it is sent among the ARM to be for data processing again, has improved the real-time of controller.
The online programming interface of ARM and fpga chip is directly connected to whether operate as normal of entire controller, and the design of this interface must be guaranteed errorless.The ARM microprocessor the detail programming interface adopt the JTAG debugging interface meet the IEEE1149.1-1990 standard.
Configuration mode for fpga chip, can FPGA be configured by the I/O pin of ARM, this method can be omitted the FPGA configuring chip but also reduce some costs simultaneously, strengthened the coupling between FPGA and the ARM, in case but some pin damage of ARM chip will cause FPGA to dispose, cisco unity malfunction, thereby reduced system reliability, therefore system adopts the EPIC6Q240C8 type FPGA of AS pattern (Active SerialConfiguration) configuration Cyclone series, this pattern selects for use EPCS4 type Altera FPGA configuring chip by the ByteBlasterII download cable FPGA to be configured, but repeated configuration 100,000 times.This mode circuit is simple, easy to use, with low cost, is highly suitable for industry spot and uses.
(3) software flow
1) embedded detection system software
As shown in Figure 4, after embedded detection system receives the enabling signal of main control computer testing software by serial ports, at first carry out the initialization setting, start then, send the detection resources data from detecting.Source traffic is made of string number signal " 1 ", node one end input from corresponding each module of ATE (automatic test equipment), transfer to node one end of corresponding target machine by the respective gut of operating system, this moment, FPGA carried out scan round to each node of target machine, there is the passage of line to receive signal " 1 ", and the channel signal that does not have line hold mode " 0 " still, FPGA receives this target data, send to ARM by spi bus, carry out data processing, resolve, with valid data---promptly there are the data of line relation to generate relation data by communication protocol, send to the main control computer testing software by 232 serial ports, data are further handled by testing software.
2) main control computer testing software:
As shown in Figure 5, the main control computer testing software finishes: the serial ports configuration, to embedded detection system transmitting control commands, handle, show by communication protocol receiving the relation data of uploading, and measured line relation data spanned file is preserved several big functions from serial ports.
Claims (1)
1. intelligent type signal transfer system, it is characterized in that: it is made up of operating system and embedded detection system two large divisions;
Described operating system is to be made of guidance panel, and the user can finish the respective gut operation according to signal converting relation and various needs on guidance panel;
Described embedded detection system is to be made of ARM and FPGA embedded system, and ARM is a central processing unit as CPU, it is the main control chip of system, and FPGA has abundant I/O is the input and output resources, is suitable for use as the peripheral circuit of CPU, carries out data interaction by spi bus between the two;
This ARM central processing unit, adopt the LPC2148 of PHILIPS company, it is 32 ARM7 microcontrollers supporting real-time simulation and embedded tracking, have the high speed FLASH storer that 32KB and 512KB embed, the memory interface of 128 bit widths and unique accelerating structure, 32 codes can be moved under maximum clock speed, and have spi bus; SPI is a kind of high speed, full duplex, synchronous communication bus, it is a ring bus structure, constitute by slave selection wire, serial time clock line, main frame output slave incoming line and main frame input slave output line, its sequential is simple, at serial time clock line is under the control of sck, and two bidirectional shift registers carry out exchanges data; And on the pin of chip, only take four lines, this communication protocol that the communication between ARM and the FPGA is integrated; ARM is as central processing unit, and external power supply module, program load-on module are expanded the RS-232 serial line interface, and the main control computer testing software is attached thereto by serial ports, carries out control operation; ARM sheet stored module is made up of SRAM and NOR type FLASH, SRAM deposits the dynamic data of ARM at working procedure as the internal memory of ARM, FLASH storage ARM program and some constant parameter, content is not lost after the power down, carries out data communication by spi bus ARM and FPGA; This FPGA adopts the mainstream chip Cyclone EP1C6Q240C8 of altera corp; There is the logical resource that is equivalent to more than 100,000 this FPGA inside, 5980 logical blocks, and 20 M4K pieces are 256 * 18bit, with generating on-chip memory RAM, ROM, dual port RAM and FIFO; Two analog phase-locked looks that inside is integrated are used for the clock of input is carried out frequency multiplication and phase shift; FPGA regards the high-speed peripheral of ARM as, EP1C6Q240C8 constitutes by multi-disc, it comprises data output and load module, testing software sends enabling signal, through RS232 serial ports input ARM, ARM produces source data, issue FPGA by spi bus, I/O mouth output by output module, source data drives each the line path of operating system of flowing through through chip for driving, generates target data by chip for driving, and the FPGA load module is by each chip for driving input of scanning, target data is read in, by spi bus input ARM; ARM handles, resolves target data, and the line relation of decision operation system by serial ports, sends to testing software with the line relation data that generates, and shows testing result on the main control computer screen; The ARM microprocessor the detail programming interface adopt the JTAG debugging interface meet the IEEE1149.1-1990 standard; For the configuration mode of fpga chip, be that the I/O pin by ARM is configured FPGA, it is the EPIC6Q240C8 type FPGA of Active SerialConfiguration configuration Cyclone series that this system adopts the AS pattern.
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| CN101915877A (en) * | 2010-07-02 | 2010-12-15 | 北京航空航天大学 | Bus technology-based universal electromagnetic susceptibility testing device and method |
| CN102435890A (en) * | 2011-10-21 | 2012-05-02 | 上海凌世电子有限公司 | EMS test method and test device |
| CN102567197A (en) * | 2010-12-28 | 2012-07-11 | 北京旋极信息技术股份有限公司 | Simulation test method and device |
| CN103368802A (en) * | 2012-03-29 | 2013-10-23 | 罗伯特·博世有限公司 | Communication device and method for configuring programmable hardware |
| CN103531251A (en) * | 2013-10-29 | 2014-01-22 | 北京兆易创新科技股份有限公司 | Multi-chip packaging system |
| CN103995475A (en) * | 2014-05-16 | 2014-08-20 | 北京航空航天大学 | Flexible embedded type tested device simulator |
| CN104333486A (en) * | 2014-10-31 | 2015-02-04 | 大唐移动通信设备有限公司 | Testing system and method of network cell device |
| CN104954215A (en) * | 2015-07-29 | 2015-09-30 | 天津市英贝特航天科技有限公司 | CAN bus circuit |
| CN105551528A (en) * | 2015-12-10 | 2016-05-04 | 上海精密计量测试研究所 | Testing apparatus and method of high-speed large-capacity multi-chip Flash module based on ATE |
| CN106878100A (en) * | 2015-12-11 | 2017-06-20 | 全球能源互联网研究院 | A kind of method of testing and system of ellipse curve public key cipher security coprocessor |
| CN108196989A (en) * | 2017-12-13 | 2018-06-22 | 苏州长风航空电子有限公司 | A kind of universal debugging interface based on i.MX6 series processors platforms |
| CN114184935A (en) * | 2021-11-30 | 2022-03-15 | 上海御渡半导体科技有限公司 | ATE board card state display device and display method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101915877A (en) * | 2010-07-02 | 2010-12-15 | 北京航空航天大学 | Bus technology-based universal electromagnetic susceptibility testing device and method |
| CN102567197A (en) * | 2010-12-28 | 2012-07-11 | 北京旋极信息技术股份有限公司 | Simulation test method and device |
| CN102435890A (en) * | 2011-10-21 | 2012-05-02 | 上海凌世电子有限公司 | EMS test method and test device |
| CN103368802A (en) * | 2012-03-29 | 2013-10-23 | 罗伯特·博世有限公司 | Communication device and method for configuring programmable hardware |
| CN103531251B (en) * | 2013-10-29 | 2016-04-27 | 北京兆易创新科技股份有限公司 | A kind of multi-chip package system |
| CN103531251A (en) * | 2013-10-29 | 2014-01-22 | 北京兆易创新科技股份有限公司 | Multi-chip packaging system |
| CN103995475A (en) * | 2014-05-16 | 2014-08-20 | 北京航空航天大学 | Flexible embedded type tested device simulator |
| CN103995475B (en) * | 2014-05-16 | 2016-05-18 | 北京航空航天大学 | A kind of flexible embedded equipment under test simulator |
| CN104333486A (en) * | 2014-10-31 | 2015-02-04 | 大唐移动通信设备有限公司 | Testing system and method of network cell device |
| CN104333486B (en) * | 2014-10-31 | 2018-07-17 | 大唐移动通信设备有限公司 | A kind of network element device test system and method |
| CN104954215A (en) * | 2015-07-29 | 2015-09-30 | 天津市英贝特航天科技有限公司 | CAN bus circuit |
| CN105551528A (en) * | 2015-12-10 | 2016-05-04 | 上海精密计量测试研究所 | Testing apparatus and method of high-speed large-capacity multi-chip Flash module based on ATE |
| CN106878100A (en) * | 2015-12-11 | 2017-06-20 | 全球能源互联网研究院 | A kind of method of testing and system of ellipse curve public key cipher security coprocessor |
| CN108196989A (en) * | 2017-12-13 | 2018-06-22 | 苏州长风航空电子有限公司 | A kind of universal debugging interface based on i.MX6 series processors platforms |
| CN114184935A (en) * | 2021-11-30 | 2022-03-15 | 上海御渡半导体科技有限公司 | ATE board card state display device and display method |
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Application publication date: 20100512 |