CN202904427U - Clock tree generation circuit with multiple function modes - Google Patents
Clock tree generation circuit with multiple function modes Download PDFInfo
- Publication number
- CN202904427U CN202904427U CN 201220510573 CN201220510573U CN202904427U CN 202904427 U CN202904427 U CN 202904427U CN 201220510573 CN201220510573 CN 201220510573 CN 201220510573 U CN201220510573 U CN 201220510573U CN 202904427 U CN202904427 U CN 202904427U
- Authority
- CN
- China
- Prior art keywords
- circuit
- clock source
- clock
- clock tree
- selector switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The utility model relates to the field of electrons, and discloses a clock tree generation circuit with multiple function modes. The clock tree generation circuit comprises at least two independent clock sources corresponding to different function modes, a selector which is used for selecting the function modes and is connected with each independent clock source through a circuit, a uniform clock source connected with the selector, and a register connected with the uniform clock circuit through a circuit, wherein a clock tree is generated between the uniform clock source and the register; and a delay time sequence circuit does not exist on at least one of paths from the independent clock sources to the selector. A clock tree circuit is simplified, so that the aims of shortening the subsequent checking flow and reducing the convergence time length along with small chip area, low power consumption and the like are fulfilled; and locating and wiring are facilitated.
Description
Technical field
The utility model relates to electronic applications, particularly the generative circuit of Clock Tree.
Background technology
For the Clock Tree generative circuit of multifunctional mode, traditional design adopts and realizes clock tree circuit under each functional mode one time as shown in Figure 1, and generation from the independent clock source of the functional mode of correspondence.Because each functional mode will be at the first-born one-tenth Clock Tree of the independent clock source of difference, and clock source has logic overlapping to final register end separately, cause static timing convergence iterative times many, needed device is also many, to the path (such as S0, the S1 of Fig. 1) between the selector switch that is used for the selection mode of operation, have separately the delay sequential circuit such as each independent clock source, so the subsequent authentication flow process is long, has the waste chip area, the problems such as power consumption is large, and convergence time is long.
The utility model content
The purpose of this utility model is to provide a kind of Clock Tree generative circuit of multifunctional mode, so that the generation of clock tree circuit can be passed through less chip area, power consumption realizes, more is conducive to placement-and-routing, also shorten the subsequent authentication flow process, thereby reduced the convergence duration.
For solving the problems of the technologies described above, the utility model provides a kind of Clock Tree generative circuit of multifunctional mode, comprises:
The independent clock source of at least two corresponding difference in functionality patterns;
Be used for the selector switch of selection function pattern, described selector switch links to each other by circuit with each described independent clock source;
The unified clock source that links to each other with described selector switch;
With the register that described unified clock source links to each other by circuit, described Clock Tree is created between this unified clock source and this register;
Wherein,, to each path of described selector switch, have at least not have the delay sequential circuit on the paths at each described independent clock source.
The utility model embodiment in terms of existing technologies, generated clock tree from the unified clock source is about to produce a plurality of points of multifunctional mode Clock Tree, is merged into a point.Because each independent clock source is to unified clock tree source, on the shortest path without postponing sequential circuit, namely at each independent clock source to the most in short-term order path circuit in unified clock source, do not have the delay circuit of balance sequential.Therefore simplified clock tree circuit, thereby it is little to reach chip area, power consumption is little, shortens the subsequent authentication flow process, reduces the purposes such as convergence duration, also more is conducive to placement-and-routing.
Description of drawings
Fig. 1 is the Clock Tree generative circuit structural representation according to the multifunctional mode of prior art;
Fig. 2 is the Clock Tree generative circuit structural representation according to the multifunctional mode of the utility model one better embodiment.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing each embodiment of the present utility model is explained in detail.Yet, persons of ordinary skill in the art may appreciate that in each embodiment of the utility model, in order to make the reader understand the application better many ins and outs have been proposed.But, even without these ins and outs with based on many variations and the modification of following each embodiment, also can realize each claim of the application technical scheme required for protection.
A better embodiment of the present utility model relates to a kind of Clock Tree generative circuit of multifunctional mode.Concrete structure as shown in Figure 2.
The Clock Tree generative circuit of this multifunctional mode comprises: the independent clock source of at least two corresponding difference in functionality patterns (being 2 independent clock sources in the present embodiment: separately clock source 0 and separately clock source 1); Selector switch is used for the selection function pattern; The unified clock source that links to each other with this selector switch; With the register that this unified clock source links to each other by circuit, Clock Tree is created between this unified clock source and this register.
Wherein, selector switch links to each other by circuit with each independent clock source,, has at least not have the delay sequential circuit on the paths at each independent clock source to each path of selector switch.Do not exist the path that postpones sequential circuit to be the shortest path in each path.
Specifically, in the present embodiment, but the generative circuit practical function pattern 0 and functional mode 1 of Clock Tree.Functional mode 0 corresponding independent clock source is independent clock source 0; Functional mode 1 corresponding independent clock source is independent clock source 1.And in the present embodiment, clock source 0 to the path (S0) of selector switch is shortest path separately.Therefore, as shown in Figure 2,, on the path between the selector switch (S1 '), exist to postpone sequential circuit at independent clock source 1, and at independent clock source 0 on the path between the selector switch (S0 '), do not have the delay sequential circuit.This selector switch comprises at least one signal input part and at least one signal output part; Signal input part is used for receiving the indicator signal of the functional mode of selecting, and signal output part is used for connecting this unified clock source.On this unified clock source to the path of register, also be provided with sequential circuit, same as the prior art, do not repeat them here.
The principle of present embodiment is as follows:
For functional mode 0 and functional mode 1, find out last selection output common point (being the selector switch that is used for the selection function pattern in the present embodiment), obtain the unified clock source.Then, from this unified clock source as new clock source, generated clock tree circuit.After this unified clock source generates complete clock tree and finishes coiling, will net table and parasitic parameter and import static timing analysis tool, analyze the sequential violation situation of each independent clock source to the path of selector switch.And according to sequential violation situation, at non-shortest path the delay sequential circuit is set, and on shortest path, does not need to add any delay circuit, to satisfy the static timing requirement.Finally obtain circuit as shown in Figure 2.
It will be understood by those skilled in the art that in the present embodiment, owing to will produce a plurality of points of multifunctional mode Clock Tree, be merged into a point (unified clock tree source), in new unified clock source generated clock tree, simplified the Clock Tree structure.And, because each independent clock source is to unified clock tree source, nothing postpones sequential circuit on the shortest path, therefore, not only can saving chip area, save power consumption, save cost, reduce the convergence duration, also more be conducive to placement-and-routing, and, traditional process there is not too many change yet, thus compatible preferably to existing techniques in realizing.
Persons of ordinary skill in the art may appreciate that the respective embodiments described above are to realize specific embodiment of the utility model, and in actual applications, can do various changes to it in the form and details, and do not depart from spirit and scope of the present utility model.
Claims (4)
1. the Clock Tree generative circuit of a multifunctional mode is characterized in that, comprises:
The independent clock source of at least two corresponding difference in functionality patterns;
Be used for the selector switch of selection function pattern, described selector switch links to each other by circuit with each described independent clock source;
The unified clock source that links to each other with described selector switch;
With the register that described unified clock source links to each other by circuit, described Clock Tree is created between this unified clock source and this register;
Wherein,, to each path of described selector switch, have at least not have the delay sequential circuit on the paths at each described independent clock source.
2. the Clock Tree generative circuit of multifunctional mode according to claim 1 is characterized in that,
The described path that postpones sequential circuit that do not exist is shortest path in described each path.
3. the Clock Tree generative circuit of multifunctional mode according to claim 1 is characterized in that,
Be provided with sequential circuit on described unified clock source to the path of described register.
4. the Clock Tree generative circuit of each described multifunctional mode in 3 according to claim 1 is characterized in that,
Described selector switch comprises at least one signal input part and at least one signal output part;
Described signal input part is used for receiving the indicator signal of the functional mode of selecting;
Described signal output part is used for connecting described unified clock source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220510573 CN202904427U (en) | 2012-09-27 | 2012-09-27 | Clock tree generation circuit with multiple function modes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220510573 CN202904427U (en) | 2012-09-27 | 2012-09-27 | Clock tree generation circuit with multiple function modes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202904427U true CN202904427U (en) | 2013-04-24 |
Family
ID=48125074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220510573 Expired - Fee Related CN202904427U (en) | 2012-09-27 | 2012-09-27 | Clock tree generation circuit with multiple function modes |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202904427U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018188081A1 (en) * | 2017-04-14 | 2018-10-18 | Synopsys, Inc. | Pessimism reduction in static timing analysis |
| CN108984806A (en) * | 2017-05-31 | 2018-12-11 | 深圳市中兴微电子技术有限公司 | A kind of clock tree synthesis method and computer readable storage medium |
| CN114610662A (en) * | 2022-03-08 | 2022-06-10 | 浪潮云信息技术股份公司 | NCSI (network control information system) time sequence adjusting method and device |
| CN115667954A (en) * | 2020-08-28 | 2023-01-31 | 华为技术有限公司 | Detection circuit for keeping time allowance |
-
2012
- 2012-09-27 CN CN 201220510573 patent/CN202904427U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018188081A1 (en) * | 2017-04-14 | 2018-10-18 | Synopsys, Inc. | Pessimism reduction in static timing analysis |
| US10740520B2 (en) | 2017-04-14 | 2020-08-11 | Synopsys, Inc. | Pessimism in static timing analysis |
| CN108984806A (en) * | 2017-05-31 | 2018-12-11 | 深圳市中兴微电子技术有限公司 | A kind of clock tree synthesis method and computer readable storage medium |
| CN108984806B (en) * | 2017-05-31 | 2022-02-18 | 深圳市中兴微电子技术有限公司 | Clock tree synthesis method and computer readable storage medium |
| CN115667954A (en) * | 2020-08-28 | 2023-01-31 | 华为技术有限公司 | Detection circuit for keeping time allowance |
| CN114610662A (en) * | 2022-03-08 | 2022-06-10 | 浪潮云信息技术股份公司 | NCSI (network control information system) time sequence adjusting method and device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN202904427U (en) | Clock tree generation circuit with multiple function modes | |
| CN105808843A (en) | Construction method of mixed signal verification platform | |
| CN101706762A (en) | Intelligent type signal transfer system | |
| CN101303711A (en) | Gating clock for on-site programmable gate array and implementing method thereof | |
| CN102495356B (en) | Processing method of reset port of scan chain asynchronous reset register | |
| CN101719177B (en) | Method and device for on-chip system modeling and simulation | |
| CN103065529B (en) | Circuit dynamic reorganization EDA comprehensive experimental system | |
| CN202102275U (en) | IO port expansion circuit | |
| CN203191662U (en) | Liquid crystal display module test system | |
| CN203849370U (en) | Boundary scan testing apparatus | |
| CN202975317U (en) | Reconstructed FPGA radar digital signal processing assembly | |
| CN104951609B (en) | A kind of method of synchronous logic structure in processing gate level netlist | |
| CN205210574U (en) | Two obs core control modules based on microcontroller realizes FPGA data configuration | |
| CN202383253U (en) | Scan chain asynchronous reset register reset port processing circuit | |
| CN201845480U (en) | CPLD experimental board | |
| CN203423672U (en) | Dosage instrument signal simulator | |
| CN105824015B (en) | A kind of pulse-generating circuit of Phased Array Radar Antenna test device | |
| CN102929194B (en) | Asynchronous multi-core programmable automation controller (PAC) | |
| CN203026023U (en) | Experimental development board of single chip | |
| CN202887556U (en) | FPGA experiment development board | |
| CN201667071U (en) | Signal transfer system | |
| CN201928246U (en) | Phase-control device for phase shifter | |
| CN201495388U (en) | Sewing machine operation panel circuit | |
| CN204650202U (en) | A kind of CPLD of utilization realizes the single-chip computer control system of ports-Extending | |
| CN204087575U (en) | FPGA test and verification platform |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130424 Termination date: 20190927 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |