CN102929194B - Asynchronous multi-core programmable automation controller (PAC) - Google Patents
Asynchronous multi-core programmable automation controller (PAC) Download PDFInfo
- Publication number
- CN102929194B CN102929194B CN201210438640.1A CN201210438640A CN102929194B CN 102929194 B CN102929194 B CN 102929194B CN 201210438640 A CN201210438640 A CN 201210438640A CN 102929194 B CN102929194 B CN 102929194B
- Authority
- CN
- China
- Prior art keywords
- interface
- mainboard
- chip
- mainboards
- synchronous debugging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- Y02P80/114—
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention discloses an asynchronous multi-core PAC. The PAC comprises an analog main board, an input/output (I/O) main board, a motion control main board, a diagnose module, a synchronous debugger, a custom enhancement mode software process improvement (SPI) bus and a baseboard which is provided with a power supply communication device and a synchronous debugging bus, wherein the three main boards are installed on the baseboard provided with the power supply communication device and the synchronous debugging bus through pins, connected through the custom enhancement mode SPI bus respectively, and respectively connected with the diagnose module connected with a personal computer (PC); five daughter boards are installed on corresponding main boards; and the synchronous debugger is connected with the PC and the three main boards respectively. According to the PAC, multi-core asynchronous operation can be achieved, the problems that the clock frequency of a single-core processor is difficult to improve and the power consumption of the processor is large are effectively solved, and a good start is provided for solving the problems of safety and stability of control systems, reduction of the software development difficulty and the like.
Description
Technical field
The invention belongs to industrial automatic control field, be specifically related to a kind of automation controller able to programme (PAC), particularly a kind of asynchronous multinuclear automation controller able to programme.
Background technology
Growth along with industrial control equipment demand, current control system is more and more difficult to meet the needed greater functionality requirement of modern commercial Application, the requirements proposing in order to meet modern industrial control system application, people have proposed automation controller able to programme (PAC), automation controller able to programme (PAC) is replacing programmable logic controller (PLC) (PLC) gradually, becomes industrial control system ideal chose.Yet, current most of PAC still adopts the pattern of the single microprocessor (MCU) that PLC uses, make the load of control system very high, easily cause the real time problems under multitask system to occur, therefore, in order to meet performance requirement, by integrated more multi-core, improving performance is inevitable choice, but the structure of core also must be considered, because if core texture is too complicated, along with increasing of core amounts, not only can not improving performance, also can bring the problems such as wire delay increase and power consumption change are large, thereby heterogeneous polynuclear is an important direction, by structure, power consumption, function, the different a plurality of cores of operational performance are integrated on chip, and divide the work and divide different tasks is distributed to different cores by task, task of allowing each core processing oneself be good at, this isomery organizational form is executed the task more efficient than the polycaryon processor of isomorphism, realized the optimization configuration of resource, and reduced overall power.The automation controller able to programme of heterogeneous polynuclear will replace single core processor, solve the development bottleneck of microprocessor, it is the inevitable development trend of industrial control system in future, within following a period of time, it will occupy very important dominant position on processor market, therefore, studying a kind of heterogeneous polynuclear for industrial control system automation controller able to programme is to have very much realistic meaning, yet, common multinuclear controller is integrated a plurality of arithmetic element cores in an integrated chip (IC) at present, and in using the system of heterogeneous polynuclear, still adopt OS to carry out task scheduling, stability and the security of whole system are based upon on OS, single hardware MCU also causes the redundancy disappearance of whole system simultaneously.
Summary of the invention
The defect or the deficiency that for above-mentioned programmable logic controller (PLC), exist, the object of the invention is to, a kind of asynchronous multinuclear automation controller able to programme is proposed, this automation controller, by multinuclear asynchronous working, efficiently solves single core processor clock frequency and is difficult to the problem improving, microprocessor power consumption is larger.And provide a good start for solving the problems such as security, stability, reduction software development difficulty of control system.
To achieve these goals, the present invention adopts following technical solution:
An asynchronous multinuclear automation controller able to programme, comprises the base plate of simulating mainboard, I/O mainboard, motion control mainboard, diagnose module, synchronous debugging device, self-defined Enhanced SPI bus, having power supply communication device and synchronous debugging bus; Simulation mainboard, I/O mainboard and these three mainboards of motion control mainboard are arranged on the base plate with power supply communication device and synchronous debugging bus by contact pin; Described three mainboards interconnect by self-defined Enhanced SPI bus respectively; Described three mainboards are connected with diagnose module respectively, described diagnose module is logic analyser level signal Acquisition Circuit, in order to realize three level signal collections on mainboard, described diagnose module is connected with PC, in order to realize the demonstration to three mainboard level signals; Synchronous debugging device is connected respectively with PC, three mainboards, in order to realize the synchronous debugging of three mainboards.
The present invention also comprises following other technologies feature:
Described controller also includes five daughter boards (7), and described five daughter boards (7) are arranged on its corresponding mainboard, in order to three mainboards are carried out respectively to Function Extension; Described five daughter boards comprise DAC Interface Expanding circuit, ADC Interface Expanding circuit, I/O Interface Expanding circuit, step motor control Interface Expanding circuit and encoder interfaces expanded circuit, wherein, DAC Interface Expanding circuit is connected with simulation mainboard with ADC Interface Expanding circuit; I/O Interface Expanding circuit is connected with I/O mainboard; Step motor control Interface Expanding circuit is connected with motion control mainboard with encoder interfaces expanded circuit.
Described self-defined Enhanced SPI bus comprises 12 signal line, respectively: data line and clock line: comprise SPI_SCK, SPI_MISO, SPI_MOSI; Chip selection signal line: comprise NSS0, NSS1, NSS2, NSS3, SPI_NSS; Look-at-me line: comprise IT0, IT1, IT2, IT3.
Described synchronous debugging device comprises USB interface, STM32 chip and STM8SL05 chip.Wherein, USB interface, STM32 chip and STM8SL05 chip are connected successively; By 5 GPIO lines on the UART1 on STM32 chip and STM8SL05 chip and GND line, jointly form synchronous debugging device interface Debugger1; By 5 GPIO lines on the UART2 on STM32 chip and STM8SL05 chip and GND line, jointly form synchronous debugging device interface Debugger2; By 5 GPIO lines on the UART3 on STM32 chip and STM8SL05 chip and GND line, jointly form synchronous debugging device interface Debugger3; By 5 GPIO lines, GND line and UART on STM8SL05 chip, jointly form synchronous debugging device interface Debugger4; Debugger1, Debugger2, Debugger3 are connected with the download debugging interface JTAG on three mainboards respectively; PC connects synchronous debugging device by USB interface, and PC is connected respectively with the download debugging interface JTAG on three mainboards by synchronous debugging device interface Debugger1, Debugger2, the Debugger3 on synchronous debugging device.
The advantage of asynchronous multinuclear of the present invention automation controller able to programme is as follows:
1, every mainboard is all with the microcontroller of different operating frequency or same frequency, this is the imbody of coenocytism of the present invention and asynchronous working, in addition, on every mainboard also all with separately independently for supporting distributed control or the fieldbus of controlling in real time, RS485 interface, USB serial communication, download debugging interface JTAG, for the identical interface communication module such as the general serial data bus UART of asynchronous communication and spi bus interface and the functional module of self separately.Thereby guaranteed the independent and asynchronous work of each mainboard self.Such as only using in the course of the work simulation mainboard, that just only needs to use the signal in the collection of Diagnose module analysis mode mainboard, so only selecting to simulate mainboard by software programming carries out work and can meet control need of work, without three mainboards, all devote oneself to work, reduce power consumption, improved execution efficiency and the security of system of automation controller.It is more than the advantage of asynchronous multinuclear.
2, three mainboards and synchronous debugging device have formed self-organization reconfiguration system, make asynchronous multinuclear of the present invention automation controller able to programme there is reconfigurability and programmability, versatility and the operational performance of multinuclear have greatly been improved, make processor existing the versatility of general purpose microprocessor, the high-performance that has again single multi core chip system, has the advantages such as dirigibility, high-performance, high reliability, low energy consumption concurrently.More than for the advantage of self-organization reconfiguration system.
3, self-defined Enhanced SPI bus has overcome the shortcoming that existing spi bus only can one-way communication, between three mainboards, by Enhanced SPI bus, forms an integral body, realizes mutual communication each other.In the course of the work, slave can interrupt by look-at-me line the signal of main frame, self is set to main frame, thereby main frame or slave each other between three mainboards, and only has at any time a mainboard as main frame, other mainboards can only be as slave, has realized the response type communication that main frame interrupts mutually with slave be connected by look-at-me line.
4, the base plate that has power supply communication device and a synchronous debugging bus is the indispensable part of the present invention, mainly contains electric supply installation and synchronous debugging bus and forms.Five daughter boards are arranged on three mainboards by contact pin according to each self-corresponding expansion interface, and three mainboards are arranged on the base plate with power supply communication device and synchronous debugging bus by contact pin; While needing, synchronous debugging device is connected with three mainboards, and while not needing, synchronous debugging device independently exists.By the electric supply installation on base plate, to three main board power supplies, realize interconnecting and communication between three mainboards, five daughter boards and synchronous debugging device.
Accompanying drawing explanation
Fig. 1 is asynchronous multinuclear of the present invention automation controller structural representation able to programme.Each label in figure: 1, simulation mainboard; 2, I/O mainboard; 3, motion control mainboard; 4, Diagnose module; 5, synchronous debugging device; 6, self-defined Enhanced SPI bus; 7, five daughter boards.
Fig. 2 is the structural representation of simulation mainboard.Each label in figure: 8, CAN Bus; 9, RS485 interface; 10, USB serial ports; 11, download debugging interface JTAG; 12, general serial data bus UART; 13, ADC analog acquisition front end modulate circuit; 14, D/A circuit; 15, simulation mainboard MCU; 16, A/D circuit; 17, DAC digital back-end modulate circuit; 18,24 row's terminals; 19,2803 chips; 20, outputting circuit for relay; 21, extend out 24 contact pins; 22, isolation DIO; 23, self-defined Enhanced SPI connection terminal; 24, communication terminal during configuration.
Fig. 3 is the structural representation of I/O mainboard.Each label in figure: 25, fieldbus (CAN); 26, RS485 interface; 27, USB serial ports; 28, download debugging interface JTAG; 29, general serial data bus UART; 30, configuration communication terminal interface; 31, extend out 24 contact pins; 32, I/O mainboard MCU; 33,4245 chips; 34, input optocoupler signal isolation circuit; 35, input terminal; 36,4245 chips; 37, output optocoupler signal isolation circuit; 38, lead-out terminal; 39,24 terminal rows; 40, self-defined Enhanced SPI connection terminal; 41, power supply terminal.
Fig. 4 is the structural representation of motion control mainboard.Each label in figure: 42, fieldbus (CAN); 43, RS485 interface; 44, USB serial ports; 45, download debugging interface JTAG; 46, general serial data bus UART; 47, configuration communication terminal interface; 48, extend out 24 contact pins; 49, motion control mainboard MCU; 50,4245 chips; 51, optocoupler signal isolation circuit; 52, single-ended transfer difference; 53,4245 chips; 54, optocoupler signal isolation circuit; 55,24 terminal rows; 56, self-defined Enhanced SPI connection terminal.
Fig. 5 is three mainboards and five daughter board connection diagrams.Each label in figure: 2, I/O mainboard; 1, simulation mainboard; 6, self-defined Enhanced SPI bus; 3, motion control mainboard; 57, DAC Interface Expanding circuit; 58, ADC Interface Expanding circuit; 59, the Interface Expanding circuit of I/O mainboard; 60, step motor control Interface Expanding circuit; 61, encoder interfaces expanded circuit.
Fig. 6 is the schematic diagram connecting by self-defined Enhanced SPI bus between three mainboards.In figure, each label is: 6, the Enhanced SPI connection terminal of Enhanced SPI bus, 23, simulation mainboard 1; 40, the Enhanced SPI connection terminal of I/O mainboard 2; 56, the Enhanced SPI connection terminal of motion control mainboard 3.
Fig. 7 is synchronous debugging device structural representation.Each label in figure: 62, USB interface; 63, STM32; 64, STM32L05.
Below in conjunction with the drawings and specific embodiments, the present invention is further explained.
Embodiment
Referring to Fig. 1, the present invention is asynchronous multinuclear automation controller able to programme, comprises simulation mainboard 1, I/O mainboard 2, motion control mainboard 3, Diagnose module 4, synchronous debugging device 5, self-defined Enhanced SPI bus 6, five daughter boards 7 and has power supply communication device and the base plate of synchronous debugging bus;
Simulation mainboard 1, I/O mainboard 2 and motion control mainboard 3 are arranged on by contact pin on the base plate with power supply communication device and synchronous debugging bus, by having electric supply installation on the base plate of power supply communication device and synchronous debugging bus to three main board power supplies.
Simulation mainboard 1, I/O mainboard 2 are connected by self-defined Enhanced SPI bus 6 with motion control mainboard 3, ad eundem between three mainboards, by self-defined Enhanced SPI bus 6, realizing the response type communication that main frame interrupts mutually with slave is connected, but any time in operational process, only have a mainboard as main frame, other mainboards are as slave.Simulate mainboard 1 for the digital signal collecting is converted to analog voltage signal by DAC, and by backward channel circuit conversion, be positive and negative 10V by 0 to 2.5V voltage of output, for servomotor simulation controlled quentity controlled variable.I/O mainboard 2 is for the input and output of the various switching values of controller.Motion control mainboard 3 is for realizing the control of stepper motor and the input of special signal (initial point signal, the input of the proprietary signal such as forward is spacing, negative sense is spacing).
Described simulation mainboard 1, I/O mainboard 2 and motion control mainboard 3 these three mainboards are connected with diagnose module 4 respectively; Diagnose module 4 is logic analyser level signal Acquisition Circuit in early stage, in order to the level signal collection on three mainboards.Diagnose module 4 can be connected with PC, and the level signal collecting is shown on PC.
Described three mainboards and synchronous debugging device 5 form self-organization reconfiguration system, make controller of the present invention have reconfigurability and programmability, improve versatility and the operational performance of multinuclear.Self-organization reconfiguration system is core component of the present invention; Diagnose module 4, self-defined Enhanced SPI bus 6 and five daughter boards 7 are supplementary modules, for meeting the collection of connection, communication, Interface Expanding and level signal.
Referring to Fig. 2, described simulation mainboard 1 comprises fieldbus 8, RS485 interface 9, USB serial ports 10, download debugging interface JTAG 11, general serial data bus UART 12, ADC analog acquisition front end modulate circuit 13, D/A circuit 14, simulation mainboard MCU 15, A/D circuit 16, DAC digital back-end modulate circuit 17, 24 row's terminals 18, 2803 chips 19, outputting circuit for relay 20, extend out 24 contact pins 21, isolation DIO 22, self-defined Enhanced SPI connection terminal 23 when configuration tri-mainboards of communication terminal 24(and to together with, it during overall work, is configuration, during overall work, by configuration communication terminal 24, carry out communication, during each independent mainboard work, be independent state, when it works alone, by independent state communication terminal, carry out communication), wherein, described fieldbus 8, RS485 interface 9, USB serial ports 10, download debugging interface JTAG 11, general serial data bus UART 12, D/A circuit 14, A/D circuit 16,2803 chips 19, extend out 24 contact pins 21, isolation DIO 22, self-defined Enhanced SPI connection terminal 23 during with configuration communication terminal 24 be connected with simulation mainboard MCU 15 respectively, described A/D circuit 16, DAC digital back-end modulate circuit 17,24 row's terminals 18, ADC analog acquisition front end modulate circuit 13 are connected successively with D/A circuit 14, described 2803 chips 19 are connected with outputting circuit for relay 20.
Referring to Fig. 3, described I/O mainboard 2 comprises fieldbus 25, RS485 interface 26, USB serial ports 27, download debugging interface JTAG28, general serial data bus UART29, configuration communication terminal interface 30, extends out 24 contact pins 31, I/O mainboard MCU 32,4245 chips 33, input optocoupler signal isolation circuit 34, input terminal 35,4245 chips 36, output optocoupler signal isolation circuit 37, lead-out terminal 38,24 terminal rows 39, self-defined Enhanced SPI connection terminal 40 and power supply terminal 41; Wherein, described fieldbus 25, RS485 interface 26, USB serial ports 27, download debugging interface JTAG28, general serial data bus UART29, configuration communication terminal interface 30, extend out 24 contact pin 31,4245 chip 33,4245 chip 36,24 terminal rows 39, self-defined Enhanced SPI connection terminal 40, power supply terminal 41 be connected with I/O mainboard MCU 32 respectively; Described input terminal 35, input optocoupler signal isolation circuit 34 are connected successively with 4245 chips 33; Described 4245 chips 36, output optocoupler signal isolation circuit 37, lead-out terminal 38 are connected successively.
Referring to Fig. 4, described motion control mainboard 3 comprises fieldbus 42, RS485 interface 43, USB serial ports 44, downloads debugging interface JTAG 45, general serial data bus UART 46, configuration communication terminal interface 47, extends out 24 contact pins 48, motion control mainboard MCU 49,4245 chips 50, optocoupler signal isolation circuit 51, single-ended transfer difference 52,4245 chips 53, optocoupler signal isolation circuit 54,24 terminal rows 55 and self-defined Enhanced SPI connection terminal 56; Wherein, described fieldbus 42, RS485 interface 43, USB serial ports 44, download debugging interface JTAG 45, general serial data bus UART 46, configuration communication terminal interface 47, extend out 24 contact pin 48,4245 chip 50,4245 chip 53,24 terminal rows 55 and be connected with motion control mainboard MCU 49 respectively with self-defined Enhanced SPI connection terminal 56; Described 4245 chips 50, optocoupler signal isolation circuit 51 are connected successively with single-ended transfer difference circuit 52; Described 4245 chips 53 are connected with optocoupler signal isolation circuit 54; Single-ended transfer difference circuit 52 is connected with 24 terminal rows 55 respectively with optocoupler signal isolation circuit 54.
Referring to Fig. 5, described five daughter boards 7 comprise DAC Interface Expanding circuit 57, ADC Interface Expanding circuit 58, I/O Interface Expanding circuit 59, step motor control Interface Expanding circuit 60 and encoder interfaces expanded circuit 61.Five Interface Expanding circuit that daughter board is respectively three mainboards, realize the Interface Expanding of three mainboards, for connecting and controlling more external unit.Wherein, DAC Interface Expanding circuit 57 and ADC Interface Expanding circuit 58 are installed on simulation mainboard 1, as the expansion interface of simulation mainboard 1 by contact pin;
I/O Interface Expanding circuit 59 is installed on I/O mainboard 2 by contact pin, as the expansion interface of I/O mainboard 2; Step motor control Interface Expanding circuit 60 and encoder interfaces expanded circuit 61 are installed on motion control mainboard 3 by contact pin, as the expansion interface of motion control mainboard 3.
Referring to Fig. 6, described self-defined Enhanced SPI bus 6 comprises 12 signal line, respectively that data line and clock line (comprise SPI_SCK, SPI_MISO, SPI_MOSI), chip selection signal line (comprises NSS0, NSS1, NSS2, NSS3, SPI_NSS) and look-at-me line (comprise IT0, IT1, IT2, IT3), wherein, data line and clock line are for the signal and communication between slave and main frame, chip selection signal line passes through this signal-line choosing slave for main frame, look-at-me line sends look-at-me to main frame for slave, thereby interrupt the signal of main frame, and self is set to main frame, other are slave, realizing the response type communication that main frame interrupts mutually with slave is connected, this is also the difference place with existing spi bus.Self-defined Enhanced SPI bus 6 is selected signal wire than the many 4 look-at-me lines of traditional spi bus and 4 silvers.
The self-defined Enhanced SPI connection terminal 56 of the self-defined Enhanced SPI connection terminal 23 of described simulation mainboard 1, the self-defined Enhanced SPI connection terminal 40 of I/O mainboard 2, motion control mainboard 3 is connected by 12 signal line of self-defined Enhanced SPI bus 6.Self-defined Enhanced SPI connection terminal meets the installation requirement of self-defined Enhanced SPI bus 6.
Referring to Fig. 7, described synchronous debugging device 5 mainly comprises USB interface 62, STM32 chip 63 and STM8SL05 chip 64.Wherein, USB interface 62, STM32 chip 63 and STM8SL05 chip 64 are connected successively; By 5 GPIO lines on the UART1 on STM32 chip 63 and STM8SL05 chip 64 and GND line, jointly form synchronous debugging device interface Debugger1; By 5 GPIO lines on the UART2 on STM32 chip 63 and STM8SL05 chip 64 and GND line, jointly form synchronous debugging device interface Debugger2; By 5 GPIO lines on the UART3 on STM32 chip 63 and STM8SL05 chip 64 and GND line, jointly form synchronous debugging device interface Debugger3; By 5 GPIO lines, GND line and UART on STM8SL05 chip 64, jointly form synchronous debugging device interface Debugger4.
Synchronous debugging device interface Debugger1, Debugger2, Debugger3 are connected with the download debugging interface JIAG on three mainboards respectively, PC is connected with the USB interface 62 of synchronous debugging device 5, and transmits data to STM32 chip 63 and STM8SL05 chip 64 by USB interface 78.Therefore, PC is connected respectively with the download debugging interface JIAG on three mainboards by Debugger1, Debugger2, the Debugger3 on synchronous debugging device 5, realizes the synchronous debugging of three mainboards.In the time of need to downloading debugging, synchronous debugging device (5) is connected with three mainboards, and while not needing, synchronous debugging device (5) can independently exist.
Synchronous debugging device interface Debugger4 is the synchronous debugging interface having more, for the expansion of mainboard.
Claims (4)
1. an asynchronous multinuclear automation controller able to programme, it is characterized in that, comprise the base plate of simulating mainboard (1), I/O mainboard (2), motion control mainboard (3), diagnose module (4), synchronous debugging device (5), self-defined Enhanced SPI bus (6), thering is power supply communication device and synchronous debugging bus; Simulation mainboard (1), I/O mainboard (2) and these three mainboards of motion control mainboard (3) are arranged on the base plate with power supply communication device and synchronous debugging bus by contact pin; Described three mainboards interconnect by self-defined Enhanced SPI bus (6) respectively; Described three mainboards are connected with diagnose module (4) respectively, described diagnose module (4) is logic analyser level signal Acquisition Circuit, in order to realize three level signal collections on mainboard, described diagnose module (4) is connected with PC, in order to realize the demonstration to three mainboard level signals; Synchronous debugging device (5) is connected respectively with PC, three mainboards, in order to realize the synchronous debugging of three mainboards.
2. asynchronous multinuclear as claimed in claim 1 automation controller able to programme, is characterized in that, also includes five daughter boards (7), and described five daughter boards (7) are arranged on its corresponding mainboard, in order to three mainboards are carried out respectively to Function Extension; Described five daughter boards (7) comprise DAC Interface Expanding circuit (57), ADC Interface Expanding circuit (58), I/O Interface Expanding circuit (59), step motor control Interface Expanding circuit (60) and encoder interfaces expanded circuit (61), wherein, DAC Interface Expanding circuit (57) is connected with simulation mainboard (1) with ADC Interface Expanding circuit (58); I/O Interface Expanding circuit (59) is connected with I/O mainboard (2); Step motor control Interface Expanding circuit (60) is connected with motion control mainboard (3) with encoder interfaces expanded circuit (61).
3. asynchronous multinuclear as claimed in claim 1 automation controller able to programme, is characterized in that, described self-defined Enhanced SPI bus (6) comprises 12 signal line, respectively: data line and clock line: comprise SPI_SCK, SPI_MISO, SPI_MOSI; Chip selection signal line: comprise NSS0, NSS1, NSS2, NSS3, SPI_NSS; Look-at-me line: comprise IT0, IT1, IT2, IT3.
4. asynchronous multinuclear as claimed in claim 1 automation controller able to programme, is characterized in that, described synchronous debugging device (5) comprises USB interface (62), STM32 chip (63) and STM8SL05 chip (64); Wherein, USB interface (62), STM32 chip (63) and STM8SL05 chip (64) are connected successively; By 5 GPIO lines on the UART1 on STM32 chip (63) and STM8SL05 chip (64) and GND line, jointly form synchronous debugging device interface Debugger1; By 5 GPIO lines on the UART2 on STM32 chip (63) and STM8SL05 chip (64) and GND line, jointly form synchronous debugging device interface Debugger2; By 5 GPIO lines on the UART3 on STM32 chip (63) and STM8SL05 chip (64) and GND line, jointly form synchronous debugging device interface Debugger3; By 5 GPIO lines, GND line and UART on STM8SL05 chip (64), jointly form synchronous debugging device interface Debugger4; Debugger1, Debugger2, Debugger3 are connected with the download debugging interface JTAG on three mainboards respectively; PC connects synchronous debugging device (5) by USB interface (62), and PC is connected respectively with the download debugging interface JTAG on three mainboards by synchronous debugging device interface Debugger1, Debugger2, the Debugger3 on synchronous debugging device (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210438640.1A CN102929194B (en) | 2012-11-06 | 2012-11-06 | Asynchronous multi-core programmable automation controller (PAC) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210438640.1A CN102929194B (en) | 2012-11-06 | 2012-11-06 | Asynchronous multi-core programmable automation controller (PAC) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102929194A CN102929194A (en) | 2013-02-13 |
| CN102929194B true CN102929194B (en) | 2014-09-17 |
Family
ID=47644023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210438640.1A Expired - Fee Related CN102929194B (en) | 2012-11-06 | 2012-11-06 | Asynchronous multi-core programmable automation controller (PAC) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102929194B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103744342B (en) * | 2014-01-22 | 2016-09-14 | 大连理工计算机控制工程有限公司 | A kind of PAC real-time control system based on dual core processor |
| CN109766292A (en) * | 2019-01-23 | 2019-05-17 | 济南浪潮高新科技投资发展有限公司 | A kind of jtag interface multiplexing functions circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090210070A1 (en) * | 2007-11-13 | 2009-08-20 | Schultz Ronald E | Industrial controller using shared memory multicore architecture |
| CN101840368A (en) * | 2010-03-26 | 2010-09-22 | 中国科学院计算技术研究所 | JTAG (Joint Test Action Group) real-time on-chip debug method and system of multicore processor |
| CN102103535A (en) * | 2011-03-07 | 2011-06-22 | 北京大学深圳研究生院 | Multicore processor, and system and method for debugging multicore processor |
| CN202975731U (en) * | 2012-11-06 | 2013-06-05 | 长安大学 | Novel asynchronous multiple nuclear automation controller |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009054083A (en) * | 2007-08-29 | 2009-03-12 | Hitachi Ltd | Processor, data transfer unit, and multi-core processor system |
-
2012
- 2012-11-06 CN CN201210438640.1A patent/CN102929194B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090210070A1 (en) * | 2007-11-13 | 2009-08-20 | Schultz Ronald E | Industrial controller using shared memory multicore architecture |
| CN101840368A (en) * | 2010-03-26 | 2010-09-22 | 中国科学院计算技术研究所 | JTAG (Joint Test Action Group) real-time on-chip debug method and system of multicore processor |
| CN102103535A (en) * | 2011-03-07 | 2011-06-22 | 北京大学深圳研究生院 | Multicore processor, and system and method for debugging multicore processor |
| CN202975731U (en) * | 2012-11-06 | 2013-06-05 | 长安大学 | Novel asynchronous multiple nuclear automation controller |
Non-Patent Citations (2)
| Title |
|---|
| 多核处理器系统设计;杨东芳;《郑州铁路职业技术学院学报》;20090320(第1期);28-30 * |
| 杨东芳.多核处理器系统设计.《郑州铁路职业技术学院学报》.2009,(第1期),28-30. |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102929194A (en) | 2013-02-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102360046B (en) | General test method for motor vehicle electrical product | |
| CN109063339B (en) | Digital spacecraft component-level embedded simulation system | |
| CN202975731U (en) | Novel asynchronous multiple nuclear automation controller | |
| CN108732987A (en) | It can customize the embedded soft PLC control system and its design method of I/O port numbers | |
| CN102929194B (en) | Asynchronous multi-core programmable automation controller (PAC) | |
| CN202150868U (en) | Multi-protocol data acquisition gateway | |
| CN201607721U (en) | Embedded online debugging system | |
| CN111212000B (en) | Exchange backplate based on PXIe bus | |
| CN202904427U (en) | Clock tree generation circuit with multiple function modes | |
| RU160905U1 (en) | MULTIFUNCTIONAL CONTROLLER OF WIDE APPLICATION | |
| CN104965469A (en) | CPCI bus standard-based multi-function acquisition control device | |
| CN202453435U (en) | Debug control device, debug execution device and debug system | |
| CN201348757Y (en) | PC/104 motherboard using power supply circuit separation design | |
| CN210380935U (en) | Communication address self-setting system of digital weighing sensor | |
| CN103218334A (en) | Computer peripheral cascade device based on USB (Universal Serial Bus) and RS485 bus | |
| CN203630782U (en) | Universal serial bus (USB) interface chip for embedded applications | |
| CN207301729U (en) | A kind of embedded multi-axis controller with man-machine interface | |
| CN218768136U (en) | Device for switching I2C bus by using programmable logic device | |
| CN201444302U (en) | SOC chip with pin capable of being configured | |
| CN101719053A (en) | Method for reading IIC storage card by SPI interface | |
| CN111781866A (en) | Reconfigurable testing and sending control computer module group based on FPGA | |
| CN100405252C (en) | Conversion circuit of clock signal | |
| CN210721099U (en) | STM 32-based gating control system | |
| CN202917072U (en) | Embedded system | |
| CN105243829B (en) | Portable analog meter module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140917 Termination date: 20161106 |