CN201444302U - SOC chip with pin capable of being configured - Google Patents
SOC chip with pin capable of being configured Download PDFInfo
- Publication number
- CN201444302U CN201444302U CN2009200268448U CN200920026844U CN201444302U CN 201444302 U CN201444302 U CN 201444302U CN 2009200268448 U CN2009200268448 U CN 2009200268448U CN 200920026844 U CN200920026844 U CN 200920026844U CN 201444302 U CN201444302 U CN 201444302U
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- soc
- soc chip
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- 239000011159 matrix material Substances 0.000 claims abstract description 9
- 238000005516 engineering process Methods 0.000 description 4
- 210000004556 brain Anatomy 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Abstract
The utility model discloses an SOC chip with the pin capable of being configured, which belongs to an SOC chip, the structure of which comprises an IP core, a pin control unit and a pin, wherein the pin is controlled by the pin control unit, the digital signal output by the IP core is accessed into a priority encoder to define priority, the pin selection signal of the pin control unit is accessed to a pin latch to be latched, and both the priority encoder and the pin latch are connected to a cross matrix module. Compared with the prior art, the configurable design of the utility model can lead the definition of the I/O port of the chip to be defined within a certain range, so the wiring of the PCB board is very convenient, thereby, the time is saved and the efficiency is improved.
Description
Technical field
The utility model relates to a kind of SOC chip, specifically a kind of SOC chip of configurable pin.
Background technology
Because the demand of information market and the development of microelectronics self, having caused with microfabrication (the integrated circuit characteristic dimension is constantly dwindled) is the kinds of processes integrated technology of principal character and the development of application oriented system level chip.SOC produces under the general orientation that integrated system (IS) changes at integrated circuit (IC) just.
The definition of SOC is varied, owing to its rich connotation, applied range, is difficult to provide accurate definition.In general, SOC is called system level chip, and the title SOC (system on a chip) is also arranged, and meaning it is a product, is an integrated circuit that application-specific target is arranged, and wherein comprises holonomic system and the full content of embedded software is arranged.It is again a kind of technology simultaneously,, divides to software/hardware from determining systemic-function in order to realization, and finishes the whole process of design.From the narrow sense angle, it is that the chip of infosystem core is integrated, is that the system core parts are integrated on the chip piece; From the broad sense angle, SOC is a mini system, if central processing unit (CPU) is a brain, SOC is exactly the system that comprises brain, heart, eyes and hand so.Both at home and abroad the general tendency of academia is defined as SOC microprocessor, Simulation with I P nuclear, digital IP kernel and storer (or sheet external memory control interface) is integrated on the one chip, its normally customization, or towards the standardized product of special-purpose.
The SOC chip is because its function is many, so can run into a lot of difficulties in the design of pcb board wiring.
The utility model content
Technical assignment of the present utility model is at above weak point, and the SOC chip of a kind of configurable pin that a kind of SOC chip pin can dispose is provided.
The technical scheme that its technical matters that solves the utility model adopts is: comprise IP kernel, pin control module and pin, pin is by the control of pin control module; Definition priority in the Digital signal access priority scrambler of IP kernel output, the pin of pin control module select signal by inserting the pin latches, and priority encoder and pin latch all are connected to crossing matrix modules.
The course of work of the SOC chip of a kind of configurable pin of the present utility model is:
1, the Digital signal of each IP kernel output of SOC defines priority by priority encoder;
2, the pin of pin control module selects signal by the pin latches;
3, the information of priority encoder and pin latch is sent into crossing matrix modules;
4, crossing matrix modules is determined the pin positions of each Digital signal correspondence according to the pin of the Digital priority class of traffic of priority encoder definition and pin latches.
The SOC chip of a kind of configurable pin of the present utility model is compared with prior art, the configurable design of SOC pin then makes the definition of chip I/O mouth to define freely within the specific limits, therefore can be very convenient in the placement-and-routing of pcb board, thus the time saved, improved efficient; Thereby, have good value for applications.
Description of drawings
Below in conjunction with accompanying drawing the utility model is further specified.
Accompanying drawing 1 is a kind of circuit structure block diagram of SOC chip of configurable pin.
Among the figure: 1, IP kernel; 2, priority encoder; 3, crossing matrix modules; 4, pin control module; 5, pin; 6, pin latch.
Embodiment
The utility model is described in further detail below in conjunction with the drawings and specific embodiments.
The SOC chip of a kind of configurable pin of the present utility model, its structure comprise IP kernel 1, pin control module 4 and pin 5, and pin 5 is by 4 controls of pin control module; Definition priority in the Digital signal access priority scrambler 2 of IP kernel 1 output, the pin of pin control module 4 select signal to latch by inserting pin latch 6, and priority encoder 2 all is connected to crossing matrix modules 3 with pin latch 6.
The course of work of the SOC chip of a kind of configurable pin of the present utility model is:
1, the Digital signal (as serial ports controller signal, timer signal, 12C bus controller signal, spi bus controller signals, system clock module signal etc. among the figure) of each IP kernel 1 output of SOC is by priority encoder 2 definition priority;
2, the pin of pin control module 4 (a plurality of pins are arranged) selects signal to latch by pin latch 6;
3, the information of priority encoder 2 and pin latch 6 is sent into crossing matrix modules 3;
4, the pin 5 that latchs according to the Digital priority class of traffic and the pin latch 6 of priority encoder 2 definition of crossing matrix modules 3 is determined the pin positions of each Digital signal correspondence.
Therefore, each pin 5 can be according to demand, its output Digital signal of definition configuration.Thereby can make that the wiring of pcb board is more flexible.
Except that the described technical characterictic of instructions, be the known technology of those skilled in the art.
Claims (1)
1. the SOC chip of a configurable pin, comprise IP kernel, pin control module and pin, pin is by the control of pin control module, the interior definition of the Digital signal access priority scrambler priority that it is characterized in that IP kernel output, the pin of pin control module selects signal by inserting the pin latches, and priority encoder and pin latch all are connected to crossing matrix modules.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2009200268448U CN201444302U (en) | 2009-06-04 | 2009-06-04 | SOC chip with pin capable of being configured |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2009200268448U CN201444302U (en) | 2009-06-04 | 2009-06-04 | SOC chip with pin capable of being configured |
Publications (1)
Publication Number | Publication Date |
---|---|
CN201444302U true CN201444302U (en) | 2010-04-28 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN2009200268448U Expired - Fee Related CN201444302U (en) | 2009-06-04 | 2009-06-04 | SOC chip with pin capable of being configured |
Country Status (1)
Country | Link |
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CN (1) | CN201444302U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101794771A (en) * | 2010-02-26 | 2010-08-04 | 深圳市硅格半导体有限公司 | SIP (Session Initiation Protocol) chip and SOC (System On Chip) thereof |
CN105223492A (en) * | 2015-10-23 | 2016-01-06 | 英特格灵芯片(天津)有限公司 | A kind of chip pin configuration-system and method thereof |
-
2009
- 2009-06-04 CN CN2009200268448U patent/CN201444302U/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101794771A (en) * | 2010-02-26 | 2010-08-04 | 深圳市硅格半导体有限公司 | SIP (Session Initiation Protocol) chip and SOC (System On Chip) thereof |
CN101794771B (en) * | 2010-02-26 | 2011-06-08 | 深圳市硅格半导体有限公司 | SIP (Session Initiation Protocol) chip and SOC (System On Chip) thereof |
CN105223492A (en) * | 2015-10-23 | 2016-01-06 | 英特格灵芯片(天津)有限公司 | A kind of chip pin configuration-system and method thereof |
CN105223492B (en) * | 2015-10-23 | 2018-08-28 | 英特格灵芯片(天津)有限公司 | A kind of chip pin configuration system and method |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100428 Termination date: 20120604 |