CN100480923C - Controller soft realizing method from I2C bus - Google Patents

Controller soft realizing method from I2C bus Download PDF

Info

Publication number
CN100480923C
CN100480923C CNB2006100328242A CN200610032824A CN100480923C CN 100480923 C CN100480923 C CN 100480923C CN B2006100328242 A CNB2006100328242 A CN B2006100328242A CN 200610032824 A CN200610032824 A CN 200610032824A CN 100480923 C CN100480923 C CN 100480923C
Authority
CN
China
Prior art keywords
mcu
scl
controller
clock signal
external interrupt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2006100328242A
Other languages
Chinese (zh)
Other versions
CN1821914A (en
Inventor
白骥
郭敏强
黄黎明
徐勇
何彦
许雪松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Skyworth RGB Electronics Co Ltd
Original Assignee
Shenzhen Skyworth RGB Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Skyworth RGB Electronics Co Ltd filed Critical Shenzhen Skyworth RGB Electronics Co Ltd
Priority to CNB2006100328242A priority Critical patent/CN100480923C/en
Publication of CN1821914A publication Critical patent/CN1821914A/en
Priority to HK07101832.3A priority patent/HK1094606A1/en
Application granted granted Critical
Publication of CN100480923C publication Critical patent/CN100480923C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

  • Information Transfer Systems (AREA)

Abstract

This invention discloses a soft realization method for 1< 2 >C bus line from a controller characterizing in connecting SCL of a master controller directly to said MCU outer interruption port to test the up-rising edge and the descending edge of the SCL time signal of the master controller or connecting the SCL line of the master controller to an outer interruption port of the MCU directly and connecting it to the input of a not-gate circuit, an outer interruption port of the MCU tests the up-rising edge of the SCL clock signals from the master controller, the other port or the input pin of a counter test the descending edge of the SCL clock signal, so it's not necessary for the MCU to cost much time to sample, the data rate reception is adaptive and in short code to save much storage space.

Description

I 2The soft implementation method of C bus slave controller
Technical field
The present invention relates to the interconnection between distinct device, especially relate to a kind of I 2The soft implementation method of C bus slave controller.
Background technology
Adopt the bus structure of unified standard to make realization interconnection easily between distinct device, so that the expansion of parts and equipment.Along with microelectric technique and development of computer, bussing technique is also in development and perfect constantly.(Inter-Integrated Circuit abbreviates I as to the built-in integrated circuit of being released by Philips company 2C or Inter-IC) bus is the internal bus that is used for the interconnection of chip one-level.This simple two-way two line buses, interface line comprises a serial data line SDA and a serial time clock line SCL, adds that ground wire also has only three, because transmission line seldom, and antijamming capability is strong, speed is fast, has a wide range of applications with the chip one-level communications field at household electrical appliances.Band I 2The device of C bus interface can work in the master controller pattern, also can work in the slave controller pattern, still, and I 2Can only carry out simultaneously the master-slave communication of a master controller and a plurality of slave controllers on the C bus, each transmission regulation is initiated by master controller.Yet, many microcontroller MCU are arranged for saving hardware resource in the sheet, do not design Hardware I 2The C bus; The Hardware I of the MCU that has own 2The C bus controller is not enough; The Hardware I of some MCU also 2The C bus has only the master controller pattern not have the slave controller pattern, perhaps has only the slave controller pattern not have the master controller pattern.Have not yet to see effective solution I 2C bus slave controller lack problem, some can only adopt at hardware aspect and extend out chip and add I 2C bus slave controller, and adopt the soft implementation method of I2C bus slave controller very complicated, generally be that the clock frequency that detects on the scl line by an interruptive port is the 100Kbit/s of mode standard, or the 400Kbit/s of quick mode, or the 3.4Mbit/s of fast mode, generally be that rising edge or negative edge trigger interruption, requirement is sampled to scl line and sda line simultaneously with higher rate, then according to the data on the clock rate reception sda line, the legitimacy of judgment data causes the data code length that receives on the sda line longer, and MCU will spend a large amount of time and sample, preventing misreading of data, the clock rate on can't automatic adaptive scl line.If master controller crystal oscillation frequency less stable causes the clock frequency on the scl line that bigger deviation is arranged; Perhaps master controller work also is to use software simulation, does not use timer to control its traffic rate, and by the data on the reception of the speed on the pre-determined scl line sda line, stability and reliability are difficult to guarantee so.
Summary of the invention
A technical matters to be solved by this invention is the defective that overcomes prior art, at the I that lacks that can detect rising edge of clock signal and negative edge simultaneously 2The microcontroller of C bus slave controller proposes a kind of I 2The soft implementation method of C bus slave controller, with master controller realize more efficient, more save the master-slave communication of resource;
Another technical matters to be solved by this invention is the defective that overcomes prior art, at the I that lacks that can only detect rising edge of clock signal or negative edge 2The microcontroller of C bus slave controller proposes another kind of I 2The soft implementation method of C bus slave controller, with master controller realize more efficient, more save the master-slave communication of resource.
For the I that lacks that can detect rising edge of clock signal and negative edge simultaneously 2The microcontroller of C bus slave controller, technical matters of the present invention is solved by the following technical programs.
This I 2The soft implementation method of C bus slave controller, the mainboard of corresponding master controller is provided with microcontroller MCU chip.
This I 2The characteristics of the soft implementation method of C bus slave controller are:
The MCU chip of the external interrupt port that but described microcontroller MCU chip as slave controller is the band edge to be triggered;
Described MCU external interrupt port has only one;
The scl line of master controller is connected directly to the external interrupt port of described MCU, detect the SCL rising edge of clock signal and the negative edge of autonomous controller by the external interrupt port of described MCU, can realize the master-slave communication between master controller and this slave controller.The outside connecting circuit of described MCU is with respect to traditional band I 2The hardware circuit of the slave controller analogy method of C bus interface need not to do change.
For the I that lacks that can detect rising edge of clock signal and negative edge simultaneously 2The microcontroller of C bus slave controller, technical matters of the present invention is solved by following further technical scheme.
Come the SCL rising edge of clock signal of autonomous controller, the detection of negative edge to be, by code the triggering mode register of MCU is put one, MCU external interrupt rising edge triggers, with the zero clearing of triggering mode register, MCU external interrupt negative edge triggers, detect the SCL rising edge of clock signal by described MCU external interrupt port earlier, trigger the back reading of data, also the external interrupt port is changed into negative edge and trigger; Negative edge is finished data processing after triggering, and the external interrupt port is changed into rising edge again and triggers.
Described MCU comprises the MCU of PIC series and the MCU of part A RM series.
For the I that lacks that can only detect rising edge of clock signal or negative edge 2The microcontroller of C bus slave controller, technical matters of the present invention is solved by the following technical programs.
This I 2The soft implementation method of C bus slave controller, the mainboard of corresponding master controller is provided with microcontroller MCU chip.
This I 2The characteristics of the soft implementation method of C bus slave controller are:
The MCU chip of the external interrupt port that but the microcontroller MCU chip of described slave controller is the band edge to be triggered;
If described MCU external interrupt port has two, on scl line, increase the not circuit that an output terminal is connected to the external interrupt port of described MCU;
If described MCU external interrupt port has only one, its inside counting device is arranged to minimum, the output terminal of the not circuit that increases on scl line is connected to the input pin of counter, produces to overflow with counter and interrupts substituting the MCU external interrupt;
The scl line of master controller is connected directly to the external interrupt port of described MCU, also be connected to the input end of described not circuit simultaneously, come the SCL clock signal of autonomous controller to be divided into two external interrupt ports that one positive one anti-two-way SCL clock signal is sent to described MCU respectively, positive one road SCL rising edge of clock signal is the negative edge of anti-one road SCL clock signal, the negative edge of positive one road SCL clock signal is anti-one road SCL rising edge of clock signal, detect the SCL rising edge of clock signal of autonomous controller by the external interrupt port of described MCU, the input pin of another external interrupt port or counter detects the negative edge of the SCL clock signal of autonomous controller, can realize the master-slave communication between master controller and this slave controller.
For the I that lacks that can only detect rising edge of clock signal or negative edge 2The microcontroller of C bus slave controller, technical matters of the present invention is solved by following further technical scheme.
Come the SCL rising edge of clock signal of autonomous controller, the detection of negative edge to be, detect the SCL rising edge of clock signal of autonomous controller by the external interrupt port of described MCU, the input pin of another external interrupt port or counter detects the negative edge of the SCL clock signal of autonomous controller, MCU detects the rising edge of SCL signal earlier, detects its negative edge again; If detect negative edge earlier, discardable this signal of MCU, the rising edge of wait SCL signal obtains data then.
Described MCU comprises the MCU of 51 series, the MCU of MSP series and the MCU of risc instruction set.
Be compared with the prior art, MCU of the present invention needn't spend a large amount of time and sample, to prevent misreading of data, and the speed that receives data is adaptive, fully according to the clock frequency work on the scl line, need not speeds match, even corresponding master controller the crystal oscillation frequency less stable, cause the clock frequency on the scl line that bigger deviation is arranged, perhaps master controller work also is to use software simulation, do not use timer to control its traffic rate, the data stability and the reliability that receive on the SDA can not be affected yet.In addition, the data code that adopts the inventive method to receive is shorter than current methods, can save a large amount of program's memory spaces, because size of code reduces, the reliability of system also can improve greatly.Range of application of the present invention is to need soft realization I 2C bus slave controller occasions for communication is as devices such as power supply control single chip computer, RAM, ROM, A/D, D/A, lcd drivers.
Description of drawings
Fig. 1 is I 2Data transmission sequential chart on the C bus;
Fig. 2 is I 2Commencing signal on the C bus and stop signal sequential chart;
Fig. 3 is the connection diagram that the MCU of PIC series adopts the inventive method embodiment;
Fig. 4 is the connection diagram that the MCU of 51 series adopts the inventive method embodiment.
Embodiment
Embodiment one: the MCU of PIC series adopts I 2The soft implementation method of C bus slave controller
Fig. 1,2 meets I 2The I of C bussing technique standard 2Data transmission sequential chart on the C bus and commencing signal, stop signal sequential chart.It is effective when SCL is high level that all SDA go up the data that transmit, master controller transmits the data of an eight bit byte (8Bit), on sda line, transmit successively to lowest order by most significant digit, when SCL is high level, the level of SDA is a significant level, when SCL was low level, the SDA level changed to transmit next data bit.After master controller had transmitted a byte, master controller can discharge sda line, and sda line will be high level under the effect of pull-up resistor.After if slave controller successfully receives the data of a byte, just send response bits and drag down sda line, promptly output low level is confirmed data to master controller on sda line.The level of sda line keeps stable during for high level at scl line, and only saltus step is just legal when scl line is low level.I 2C bussing technique regulation and stipulation: when SCL was high level, the level on the sda line was a low level by the high level saltus step, the expression beginning, and the instruction slave controller begins to receive the data on the bus; And the level on the sda line is a high level by low transition, and expression stops, and the instruction slave controller stops to receive the data on the bus.Scl line rising edge among Fig. 1 and scl line negative edge, the level equalization on the sda line, this is data; Scl line rising edge among Fig. 2 and scl line negative edge, the level generation saltus step on the sda line, this is a control signal.
The connection of this embodiment as shown in Figure 3, described MCU is the I that lacks that can detect rising edge of clock signal and negative edge simultaneously 2The microcontroller of the PIC series of C bus interface has an external interrupt port INT.Detect the SCL rising edge of clock signal and the negative edge of autonomous controller by the external interrupt port of MCU, be the triggering mode register of MCU to be put one by code, MCU external interrupt rising edge triggers, with the zero clearing of triggering mode register, MCU external interrupt negative edge triggers, detect the SCL rising edge of clock signal by MCU external interrupt port earlier, trigger the back reading of data, also the external interrupt port is changed into negative edge and trigger; Negative edge is finished data processing after triggering, and the external interrupt port is changed into rising edge again and triggers.
MCU external interrupt port INT detect autonomous controller the SCL clock signal rising edge, detect the SCL positive transition and trigger to interrupt, read the level on the sda line; Detect the negative saltus step of SCL then and trigger interruption, read the level on the sda line again.Recognition rule is referring to table 1, if two level are inconsistent on the sda line, and low level behind the first high level, this is a commencing signal; High level after elder generation's low level, this is a stop signal.Being that commencing signal is just prepared to receive data, is that stop signal just stops to receive data.After commencing signal detects, just can read the data on the sda line, if two level are consistent, just be defined as data, high level is 1, and low level is 0, and it is collected as a position, and eight positions are a byte.If collected a byte, MCU output low level on sda line is confirmed to master controller as affirmation (Acknowledgment is called for short ACK) signal, obtains stop signal, transmits with regard to no datat on the data line.
Table 1
SDA data during rising edge SDA data during negative edge Judged result
1 0 The start bit
1 1 Data 1
0 0 Data 0
0 1 Position of rest
The MCU of two: 51 series of embodiment adopts I 2The soft implementation method of C bus slave controller
The connection of this embodiment as shown in Figure 4, described MCU is the I that lacks that can only detect rising edge of clock signal or negative edge 2The microcontroller of 51 series of C bus interface has two external interrupt port INT1, INTO, increases the not circuit U that an output terminal is connected to the external interrupt port INT0 of described MCU on scl line.
The scl line of master controller is connected directly to the external interrupt port INT1 of described MCU, also be connected to the input end of described not circuit U simultaneously, come the SCL clock signal of autonomous controller to be divided into two external interrupt port INT1 that one positive one anti-two-way SCL clock signal is sent to described MCU respectively, INT0, positive one road SCL rising edge of clock signal is the negative edge of anti-one road SCL clock signal, the negative edge of positive one road SCL clock signal is anti-one road SCL rising edge of clock signal, detect the SCL rising edge of clock signal of autonomous controller by the external interrupt port INT0 of described MCU, another external interrupt port INT1 detects the negative edge of the SCL clock signal of autonomous controller, can realize the master-slave communication between master controller and this slave controller.
MCU external interrupt port INT0 detect autonomous controller the SCL clock signal rising edge, detect the SCL positive transition and trigger to interrupt, read the level on the sda line; External interrupt port INT1 detects the negative saltus step of SCL and triggers interruption then, reads the level on the sda line again.If two level are inconsistent on the sda line, low level behind the first high level, this is a commencing signal; High level after elder generation's low level, this is a stop signal.Being that commencing signal is just prepared to receive data, is that stop signal just stops to receive data.After commencing signal detects, just can read the data on the sda line, if two level are consistent, just be defined as data, high level is 1, and low level is 0, and it is collected as a position, and eight positions are a byte.If collected a byte, MCU output low level on sda line is confirmed to master controller as ack signal, obtains stop signal, transmits with regard to no datat on the data line.
Above content be in conjunction with concrete preferred implementation to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to the scope of patent protection that the present invention is determined by claims of being submitted to.

Claims (6)

1. I 2The soft implementation method of C bus slave controller, the mainboard of corresponding master controller is provided with microcontroller MCU chip, it is characterized in that:
The MCU chip of the external interrupt port that but described microcontroller MCU chip as slave controller is the band edge to be triggered;
Described slave controller MCU external interrupt port has only one;
The scl line of master controller is connected directly to the external interrupt port of described slave controller MCU, detect the SCL rising edge of clock signal and the negative edge of autonomous controller by the external interrupt port of described slave controller MCU, can realize the master-slave communication between master controller and this slave controller.
2. I as claimed in claim 1 2The soft implementation method of C bus slave controller is characterized in that:
Come the SCL rising edge of clock signal of autonomous controller, the detection of negative edge to be, by code the triggering mode register of MCU is put one, MCU external interrupt rising edge triggers, with the zero clearing of triggering mode register, MCU external interrupt negative edge triggers, detect the SCL rising edge of clock signal by described slave controller MCU external interrupt port earlier, trigger the back reading of data, also the external interrupt port is changed into negative edge and trigger; Negative edge is finished data processing after triggering, and the external interrupt port is changed into rising edge again and triggers.
3. I as claimed in claim 1 or 2 2The soft implementation method of C bus slave controller is characterized in that:
Described slave controller MCU comprises the MCU of PIC series and the MCU of part A RM series.
4. I 2The soft implementation method of C bus slave controller, the mainboard of corresponding master controller is provided with microcontroller MCU chip, it is characterized in that:
The MCU chip of the external interrupt port that but the microcontroller MCU chip of described slave controller is the band edge to be triggered;
If described slave controller MCU external interrupt port has two, on scl line, increase the not circuit that an output terminal is connected to the external interrupt port of described slave controller MCU, the scl line of master controller is connected directly to the external interrupt port of described slave controller MCU, also be connected to the input end of described not circuit simultaneously, come the SCL clock signal of autonomous controller to be divided into two external interrupt ports that one positive one anti-two-way SCL clock signal is sent to described slave controller MCU respectively, positive one road SCL rising edge of clock signal is the negative edge of anti-one road SCL clock signal, the negative edge of positive one road SCL clock signal is anti-one road SCL rising edge of clock signal, detect the SCL rising edge of clock signal of autonomous controller by the external interrupt port of described slave controller MCU, another external interrupt port detects the negative edge of the SCL clock signal of autonomous controller, can realize the master-slave communication between master controller and this controller;
If described slave controller MCU external interrupt port has only one, its inside counting device is arranged to minimum, on scl line, increase the not circuit that an output terminal is connected to the input pin of counter, overflow interruption with the counter generation and substitute the MCU external interrupt, the scl line of master controller is connected directly to the external interrupt port of described slave controller MCU, also be connected to the input end of described not circuit simultaneously, come the SCL clock signal of autonomous controller to be divided into the external interrupt port sum counter input pin that one positive one anti-two-way SCL clock signal is sent to described slave controller MCU respectively, positive one road SCL rising edge of clock signal is the negative edge of anti-one road SCL clock signal, the negative edge of positive one road SCL clock signal is anti-one road SCL rising edge of clock signal, detect the SCL rising edge of clock signal of autonomous controller by the external interrupt port of described slave controller MCU, the input pin of counter detects the negative edge of the SCL clock signal of autonomous controller, can realize the master-slave communication between master controller and this controller.
5. I as claimed in claim 4 2The soft implementation method of C bus slave controller is characterized in that:
Come the SCL rising edge of clock signal of autonomous controller, the detection of negative edge to be, detect the SCL rising edge of clock signal of autonomous controller by the external interrupt port of described slave controller MCU, the input pin of another external interrupt port or counter detects the negative edge of the SCL clock signal of autonomous controller, described slave controller MCU detects the rising edge of SCL signal earlier, detects its negative edge again; If detect negative edge earlier, discardable this signal of described slave controller MCU, the rising edge of wait SCL signal obtains data then.
6. as claim 4 or 5 described I 2The soft implementation method of C bus slave controller is characterized in that:
Described slave controller MCU comprises the MCU of 51 series, the MCU of MSP series and the MCU of risc instruction set.
CNB2006100328242A 2006-01-13 2006-01-13 Controller soft realizing method from I2C bus Expired - Fee Related CN100480923C (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CNB2006100328242A CN100480923C (en) 2006-01-13 2006-01-13 Controller soft realizing method from I2C bus
HK07101832.3A HK1094606A1 (en) 2006-01-13 2007-02-15 Method for implementing i2c bus slave controller by software

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2006100328242A CN100480923C (en) 2006-01-13 2006-01-13 Controller soft realizing method from I2C bus

Publications (2)

Publication Number Publication Date
CN1821914A CN1821914A (en) 2006-08-23
CN100480923C true CN100480923C (en) 2009-04-22

Family

ID=36923322

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006100328242A Expired - Fee Related CN100480923C (en) 2006-01-13 2006-01-13 Controller soft realizing method from I2C bus

Country Status (2)

Country Link
CN (1) CN100480923C (en)
HK (1) HK1094606A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103092175A (en) * 2013-01-21 2013-05-08 杭州华三通信技术有限公司 Controlling method and device for serial clock line (SCL) between inter-integrated circuit (I2C) master equipment and slave equipment

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101465838B (en) * 2007-12-21 2013-01-16 希姆通信息技术（上海）有限公司 Method for implementing self-adapting velocity simulation I2C bus communication
CN102314403B (en) * 2011-08-26 2013-12-11 苏州佳世达电通有限公司 Device and method for identifying I2C (Inter-Integrated Circuit) bus signal by taking MCU (Micro Control Unit) as slave device
CN103440216B (en) * 2013-08-22 2016-12-28 深圳市汇顶科技股份有限公司 A kind of by I2C from the chip of equipment debugging MCU and method
CN105261329B (en) * 2015-11-26 2018-02-16 西安诺瓦电子科技有限公司 More LED display modules management methods
CN108170044A (en) * 2016-12-07 2018-06-15 上海协同科技股份有限公司 The device of time synchronization and its time synchronization implementation method between achievable module
FR3100349B1 (en) * 2019-08-28 2022-07-08 Stmicroelectronics Grand Ouest Sas Communication on I2C bus
CN111045968A (en) * 2019-11-04 2020-04-21 深圳震有科技股份有限公司 Method for realizing CPU slave computer on IIC, intelligent terminal and storage medium
CN111459868B (en) * 2020-03-31 2021-05-18 北京润科通用技术有限公司 Bit identification method, device and system of I2C bus and electronic equipment

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2612172Y (en) * 2003-04-17 2004-04-14 重庆赋仁科技发展有限公司 USSD communicating radio remote controller
CN2702553Y (en) * 2004-06-26 2005-05-25 海信集团有限公司 Television circuit for implementing data upgrade through DVI or VGA terminal multiplexing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2612172Y (en) * 2003-04-17 2004-04-14 重庆赋仁科技发展有限公司 USSD communicating radio remote controller
CN2702553Y (en) * 2004-06-26 2005-05-25 海信集团有限公司 Television circuit for implementing data upgrade through DVI or VGA terminal multiplexing

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
MSP430系列单片机与IIC总线方式的EEPROM接口. 金明，陶维清.仪器仪表用户，第10卷第6期. 2003
MSP430系列单片机与IIC总线方式的EEPROM接口. 金明，陶维清.仪器仪表用户，第10卷第6期. 2003 *
模拟IIC总线从器件的一种方法. 王佳斌，戴在平.华侨大学学报(自然科学版)，第25卷第2期. 2004
模拟IIC总线从器件的一种方法. 王佳斌，戴在平.华侨大学学报(自然科学版)，第25卷第2期. 2004 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103092175A (en) * 2013-01-21 2013-05-08 杭州华三通信技术有限公司 Controlling method and device for serial clock line (SCL) between inter-integrated circuit (I2C) master equipment and slave equipment
CN103092175B (en) * 2013-01-21 2015-04-15 杭州华三通信技术有限公司 Controlling method and device for serial clock line (SCL) between inter-integrated circuit (I2C) master equipment and slave equipment

Also Published As

Publication number Publication date
CN1821914A (en) 2006-08-23
HK1094606A1 (en) 2007-04-04

Similar Documents

Publication Publication Date Title
CN100480923C (en) Controller soft realizing method from I2C bus
CN111427831B (en) Interface implementation method based on power management bus protocol
CN202870808U (en) FPGA realization device of SPI serial port module
CN101770443B (en) Time sequence adjusting method for internal IC (integrated circuit) bus, corresponding device and system thereof
CN103095855B (en) I2C communication interface unit
CN101087235A (en) A FPGA-based multi-functional communication interface conversion device and method
CN103092175B (en) Controlling method and device for serial clock line (SCL) between inter-integrated circuit (I2C) master equipment and slave equipment
CN109062850B (en) Data sending and receiving method of single chip microcomputer
CN103838700A (en) level multiplexing control serial communication device and communication method thereof
CN101727422A (en) Method and system for controlling unibus equipment
CN101208682B (en) Slave device with latched request for service
CN104199795A (en) Bus framework
US7353300B2 (en) Apparatus to improve the firmware efficiency for a multiframe serial interface
CN101826068A (en) Method for hot-plugging PCI-E device and application thereof
CN101339542A (en) Data transmission device, control circuit chip and operation mode control method
CN105354157A (en) Method, device and system for configuring IIC (Inter-Integrated Circuit) device
CN111538626A (en) Method for releasing from I2C equipment
CN201378316Y (en) Universal input/output interface extension circuit and mobile terminal with same
US6874047B1 (en) System and method for implementing an SMBus/I2C interface on a network interface card
CN109684251A (en) A kind of processing method of chip I/O data and a kind of chip
CN101853232A (en) Extensible adapter
CN210924562U (en) Backboard communication device
CN102955545A (en) Computer
CN109887259B (en) Single-wire transmission device and method
CN201489527U (en) Chip for converting PCI Express interface into PCI interface

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1094606

Country of ref document: HK

C14 Grant of patent or utility model
GR01 Patent grant
REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1094606

Country of ref document: HK

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090422

Termination date: 20150113

EXPY Termination of patent right or utility model