CN202870808U - FPGA realization device of SPI serial port module - Google Patents
FPGA realization device of SPI serial port module Download PDFInfo
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- CN202870808U CN202870808U CN 201220320399 CN201220320399U CN202870808U CN 202870808 U CN202870808 U CN 202870808U CN 201220320399 CN201220320399 CN 201220320399 CN 201220320399 U CN201220320399 U CN 201220320399U CN 202870808 U CN202870808 U CN 202870808U
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Abstract
The utility model provides an FPGA (Field Programmable Gate Array) realization device of an SPI (Serial Peripheral Interface) serial port module, and belongs to the field of interface communication. The device takes the FPGA as a hardware platform, and comprises an external parallel interface module (1), a data receiving FIFO (first input, first output) module (2), a communication parameter configuration module (3), a data transmitting FIFO module (4), a serial data receiving, command parsing and interrupt generation module (5), a serial clock generation and transmitting-receiving control module (6) and a serial data transmitting processing module (7). According to the utility model, automatic receiving and transmitting of SPI communication data can be realized, and an SPI serial port can be rapidly configured by the exterior, so as to complete dynamic changes of the serial port communication rate, the clock mode, the working manner, the data length and the like. The design can be expanded to a multipath SPI data communication interface, which compensates the defects of complication in operation and limited functions of a build-in SPI hardware serial port of a conventional treatment and control device on one hand, and releases a singlechip and a DSP (Digital Signal Processor) from frequent data query or data interrupt on the other hand, so as to put more effort into other function control.
Description
Technical field
The utility model relates to the interface communication field, particularly relates to the device based on the FPGA realization of a kind of Serial Peripheral Interface (SPI) (SPI) communication.
Background technology
Serial Peripheral Interface (SPI) (SPI) is the serial input/delivery outlet of a high-speed synchronous.SPI is generally used for communicating between processor and external peripheral and other processor.A lot of new devices such as LCD module, FLASH, ADC, eeprom memory and clock chip etc. have all adopted the SPI interface.But in actual development is used, if master controller without the SPI interface or need to a plurality of peripheral communications with SPI interface, will simulate by software with the I/O mouth of master controller, this has limited to a great extent its application and has made troubles to data transmission.
Current, become a kind of main flow (such as DSP+FPGA, MCU+FPGA etc.) based on the system architecture of principal and subordinate processor structure.The FPGA advantage is that mainly it has very strong dirigibility, and namely the concrete logic function of its inside can configure as required, and is very convenient to modification and the maintenance of circuit.The IP kernel that the FPGA realization of tradition SPI interface often adopts producer to provide is realized, though this method can satisfy the SPI communicating requirement substantially, designs underaction, is unfavorable for Function Extension.
The utility model content
The purpose of this utility model provides a kind of FPGA implement device of SPI serial port module, this device is take FPGA as hardware platform, adopt hardware to realize that the SPI interface expands, can realize automatic reception and transmission to the SPI communication data, also can carry out rapid configuration to this SPI serial ports by the outside, thereby finish the dynamic change of serial communication speed, clock module, working method, data length etc.This design is extendible to be multichannel SPI data communication interface, on the one hand remedied that the SPI hardware operation of serial-port that conventional processing control device (single-chip microcomputer, DSP etc.) carries is loaded down with trivial details, the deficiency of function limitation, also single-chip microcomputer, DSP are freed interrupting from frequently data query or data on the other hand, thereby drop into more energy in other function control.This device can satisfy the demand of SPI communication, and design is more flexible again, is more conducive to Function Extension.
The technical scheme that the utility model or invention are adopted is as follows: a kind of FPGA implement device of SPI serial port module, it is characterized in that: comprise external parallel interface module 1, data receiver fifo module 2, communication parameter configuration module 3, data send fifo module 4, Serial data receiving, command analysis and interruption generation module 5, serial clock produce and transmitting-receiving control module 6, serial data transmission processing module 7.
Described external parallel interface module 1 sends fifo module 4 with data receiver fifo module 2, communication parameter configuration module 3, data respectively and links to each other;
Described data receiver fifo module 2 links to each other with Serial data receiving, command analysis and interruption generation module 5 again;
Described communication parameter configuration module 3 produces with serial clock again and transmitting-receiving control module 6 links to each other;
Described data send fifo module 4 and link to each other with serial data transmission processing module 7 again;
Described Serial data receiving, command analysis and interruption generation module 5, serial clock produce and transmitting-receiving control module 6, and serial data transmission processing module 7 links to each other successively.
As preferably, also comprise the condition line SPI_STATUS12 that links to each other with serial clock generation and transmitting-receiving control module 6.
As preferably, described external parallel interface module 1 links to each other with processing controller 8.
As preferably, described Serial data receiving, command analysis and interrupt generation module 5 and link to each other with main frame input/slave output data line SPISOMI9.
As preferably, described serial clock produces and transmitting-receiving control module 6 links to each other with serial time clock line SPICLK10, slave gating signal line SPI_CS11 respectively again.
As preferably, described serial data transmission processing module 7 links to each other with main frame output/slave input data line SPISIMO13 again.
Compared with prior art, the beneficial effects of the utility model are:
1, this design is extendible is multichannel SPI data communication interface, on the one hand remedied that the SPI hardware operation of serial-port that conventional processing control device (single-chip microcomputer, DSP etc.) carries is loaded down with trivial details, the deficiency of function limitation, also single-chip microcomputer, DSP are freed interrupting from frequently data query or data on the other hand, thereby drop into more energy in other function control.
2, this device can satisfy the demand of SPI communication, and design is more flexible again, is more conducive to Function Extension.
Description of drawings
Fig. 1 is principle of device schematic diagram of the present utility model.
Fig. 2 is the wherein application schematic diagram of an embodiment of the utility model.
Fig. 3 is SPI holotype data receiver sequential chart embodiment illustrated in fig. 2.
Fig. 4 is SPI holotype data transmission timing figure embodiment illustrated in fig. 2.
Fig. 5 is SPI holotype data receiver process flow diagram embodiment illustrated in fig. 2.
Fig. 6 is SPI holotype data transmission flow figure embodiment illustrated in fig. 2.
Embodiment
Below in conjunction with drawings and Examples the utility model is further described.
As shown in Figure 1, a kind of FPGA implement device of SPI serial port module, comprise external parallel interface module 1, data receiver fifo module 2, communication parameter configuration module 3, data send fifo module 4, Serial data receiving, command analysis and interruption generation module 5, serial clock produces and transmitting-receiving control module 6, serial data transmission processing module 7.
Described external parallel interface module 1 sends fifo module 4 with data receiver fifo module 2, communication parameter configuration module 3, data respectively and links to each other;
Described data receiver fifo module 2 links to each other with Serial data receiving, command analysis and interruption generation module 5 again;
Described communication parameter configuration module 3 produces with serial clock again and transmitting-receiving control module 6 links to each other;
Described data send fifo module 4 and link to each other with serial data transmission processing module 7 again;
Described Serial data receiving, command analysis and interruption generation module 5, serial clock produce and transmitting-receiving control module 6, and serial data transmission processing module 7 links to each other successively.
Wherein, data receiver fifo module 2 and data send fifo module 4 and are used for being the FIFO that receives the transmission data.Communication parameter configuration module 3 is for the various parameters of processing controller 8 read-write configuration SPI.External parallel interface module 1 responsible and existing external treatment controller 8(such as single-chip microcomputer, DSP etc.) carry out data interaction.Serial data receiving, command analysis and interruption generation module 5 are finished Serial data receiving, communications command is resolved and produce look-at-me notifier processes controller 8 carries out the data receiver operation.Serial clock produces and transmitting-receiving control module 6 is used for occuring clock signal under the holotype, simultaneously function is carried out in the reception of data or transmission and switches.Serial data transmission processing module 7 is responsible for the data serial that walks abreast is into spread out of, the processing that complete paired data sends.
As shown in Figure 2, also comprise the condition line SPI_STATUS 12 that links to each other with serial clock generation and transmitting-receiving control module 6.
Described external parallel interface module 1 links to each other with processing controller 8.
Described Serial data receiving, command analysis and interruption generation module 5 link to each other with main frame input/slave output data line SPISOMI 9.
Described serial clock produces and transmitting-receiving control module 6 links to each other with serial time clock line SPICLK 10, slave gating signal line SPI_CS 11 respectively again.
Described serial data transmission processing module 7 links to each other with main frame output/slave input data line SPISIMO 13 again.
As shown in Figure 3 and Figure 4, the SPI serial line interface use 4 lines can with multiple standards central component indirect interface: serial time clock line SPICLK 10, main frame output/slave input data line SPISIMO 13, the slave gating signal line SPI_CS 11 of main frame input/slave output data line SPISOMI 9 and Low level effective.
Serial time clock line SPICLK 10 is the host clock line, is an input of slave, for the sending and receiving of main frame input/slave output data line SPISOMI 9 data provides synchronizing clock signals.The phase place of clock (CPHA) and polarity (CPOL) can be used for controlling data transfer.The stationary state of CPOL=" 0 " expression SCLK is low level, and CPOL=" 1 " represents that then the stationary state of SCLK is high level.Clock phase (CPHA) can be used for selecting two kinds of different data-transmission modes.If CPHA=" 0 ", data first SCLK edge after signal SPI_CS statement is effective.And when CPHA=" 1 ", second the SCLK edge of data after signal SPI_CS statement just effectively.Therefore, clock phase and the polarity of SPI equipment must unanimously just can communicate in main frame and the slave.
SPI has two kinds of mode of operations: holotype and from pattern.Be operated under the holotype, no matter be to send or receive data, serial time clock line SPICLK 10 provides clock for whole serial communication network.When serial data sent, that at first send was highest significant position (MSB), the transmission (SPISIMO) of 1 corresponding 1 bit data of effect of clock signal and the reception (SPISOMI) of other 1 bit data.Be operated under pattern, no matter be to send or receive data, must under serial time clock line SPICLK 10 signal functions, stop, and slave gating signal line SPI_CS 11 signals be effectively essential always.1 typical SPI system comprises a main MCU and 1 or several from peripheral components.
The utility model carries out the transmitting-receiving of SPI data in this illustrated embodiment by a default data traffic rate (5Mbps), clock module (without the negative edge of phase delay), master/slave working method (main SPI pattern).Can carry out by 8 pairs of these modules of external treatment controller the dynamic-configuration of various messaging parameters, to adapt to the situations such as different traffic rates, clock module, working method, data length.Configure complete after, can begin the transmitting-receiving process of SPI data.
Increased the handshake line of a master/slave SPI side in the present embodiment, namely condition line SPI_STATUS 12, and this signal wire is drawn from the side to be low level when sending data from SPI side, and is set to high level from the side from SPI side's receive data the time.
As shown in Figure 5, when the moment that sends data from SPI side arrives, this device detects condition line SPI_STATUS12 and is " low ", then serial clock generation and transmitting-receiving control module start receive logic immediately, externally export serial time clock line SPICLK 10 signals and gating signal line SPI_CS 11 signals, simultaneously constantly carry out data sampling at serial time clock line SPICLK 10 rising edges, and serial data is carried out respective cache.
When sampled data consists of a complete bytes, the data of receiving are deposited in " data receiver FIFO " by receiver module, simultaneously the special field in the serial data is carried out protocol analysis.Process is as follows: after retrieval receives data synchronous head byte " AAH AAH " first, the complete bytes that receives is later carried out+1 counting to be processed, after serial data total length byte is received in retrieval again, judge whether paid-in total amount of byte reaches serial data total length value.If reach receive data total length value, represent that then a frame data order receives complete, put out " order data receives complete " sign by receiver module herein; Simultaneously, when the rising edge that detects condition line SPI_STATUS12 arrives, provide the complete interrupt identification signal of data receiver int_rxd and in time interrupt processing controller 8, notice peripheral control unit reading out data is processed, just interrupt once and needn't whenever receive 1 byte, avoided master routine frequently to be interrupted.
At present, the reception FIFO of this device and the transmission FIFO degree of depth all are set as 2048 bytes, can a large amount of communication data of buffer memory, and can be with the data cover of before having received, external treatment controller 8 can be after handling other critical task, carry out again reading and subsequent treatment of SPI data, and needn't worry that the SPI data that received can lose.
As shown in Figure 6, when needs send the SPI data, all data that external treatment controller 8 will need to send write in " data send fifo module 4 " of this device successively, after again this being installed another address location and writes " start send order ", can send data by the log-on data sending module.Whether these device real-time judgment data send FIFO is empty, if data then immediately externally output string row clock SPICLK signal and gating signal SPI_CS are arranged in the FIFO, and constantly the data of taking out are sent at the negative edge of SPICLK, that at first send is highest significant position (MSB).Namely for master routine, write the data that all need to send to a particular address exactly, write again one and start the transmission that the transmission order can be finished total data automatically, need not to carry out transmission flow control.
In addition, in order to guarantee the accuracy of code, at first should write corresponding test vector as the input stimulus of this SPI module according to the functions of modules demand, then through checking the Output rusults of module, judge whether the various functions of this SPI device is correct.
When setting up test platform, the model simulation according to the module that sends, is set up the main SPI number formulary of simulation according to the module that sends from the SPI number formulary simultaneously, will receive/send data content and compare, verify.Under the assistant analysis of simulation software, obtained correct result.
Simultaneously, after the EDIF file of whole project engineering file after comprehensive submitted to ISE and carry out layout, wiring, the mcs file that generates is downloaded among the fpga chip XCV600E of XILINX company and move, through actual test, can reach this system and require the performance that realizes, have very strong practicality.
The above only is preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.
Claims (6)
1. the FPGA implement device of a SPI serial port module is characterized in that:
Comprise external parallel interface module (1), data receiver fifo module (2), communication parameter configuration module (3), data send fifo module (4), Serial data receiving, command analysis and interruption generation module (5), serial clock produces and transmitting-receiving control module (6), serial data transmission processing module (7);
Described external parallel interface module (1) sends fifo module (4) with data receiver fifo module (2), communication parameter configuration module (3), data respectively and links to each other;
Described data receiver fifo module (2) links to each other with Serial data receiving, command analysis and interruption generation module (5) again;
Described communication parameter configuration module (3) produces with serial clock again and transmitting-receiving control module (6) links to each other;
Described data send fifo module (4) and link to each other with serial data transmission processing module (7) again;
Described Serial data receiving, command analysis and interruption generation module (5), serial clock produce and transmitting-receiving control module (6), and serial data transmission processing module (7) links to each other successively.
2. the FPGA implement device of a kind of SPI serial port module according to claim 1 is characterized in that:
Also comprise the condition line SPI_STATUS(12 that links to each other with serial clock generation and transmitting-receiving control module (6)).
3. the FPGA implement device of a kind of SPI serial port module according to claim 2 is characterized in that:
Described external parallel interface module (1) links to each other with processing controller (8).
4. the FPGA implement device of a kind of SPI serial port module according to claim 2 is characterized in that:
Described Serial data receiving, command analysis and interruption generation module (5) and main frame input/slave output data line SPISOMI(9) link to each other.
5. the FPGA implement device of a kind of SPI serial port module according to claim 2 is characterized in that:
Described serial clock produce and transmitting-receiving control module (6) again respectively with serial time clock line SPICLK(10), slave gating signal line SPI_CS(11) link to each other.
6. the FPGA implement device of a kind of SPI serial port module according to claim 2 is characterized in that:
Described serial data transmission processing module (7) again with main frame output/slave input data line SPISIMO(13) link to each other.
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| CN 201220320399 CN202870808U (en) | 2012-07-04 | 2012-07-04 | FPGA realization device of SPI serial port module |
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| CN 201220320399 CN202870808U (en) | 2012-07-04 | 2012-07-04 | FPGA realization device of SPI serial port module |
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Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101447154B1 (en) | 2013-11-12 | 2014-10-06 | 엘아이지넥스원 주식회사 | Universal spi core using fpga and operation method thereof |
| KR101506279B1 (en) | 2013-11-12 | 2015-03-26 | 엘아이지넥스원 주식회사 | Universal spi core using fpga |
| CN104503934A (en) * | 2014-12-02 | 2015-04-08 | 天津国芯科技有限公司 | Extendable serial transmission device |
| CN105550147A (en) * | 2015-12-11 | 2016-05-04 | 上海华冠电子设备有限责任公司 | SPI bus expansion system and communication method therefor |
| CN106445853A (en) * | 2016-08-30 | 2017-02-22 | 天津天地伟业数码科技有限公司 | Transformation method of SPI (Serial Peripheral Interface) and UART (Universal Asynchronous Receiver/Transmitter) interface on the basis of FPGA (Field Programmable Gate Array) |
| CN106444535A (en) * | 2016-11-18 | 2017-02-22 | 威科达（东莞）智能控制有限公司 | Motion controller and control method |
| CN106776402A (en) * | 2016-12-19 | 2017-05-31 | 中国电子科技集团公司第二十研究所 | A kind of SCM Based serial communication controlling system and method |
| CN107677869A (en) * | 2017-09-25 | 2018-02-09 | 优利德科技(中国)有限公司 | A kind of apparatus and method for improving message transmission rate between SPI interface ADC and MCU |
| CN107704407A (en) * | 2017-11-02 | 2018-02-16 | 郑州云海信息技术有限公司 | A kind of system and method for being used for data processing between SPI and UART |
| CN107967231A (en) * | 2017-12-07 | 2018-04-27 | 天津天地伟业机器人技术有限公司 | A kind of system of Spi Multipexers full duplex serial ports |
| CN108153698A (en) * | 2017-11-15 | 2018-06-12 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | Data interactive method |
| CN109408426A (en) * | 2018-10-23 | 2019-03-01 | 四川九洲电器集团有限责任公司 | A kind of agile and all-purpose serial communication method and system |
| CN111522770A (en) * | 2020-04-27 | 2020-08-11 | 成都汇蓉国科微系统技术有限公司 | FPGA (field programmable Gate array) -based parameterized configured SPI (Serial peripheral interface) controller and use method |
| CN111666248A (en) * | 2020-06-16 | 2020-09-15 | 中国北方车辆研究所 | RS422 serial port communication control system and method based on FPGA |
| CN111817743A (en) * | 2020-07-08 | 2020-10-23 | 广东奥普特科技股份有限公司 | Parallel port communication circuit |
| CN112035399A (en) * | 2020-08-26 | 2020-12-04 | 天津津航计算技术研究所 | FPGA-based SPI slave module implementation method |
| CN116401188A (en) * | 2023-03-30 | 2023-07-07 | 昆易电子科技(上海)有限公司 | FPGA-based processing method, circuit and electronic equipment |
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- 2012-07-04 CN CN 201220320399 patent/CN202870808U/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101506279B1 (en) | 2013-11-12 | 2015-03-26 | 엘아이지넥스원 주식회사 | Universal spi core using fpga |
| KR101447154B1 (en) | 2013-11-12 | 2014-10-06 | 엘아이지넥스원 주식회사 | Universal spi core using fpga and operation method thereof |
| CN104503934A (en) * | 2014-12-02 | 2015-04-08 | 天津国芯科技有限公司 | Extendable serial transmission device |
| CN105550147A (en) * | 2015-12-11 | 2016-05-04 | 上海华冠电子设备有限责任公司 | SPI bus expansion system and communication method therefor |
| CN105550147B (en) * | 2015-12-11 | 2018-04-24 | 上海仪电楼宇科技有限公司 | A kind of spi bus expansion system and its means of communication |
| CN106445853A (en) * | 2016-08-30 | 2017-02-22 | 天津天地伟业数码科技有限公司 | Transformation method of SPI (Serial Peripheral Interface) and UART (Universal Asynchronous Receiver/Transmitter) interface on the basis of FPGA (Field Programmable Gate Array) |
| CN106444535B (en) * | 2016-11-18 | 2019-12-03 | 威科达（东莞）智能控制有限公司 | A kind of motion controller and control method |
| CN106444535A (en) * | 2016-11-18 | 2017-02-22 | 威科达（东莞）智能控制有限公司 | Motion controller and control method |
| CN106776402A (en) * | 2016-12-19 | 2017-05-31 | 中国电子科技集团公司第二十研究所 | A kind of SCM Based serial communication controlling system and method |
| CN107677869A (en) * | 2017-09-25 | 2018-02-09 | 优利德科技(中国)有限公司 | A kind of apparatus and method for improving message transmission rate between SPI interface ADC and MCU |
| CN107704407A (en) * | 2017-11-02 | 2018-02-16 | 郑州云海信息技术有限公司 | A kind of system and method for being used for data processing between SPI and UART |
| CN108153698A (en) * | 2017-11-15 | 2018-06-12 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | Data interactive method |
| CN107967231A (en) * | 2017-12-07 | 2018-04-27 | 天津天地伟业机器人技术有限公司 | A kind of system of Spi Multipexers full duplex serial ports |
| CN109408426A (en) * | 2018-10-23 | 2019-03-01 | 四川九洲电器集团有限责任公司 | A kind of agile and all-purpose serial communication method and system |
| CN109408426B (en) * | 2018-10-23 | 2020-06-26 | 四川九洲电器集团有限责任公司 | Flexible and universal serial communication method and system |
| CN111522770A (en) * | 2020-04-27 | 2020-08-11 | 成都汇蓉国科微系统技术有限公司 | FPGA (field programmable Gate array) -based parameterized configured SPI (Serial peripheral interface) controller and use method |
| CN111522770B (en) * | 2020-04-27 | 2022-03-11 | 成都汇蓉国科微系统技术有限公司 | FPGA (field programmable Gate array) -based parameterized configured SPI (Serial peripheral interface) controller and use method |
| CN111666248A (en) * | 2020-06-16 | 2020-09-15 | 中国北方车辆研究所 | RS422 serial port communication control system and method based on FPGA |
| CN111817743A (en) * | 2020-07-08 | 2020-10-23 | 广东奥普特科技股份有限公司 | Parallel port communication circuit |
| CN112035399A (en) * | 2020-08-26 | 2020-12-04 | 天津津航计算技术研究所 | FPGA-based SPI slave module implementation method |
| CN116401188A (en) * | 2023-03-30 | 2023-07-07 | 昆易电子科技(上海)有限公司 | FPGA-based processing method, circuit and electronic equipment |
| CN116401188B (en) * | 2023-03-30 | 2024-04-12 | 昆易电子科技(上海)有限公司 | FPGA-based processing method, circuit and electronic equipment |
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