KR101447154B1 - Universal spi core using fpga and operation method thereof - Google Patents

Universal spi core using fpga and operation method thereof Download PDF

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Publication number
KR101447154B1
KR101447154B1 KR1020130136899A KR20130136899A KR101447154B1 KR 101447154 B1 KR101447154 B1 KR 101447154B1 KR 1020130136899 A KR1020130136899 A KR 1020130136899A KR 20130136899 A KR20130136899 A KR 20130136899A KR 101447154 B1 KR101447154 B1 KR 101447154B1
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South Korea
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signal
spi
core
communication
spi core
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KR1020130136899A
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Korean (ko)
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홍준호
온새움
전창규
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엘아이지넥스원 주식회사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Abstract

A method to operate a universal SPI core using FPGA is disclosed. According to the present invention, the SPI core receives a control signal to specify various settings from a corresponding apparatus having an SPI core to set various setting values including a clock polarity setting signal (CPOL) or a phase setting signal (CPHA), thereby the corresponding apparatus can directly specify the various settings.

Description

TECHNICAL FIELD [0001] The present invention relates to a general-purpose SPI core using an FPGA,

The present invention relates to a general-purpose SPI core operating method, and more particularly, to a general-purpose SPI core operating method that can be implemented using an FPGA.

The Serial to Peripheral Interface (SPI) is a synchronous serial data connection standard that operates in architecture full duplex communication mode, and is a serial peripheral interface. SPI is one of the serial communication methods used to transfer data at high speed between CPU and multiple CPUs or between CPU and many peripheral devices. In order to use SPI communication, devices operate as one of master and slave with built-in SPI core (SPI Core) to support SPI communication. Master uses SPI communication with several slave devices and individual chip select lines Can be performed. That is, a plurality of slaves can be connected to one master, and the master performs communication in a form of selecting one of a plurality of slaves using a chip select line.

The SPI is a four-wire serial communication interface that communicates over four signal lines and specifies four logic signals corresponding to four signal lines. The four logic signals are SCLK (Serial Clock or CLK), MOSI (Mater Output Slave Input or SDI, DI, DIN, SI), MISO (Maternal Input Slave Output or SDO, DO, DOUT, SO) SS, CSB, CSN, STE).

SCLK is a clock signal for synchronization between the master and the slave, generated by the master and transmitted to the slave. MOSI and MISO are signals for data transmission and reception, and MOSI is a signal output from a master and input to a slave. MISO is a signal that is output from the slave and input to the master as opposed to MOSI. And CS is a slave selection signal as a slave selection signal as described above.

1 is a diagram showing the concept of a clock polarity setting signal and a phase setting signal of SPI communication.

The SPI control register included in the SPI core is configured to set the clock polarity setting signal CPOL and the phase setting signal CPHA. In this case, the clock polarity setting signal CPOL is a value for designating the polarity of the clock, and the phase setting signal CPHA is a value for specifying the clock phase. If CPOL = 1, ), It starts at HIGH. When CPOL = 0, the synchronous clock (SCK) starts at LOW. That is, the bit for selecting the start of the synchronous clock signal SCK is the clock polarity setting signal CPOL.

For example, as shown in FIG. 1, when the phase setting signal CPHA is 1 and the clock polarity is 1, When the set signal CPOL is 1, a data latch occurs at the rising edge. When the phase setting signal CPHA is 1 and the clock polarity setting signal CPOL is 0, data latch occurs at the falling edge, If the signal CPHA is 0 and the clock polarity setting signal CPOL is 1 on the falling edge, if the phase setting signal CPHA is 0 and the clock polarity setting signal CPOL is 0, the data latch occurs at the rising edge.

However, in the conventional SPI core, the value of the clock polarity setting signal (CPOL) and the phase setting signal (CPHA) of the control register are designed in advance as one value. Therefore, since the SPI communication between the devices having different values of the clock polarity setting signal CPOL and the phase setting signal CPHA can not be performed, the values of the clock polarity setting signal CPOL and the phase setting signal CPHA are There is a problem that the same SPI core needs to be redesigned. In other words, it is troublesome to always modify the SPI core to support SPI communication between devices in which the values of the clock polarity setting signal (CPOL) and the phase setting signal (CPHA) do not match.

It is an object of the present invention to provide an operation method of an SPI core implemented in an FPGA so that a set value can be changed corresponding to use conditions of various SPI devices.

According to another aspect of the present invention, there is provided a method of operating an SPI core, the method comprising: receiving a signal from an SPI core having an SPI logic unit, a counter, and a synchronous clock generator, The SPI core receiving a control signal including a clock polarity setting signal and a phase setting signal from the apparatus and determining a level of the clock polarity setting signal; Setting an initial level of a synchronous clock for synchronization between the SPI core and at least one other device communicating with the device according to the level of the clock signal; A standby state in which the SPI core initializes a setting for performing communication between the apparatus and the at least another apparatus; Determining whether the SPI core is a signal for activating communication of the SPI core; In response to a selection input signal applied at the device for selecting the SPI core to communicate with the device and to perform another SPI communication with the SPI core, And toggling the synchronous clock whose initial level is set; Determining the sampling phase of data to be transmitted by the SPI core to the at least one other device according to the level of the phase setting signal and transmitting and receiving data with the at least one other device in accordance with the determined sampling phase; Determining whether the number of data transmitted and received by the SPI core reaches a value of the number of transmissions specified by the control signal; The SPI core activating a transmission completion signal to 1 and outputting the transmission completion signal to the device when the number of transmitted and received data reaches the number of transmission times, and deactivating the activated slave selection signal; Determining whether the SPI core is to deactivate the SPI communication in response to the control signal; And re-entering the idle state if the SPI communication is deactivated; .

Initializing a unit communication completion signal indicating completion of a unit communication every time communication of a predetermined unit is completed with a transmission number value for setting a number of times of performing transmission in a predetermined unit; And deactivating at least one slave selection signal for selecting one of the at least one other device to perform SPI communication with the device; And a control unit.

Wherein the step of determining whether the communication activation signal is a signal for activating the communication comprises activating a selection input signal for activating one of the at least one slave selection signal and applying a counter for activating the counter and the synchronous clock generation unit, And the logic execution signal for activating the SPI logic unit are all activated.

Wherein the SPI core activates a unit communication completion signal indicating that the unit communication is completed and maintains the transmission completion signal in an inactive state when the number of the transmitted and received data is less than the number of transmissions, And further comprising:

Wherein the step of determining whether the SPI communication is to be deactivated comprises: the SPI core deactivates the select input signal, deactivates the counter and clock execution signal and the logic execution signal to zero, and initializes the count values stored in the counter It is determined that the SPI communication is inactivated when the counter initialization signal for activating the counter initialization signal to 1 is activated.

The method of operating the SPI core includes: maintaining the unit communication completion signal in an active state and maintaining the transmission completion signal in an inactive state if the SPI communication is not inactivated; And further comprising:

The method of operating the SPI core includes counting a reset count value among the count values regardless of an operation state of the current SPI core when the SPI core is initially driven or a reset signal is applied from the device to the SPI core, Determining whether the time is reached; And further comprising:

Therefore, in the method of operating the general-purpose SPI core using the FPGA of the present invention, the SPI core receives a control signal designating various settings from a corresponding device having an SPI core and outputs a clock polarity setting signal CPOL or a phase setting signal CPHA), so that the corresponding device can directly designate various settings. Therefore, it is possible to have versatility in comparison with a conventional SPI core that operates only in accordance with a predetermined set value. Also, since it is implemented in FPGA, it can be easily included in various devices and can be easily modified later.

1 is a diagram showing the concept of a clock polarity setting signal and a phase setting signal of SPI communication.
2 shows a structure of an SPI core according to an embodiment of the present invention.
3 is a detailed view showing the operation of each configuration of the SPI core of FIG.
4 illustrates a method of operating an SPI core in accordance with an embodiment of the present invention.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention can be implemented in various different forms, and is not limited to the embodiments described. In order to clearly describe the present invention, parts that are not related to the description are omitted, and the same reference numerals in the drawings denote the same members.

Throughout the specification, when an element is referred to as "including" an element, it does not exclude other elements unless specifically stated to the contrary. The terms "part", "unit", "module", "block", and the like described in the specification mean units for processing at least one function or operation, And a combination of software.

FIG. 2 shows a structure of an SPI core according to an embodiment of the present invention, for example, an SPI core 100 of a master device.

Referring to FIG. 2, the SPI core 100 includes an SPI logic unit 110, a counter 120, and a synchronous clock generation unit 130. The SPI core 100 receives a clock signal CLK, a reset signal RST, a control signal CTRL and data DATA from a corresponding device including the SPI core 100 and performs communication through SPI communication The slave selection signal CS, the synchronous clock SCLK and the transmission data SPI_WRITE to the SPI core 100 of the slave device to be received and receives the reception data signal SPI_READ from the SPI core 100 of the slave device do. Then, it acquires the data (DATA) from the received data (SPI_READ) and transmits it to the corresponding device. The control signal CTRL is not a single signal but a combination of a plurality of signals. Particularly, the control signal CTRL is a signal for designating various settings of the SPI core 100 and includes a clock polarity setting signal CPOL The value of the clock polarity setting signal CPOL or the phase setting signal CPHA of the SPI core 100 including the CPHA value can be directly designated by the corresponding device.

In the SPI core 100, the synchronous clock generator 130 generates a synchronous clock SCLK, which is a clock for providing synchronization between the master device and the SPI core 100 of the slave device. The counter 120 shifts the data DATA stored in the SPI logic unit 110 and generates a count value CNT for designating the sampling timing of the data DATA. The SPI logic unit 110 sets the output according to the control signal CTRL and the counter value CNT of the counter 120.

Accordingly, the SPI core 100 of FIG. 2 receives the control signal CTRL from the corresponding device and outputs various setting values including the values of the clock polarity setting signal CPOL and the phase setting signal CPHA to the corresponding devices It is possible to have versatility in comparison with a conventional SPI core that operates only in accordance with a predetermined set value.

3 is a detailed view showing the operation of each configuration of the SPI core of FIG.

3, the SPI core 100 receives the clock signal CLK and the reset signal RST from the corresponding device having the SPI core 100 . The clock signal CLK is a clock signal used by the SPI core 100 and serves as a reference of the operation timing of the SPI core 100. [ The reset signal RST is a signal for initializing the set value and data of the SPI core 100. While the SPI core 100 receives the selection input signal CE from the corresponding device. The SPI core 100 activates a slave selection signal CS for selecting a slave in response to the selection input signal CE. The SPI core 100 of the master device can perform SPI communication with a plurality of slave devices and the master device needs to select a slave device that desires to perform communication among the plurality of slave devices. The master device transmits the selection input signal CE to the SPI core 100. The SPI core 100 responds to the selection input signal CE to output a plurality of slave selection signal lines As a slave selection signal CS. The SPI core of the slave device connected to the slave selection signal line in which the slave selection signal CS is activated is activated.

Meanwhile, the counter 120 of the SPI core 100 receives the counter and clock execution signal (EXEC_CNT_N_SCLK_EN) and the counter initialization signal (EXEC_CNT_CLR) as the control signal CTRL from the corresponding device. The counter and the clock execution signal (EXEC_CNT_N_SCLK_EN) are drive signals for causing the counter 120 to execute. When the counter execution signal (EXEC_CNT_N_SCLK_EN) is applied, the counter 120 is driven to start counting and output a counter value (CNT). The counter initializing signal EXEC_CNT_CLR is a signal for initializing a value stored in a register provided in the counter 120, that is, a count value CNT. 3, the counter 120 includes a bit counter 121 and a reset counter 122. Each of the bit counter 121 and the reset counter 122 includes a register to store a count value . The count value CNT output from the counter 120 is a bit count value BIT_CNT and a reset counter value RST_CNT output from the bit counter 121 and the reset counter 122, Is a value stored in each of the registers of the counter 122.

Here, the bit count value BIT_CNT is a count value used for determining the data shift and the sampling timing in the SPI logic unit 110, and the count value is incremented every rising edge of the clock CLK. The reset count value RST_CNT is a count value for counting the stabilization period until the SPI core 100 is initially driven or reset when the SPI core 100 is reset.

The synchronous clock generating unit 130 receives the counter and clock execution signal EXEC_CNT_N_SCLK_EN and the clock polarity setting signal CPOL from the corresponding device and outputs the synchronous clock signal SCLK to the SPI core of the slave device. The counter and clock execution signal (EXEC_CNT_N_SCLK_EN) is a driving signal for causing the counter 120 to execute and a driving signal for causing the synchronous clock generating section 130 to execute simultaneously. That is, the counter and clock execution signal (EXEC_CNT_N_SCLK_EN) simultaneously drives the counter 120 and the synchronous clock generator 130. The clock polarity setting signal CPOL is a signal for controlling the polarity of the synchronous clock signal SCLK as described above. The synchronous clock generating unit 130 generates a synchronous clock signal SCCLK, which is output in response to the clock polarity setting signal CPOL, Determines whether the clock signal SCLK starts at the high level or the low level and outputs the clock signal SCLK to the slave device.

The SPI logic unit 110 receives the phase setting signal CPHA, the transmission count value BCNT, the logic execution signal EXEC_SPI_LOGIC and the input data DATA_IN from the corresponding device and outputs the output data DATA_OUT to the corresponding device . The phase setting signal CPHA is a signal for adjusting the data synchronization timing, and is a signal for setting the phase of the timing for sampling data. The transmission number value BCNT is a signal for setting the number of times of performing transmission in a predetermined unit (for example, byte). The logic execution signal EXEC_SPI_LOGIC is a driving signal that causes the SPI logic unit 110 to execute, similar to the counter and clock execution signal EXEC_CNT_N_SCLK_EN.

Also, the SPI logic unit 110 transmits transmission data (SPI_WRITE), which is data in bit units corresponding to the input data (DATA_IN), to the SPI core of the slave device, and receives reception data (SPI_READ) in units of bits from the SPI core of the slave device. And obtains the output data (DATA_OUT) corresponding to the received data (SPI_READ) and outputs it to the corresponding device.

The SPI logic unit 110 outputs a unit communication completion signal NEXT_BYTE to notify the corresponding device that the unit communication is completed each time communication of a preset unit (for example, byte) is completed. On the other hand, the SPI logic unit 110 outputs the transmission completion signal CHK_FIN to the corresponding device when the transmission of the number of transmission times (BCNT) is completed.

3, the SPI core 100 of the present invention receives and sets a clock polarity setting signal CPOL and a phase setting signal CPHA from a corresponding device having the SPI core 100 have. Therefore, it is possible to smoothly perform SPI communication with various kinds of slave devices in which the clock polarity setting signal CPOL and the phase setting signal CPHA are set to be different from each other. That is, communication can be performed irrespective of the SPI core setting of the slave device.

FIG. 4 illustrates a method of operating an SPI core according to an embodiment of the present invention, and illustrates an operation method according to a state machine technique.

The SPI core 100 of the present invention can be implemented as a field-programmable gate array (FPGA). The SPI core 100 implemented by the FPGA includes a hardware description language (HDL: Hardware Description Language). Common hardware description languages include VHDL (VHSIC Hardware Description Language) and Verilog. The state according to each operation of the SPI core 100 is set as a state machine technique and the SPI core 100 is implemented in the FPGA by expressing it in a hardware description language. That is, the SPI core operation method of FIG. 4 can be applied to the SPI core design method.

4, when the SPI core 100 is initially powered by applying power to the SPI core 100, the counter 120 counts up the reset count value RST_CNT ) And determines whether or not the predetermined stabilization time has been reached (S11). If the reset count value RST_CNT is smaller than the stabilization time, since the SPI core 100 is in an unstable state, no operation is performed until the reset count value RST_CNT reaches the stabilization time. However, when the reset count value RST_CNT reaches the stabilization time, the control signal CTRL is received from the device having the SPI core 100 to store various settings of the SPI core 100, and the clock polarity setting It is determined whether the signal CPOL is 0 (S12).

If the clock polarity setting signal CPOL is 0, the initial level of the synchronous clock SCLK is set to the low level L (S13). However, if the clock polarity setting signal CPOL is 1, the initial level of the synchronous clock SCLK is set to the high level H (S14). Then, it is kept in the standby state (S15). In the standby state, the SPI core 100 initializes the unit communication completion signal NEXT_BYTE and the transmission completion signal CHK_FIN to 0, and deactivates at least one slave selection signal CS to zero.

Then, the SPI core 100 determines whether communication is activated to perform communication with the slave (S16). Here, the SPI core 100 determines that the at least one selection input signal CE for selecting the slave from the corresponding device is activated to 1, the counter and clock execution signal (EXEC_CNT_N_SCLK_EN) and the logic execution signal (EXEC_SPI_LOGIC) The communication is activated.

If the SPI core 100 is not activated, the standby state is maintained (S15). However, when the communication is activated, the slave selecting signal CS corresponding to the activated selection input signal CE is activated to 0, and the synchronous clock generating unit 130 sets the synchronous clock SCLK to the clock polarity setting signal CPOL Then, the initial value is toggled (S17).

Thereafter, the SPI core 100 determines whether the phase setting signal CPHA is set to 0 (S18). If the phase setting signal CPHA is set to 0 as a result of the determination, the SPI logic unit 110 outputs the slave and transmission data SPI_WRITE and the reception data SPI_READ ) In bit units (S19). However, if the phase setting signal CPHA is set to 1, the count value CNT starts to transmit and receive the slave, the transmission data SPI_WRITE and the reception data SPI_READ bit by bit at step S0001 (S19). Here, the count value CNT means the bit count value BIT_CNT.

Then, it is determined whether the number of data transmitted / received reaches the number of transmission times (BCNT) (S21). The SPI logic unit 110 activates the transmission completion signal CHK_FIN to 1 and outputs the signal to the corresponding device and deactivates the activated slave signal CS to 1 if the number of data transmitted and received is equal to or greater than the transmission number value BCNT (S22). However, if the number of data transmitted / received is less than the number of transmission times (BCNT), the unit communication completion signal NEXT_BYTE is activated to 1 to indicate that the unit communication is completed, and the transmission completion signal CHK_FIN is set to 0 to maintain the deactivation state ).

On the other hand, if the number of transmitted / received data reaches the number of transmission times (BCNT) and the transmission completion signal CHK_FIN is activated to 1, it is determined whether communication of the SPI core 100 is to be deactivated (S24). The SPI core 100 receives at least one selection input signal CE from the corresponding device is deactivated to zero and the counter and clock execution signal EXEC_CNT_N_SCLK_EN and the logic execution signal EXEC_SPI_LOGIC are deactivated to zero and the counter initialization signal EXEC_CNT_CLR) is activated to 1, it is determined that it is inactivated. If the SPI core 100 is inactivated, the SPI core 100 enters a standby state again (S15). However, if the SPI core is not inactivated, the unit communication completion signal NEXT_BYTE is kept active and the transmission completion signal CHK_FIN is held in the inactive state (S23).

Although not shown in FIG. 4, the SPI core 100 determines whether a reset signal RST is received from a corresponding device in any operation state. When the reset signal is received, the SPI core 100 determines various settings including the reset counter RST_CNT Initialize. Then, it is determined whether the initialized reset counter RST_CNT reaches the stabilization time again (S11). That is, operates in the same manner as in the initial driving.

Also, although the activation and deactivation states of the respective signals are described as 0 or 1 in the above description, the activation and deactivation state values may vary depending on the SPI core 100 design.

As described above, if each operation of the SPI core 100 of FIG. 4 is set to a state machine technique, it can be easily expressed in a hardware description language, and as a result, the SPI core 100 can be implemented in an FPGA. The control signal CTRL including the clock polarity setting signal CPOL and the phase setting signal CPHA is received from the apparatus having the SPI core 100 and is varied and set to perform communication regardless of the setting of the slave can do.

The method according to the present invention can be implemented as a computer-readable code on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like, and a carrier wave (for example, transmission via the Internet). The computer-readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art.

Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (7)

A method of operating an SPI core, which is implemented in an FPGA and is embedded in an apparatus that performs SPI communication, and includes an SPI logic unit, a counter, and a synchronous clock generation unit,
The SPI core receiving a control signal including a clock polarity setting signal and a phase setting signal from the apparatus and determining a level of the clock polarity setting signal;
Setting an initial level of a synchronous clock for synchronization between the SPI core and at least one other device communicating with the device according to the level of the clock signal;
A standby state in which the SPI core initializes a setting for performing communication between the apparatus and the at least another apparatus;
Determining whether the SPI core is a signal for activating communication of the SPI core;
In response to a selection input signal applied at the device for selecting the SPI core to communicate with the device and to perform another SPI communication with the SPI core, And toggling the synchronous clock whose initial level is set;
Determining the sampling phase of data to be transmitted by the SPI core to the at least one other device according to the level of the phase setting signal and transmitting and receiving data with the at least one other device in accordance with the determined sampling phase;
Determining whether the number of data transmitted and received by the SPI core reaches a value of the number of transmissions specified by the control signal;
The SPI core activating a transmission completion signal to 1 and outputting the transmission completion signal to the device when the number of transmitted and received data reaches the number of transmission times, and deactivating the activated slave selection signal;
Determining whether the SPI core is to deactivate the SPI communication in response to the control signal; And
Re-entering the idle state if the SPI communication is deactivated; / RTI > of the SPI core. 2. The method of claim 1,
Initializing a unit communication completion signal indicating completion of unit communication every time communication of a predetermined unit is completed with a transmission number value for setting a number of times of performing transmission in a predetermined unit; And
Deactivating at least one slave selection signal for selecting one of the at least one other device to perform SPI communication with the device; The method comprising the steps of: The method of claim 2, wherein the step of determining whether the signal is for activation of the communication
A selection input signal for activating one of the at least one slave selection signal is activated and applied at the device, and a counter for activating the counter and the synchronous clock generator and a logic execution signal for activating the SPI logic unit Wherein the signal is a signal for activating the communication when all the signals are activated. 4. The method of claim 3,
The SPI core activating a unit communication completion signal indicating that the unit communication is completed and keeping the transmission completion signal in an inactive state if the number of the transmitted and received data is less than the number of transmission times; Further comprising the step of: 5. The method of claim 4, wherein determining whether to disable the SPI communication comprises:
The SPI core deactivates the selection input signal, the counter and clock execution signal and the logic execution signal are deactivated to zero, and when the counter initialization signal for initializing the count values stored in the counter is activated to 1, Is deactivated. ≪ Desc / Clms Page number 24 > 6. The method of claim 5,
Maintaining the unit communication completion signal in an active state and keeping the transmission completion signal in an inactive state if the SPI communication is not inactivated; Further comprising the step of: 6. The method of claim 5,
Counting a reset count value among the count values regardless of an operation state of the current SPI core when the SPI core is initially driven or a reset signal is applied from the device to the SPI core to determine whether a preset stabilization time has been reached ; Further comprising the step of:
KR1020130136899A 2013-11-12 2013-11-12 Universal spi core using fpga and operation method thereof KR101447154B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110060856A1 (en) 2009-09-09 2011-03-10 Hon Hai Precision Industry Co., Ltd. Spi control device and method for accessing spi slave devices using the same
CN202870808U (en) 2012-07-04 2013-04-10 四川九洲电器集团有限责任公司 FPGA realization device of SPI serial port module

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110060856A1 (en) 2009-09-09 2011-03-10 Hon Hai Precision Industry Co., Ltd. Spi control device and method for accessing spi slave devices using the same
CN202870808U (en) 2012-07-04 2013-04-10 四川九洲电器集团有限责任公司 FPGA realization device of SPI serial port module

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