KR101506279B1 - Universal spi core using fpga - Google Patents

Abstract

Disclosed is a general-purpose SPI core using FPGA. According to the present invention, an SPI core, embedded in a device performing SPI communications, includes: a sync clock generating part generating a sync clock for synchronization in response to a clock polarity setting signal applied by a device when SPI communications is performed between the device and at least one other device performing the SPI communications; a counter generating count values determining a sampling timing of data and the number of bits of the data transceived through the SPI communications; and a SPI logic part receiving and then storing a control signal, including the clock polarity setting signal and a phase setting signal, from the device, and transceiving the data through the SPI communications between the device and at least one other device according to the stored phase setting signal and the counter values generated in the counter.

Description

A universal SPI core using an FPGA {UNIVERSAL SPI CORE USING FPGA}

The present invention relates to a general-purpose SPI core, and more particularly to a general-purpose SPI core that can be implemented using an FPGA.

The Serial to Peripheral Interface (SPI) is a synchronous serial data connection standard that operates in architecture full duplex communication mode, and is a serial peripheral interface. SPI is one of the serial communication methods used to transfer data at high speed between CPU and multiple CPUs or between CPU and many peripheral devices. In order to use SPI communication, devices operate as one of master and slave with built-in SPI core (SPI Core) to support SPI communication. Master uses SPI communication with several slave devices and individual chip select lines Can be performed. That is, a plurality of slaves can be connected to one master, and the master performs communication in a form of selecting one of a plurality of slaves using a chip select line.

The SPI is a four-wire serial communication interface that communicates over four signal lines and specifies four logic signals corresponding to four signal lines. The four logic signals are SCLK (Serial Clock or CLK), MOSI (Mater Output Slave Input or SDI, DI, DIN, SI), MISO (Maternal Input Slave Output or SDO, DO, DOUT, SO) SS, CSB, CSN, STE).

SCLK is a clock signal for synchronization between the master and the slave, generated by the master and transmitted to the slave. MOSI and MISO are signals for data transmission and reception, and MOSI is a signal output from a master and input to a slave. MISO is a signal that is output from the slave and input to the master as opposed to MOSI. And CS is a slave selection signal as a slave selection signal as described above.

1 is a diagram showing the concept of a clock polarity setting signal and a phase setting signal of SPI communication.

The SPI control register included in the SPI core is configured to set the clock polarity setting signal CPOL and the phase setting signal CPHA. In this case, the clock polarity setting signal CPOL is a value for designating the polarity of the clock, and the phase setting signal CPHA is a value for specifying the clock phase. If CPOL = 1, ), It starts at HIGH. When CPOL = 0, the synchronous clock (SCK) starts at LOW. That is, the bit for selecting the start of the synchronous clock signal SCK is the clock polarity setting signal CPOL.

For example, as shown in FIG. 1, when the phase setting signal CPHA is 1 and the clock polarity is 1, When the set signal CPOL is 1, a data latch occurs at the rising edge. When the phase setting signal CPHA is 1 and the clock polarity setting signal CPOL is 0, data latch occurs at the falling edge, If the signal CPHA is 0 and the clock polarity setting signal CPOL is 1 on the falling edge, if the phase setting signal CPHA is 0 and the clock polarity setting signal CPOL is 0, the data latch occurs at the rising edge.

However, in the conventional SPI core, the value of the clock polarity setting signal (CPOL) and the phase setting signal (CPHA) of the control register are designed in advance as one value. Therefore, since the SPI communication between the devices having different values of the clock polarity setting signal CPOL and the phase setting signal CPHA can not be performed, the values of the clock polarity setting signal CPOL and the phase setting signal CPHA are There is a problem that the same SPI core needs to be redesigned. In other words, it is troublesome to always modify the SPI core to support SPI communication between devices in which the values of the clock polarity setting signal (CPOL) and the phase setting signal (CPHA) do not match.

It is an object of the present invention to provide an SPI core implemented in an FPGA so that a setting value can be changed corresponding to use conditions of various SPI devices.

According to an aspect of the present invention, there is provided a general-purpose SPI core using an FPGA, the SPI core including an SPI core embedded in a device for performing SPI communication, the SPI core including at least one SPI core A synchronous clock generator for generating a synchronous clock for synchronization in the SPI communication in response to a clock polarity setting signal applied from the apparatus; A counter for generating count values for determining the number of bits of data to be transmitted and received in the SPI communication and sampling timing of data; Receiving and storing a control signal including a clock polarity setting signal and a phase setting signal from the apparatus and storing a control signal including a clock polarity setting signal and a phase setting signal between the apparatus and the at least one other apparatus in accordance with the stored phase setting signal and the counter values generated in the counter An SPI logic unit for transmitting and receiving data through SPI communication; .

The clock generating unit determines an initial level of the synchronous clock according to the clock polarity setting signal and toggles the synchronous clock in response to a counter and a clock execution signal applied from the apparatus to output the synchronized clock to the other apparatus .

Wherein the counter counts a reset count value among the count values when the SPI core is initially driven or a reset signal is applied to the SPI core from the device.

Wherein the counter is activated in response to the counter and clock enable signal applied after the reset count value reaches a predetermined settling time and the bit used to determine the data transmission and sampling timing in the SPI logic portion of the count values Counts and outputs a count value, and initializes the count values in response to a counter initialization signal applied from the apparatus.

Wherein the SPI logic unit is activated in response to a logic execution signal applied from the apparatus and includes a phase setting signal for setting a phase of timing for sampling data, a transmission number value for setting a number of times of performing transmission in a predetermined unit, And outputting the data as transmission data to the other device on a bit basis in accordance with the bit count value and outputting the received data transmitted from the other device to the device as output data .

The SPI logic unit outputs a unit communication completion signal indicating completion of the unit communication to the apparatus every time the predetermined unit of communication is completed, and when the data transmission number value is transmitted by the transmission number value, To the apparatus.

Wherein the SPI core activates a slave selection signal corresponding to an activated input selection signal of at least one slave selection signal when one of the at least one selection input signal is activated from the device, And selects another device to perform the SPI communication.

The SPI core is implemented in the FPGA and is embedded in the device.

Accordingly, in the general-purpose SPI core using the FPGA of the present invention, the SPI core receives a control signal designating various settings from a corresponding device having an SPI core, and outputs a clock signal having a clock polarity setting signal CPOL or a phase setting signal CPHA Values, so that the corresponding device can directly specify various settings. Therefore, it is possible to have versatility in comparison with a conventional SPI core that operates only in accordance with a predetermined set value. Also, since it is implemented in FPGA, it can be easily included in various devices and can be easily modified later.

1 is a diagram showing the concept of a clock polarity setting signal and a phase setting signal of SPI communication.
2 shows a structure of an SPI core according to an embodiment of the present invention.
3 is a detailed view showing the operation of each configuration of the SPI core of FIG.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention can be implemented in various different forms, and is not limited to the embodiments described. In order to clearly describe the present invention, parts that are not related to the description are omitted, and the same reference numerals in the drawings denote the same members.

Throughout the specification, when an element is referred to as "including" an element, it does not exclude other elements unless specifically stated to the contrary. The terms "part", "unit", "module", "block", and the like described in the specification mean units for processing at least one function or operation, And a combination of software.

FIG. 2 shows a structure of an SPI core according to an embodiment of the present invention, for example, an SPI core 100 of a master device.

Referring to FIG. 2, the SPI core 100 includes an SPI logic unit 110, a counter 120, and a synchronous clock generation unit 130. The SPI core 100 receives a clock signal CLK, a reset signal RST, a control signal CTRL and data DATA from a corresponding device including the SPI core 100 and performs communication through SPI communication The slave selection signal CS, the synchronous clock SCLK and the transmission data SPI_WRITE to the SPI core 100 of the slave device to be received and receives the reception data signal SPI_READ from the SPI core 100 of the slave device do. Then, it acquires the data (DATA) from the received data (SPI_READ) and transmits it to the corresponding device. The control signal CTRL is not a single signal but a combination of a plurality of signals. Particularly, the control signal CTRL is a signal for designating various settings of the SPI core 100 and includes a clock polarity setting signal CPOL The value of the clock polarity setting signal CPOL or the phase setting signal CPHA of the SPI core 100 including the CPHA value can be directly designated by the corresponding device.

In the SPI core 100, the synchronous clock generator 130 generates a synchronous clock SCLK, which is a clock for providing synchronization between the master device and the SPI core 100 of the slave device. The counter 120 shifts the data DATA stored in the SPI logic unit 110 and generates a count value CNT for designating the sampling timing of the data DATA. The SPI logic unit 110 sets the output according to the control signal CTRL and the counter value CNT of the counter 120.

Accordingly, the SPI core 100 of FIG. 2 receives the control signal CTRL from the corresponding device and outputs various setting values including the values of the clock polarity setting signal CPOL and the phase setting signal CPHA to the corresponding devices It is possible to have versatility in comparison with a conventional SPI core that operates only in accordance with a predetermined set value.

3 is a detailed view showing the operation of each configuration of the SPI core of FIG.

3, the SPI core 100 receives the clock signal CLK and the reset signal RST from the corresponding device having the SPI core 100 . The clock signal CLK is a clock signal used by the SPI core 100 and serves as a reference of the operation timing of the SPI core 100. [ The reset signal RST is a signal for initializing the set value and data of the SPI core 100. While the SPI core 100 receives the selection input signal CE from the corresponding device. The SPI core 100 activates a slave selection signal CS for selecting a slave in response to the selection input signal CE. The SPI core 100 of the master device can perform SPI communication with a plurality of slave devices and the master device needs to select a slave device that desires to perform communication among the plurality of slave devices. The master device transmits the selection input signal CE to the SPI core 100. The SPI core 100 responds to the selection input signal CE to output a plurality of slave selection signal lines As a slave selection signal CS. The SPI core of the slave device connected to the slave selection signal line in which the slave selection signal CS is activated is activated.

Meanwhile, the counter 120 of the SPI core 100 receives the counter and clock execution signal (EXEC_CNT_N_SCLK_EN) and the counter initialization signal (EXEC_CNT_CLR) as the control signal CTRL from the corresponding device. The counter and the clock execution signal (EXEC_CNT_N_SCLK_EN) are drive signals for causing the counter 120 to execute. When the counter execution signal (EXEC_CNT_N_SCLK_EN) is applied, the counter 120 is driven to start counting and output a counter value (CNT). The counter initializing signal EXEC_CNT_CLR is a signal for initializing a value stored in a register provided in the counter 120, that is, a count value CNT. 3, the counter 120 includes a bit counter 121 and a reset counter 122. Each of the bit counter 121 and the reset counter 122 includes a register to store a count value . The count value CNT output from the counter 120 is a bit count value BIT_CNT and a reset counter value RST_CNT output from the bit counter 121 and the reset counter 122, Is a value stored in each of the registers of the counter 122.

Here, the bit count value BIT_CNT is a count value used for determining the data shift and the sampling timing in the SPI logic unit 110, and the count value is incremented every rising edge of the clock CLK. The reset count value RST_CNT is a count value for counting the stabilization period until the SPI core 100 is initially driven or reset when the SPI core 100 is reset.

The synchronous clock generating unit 130 receives the counter and clock execution signal EXEC_CNT_N_SCLK_EN and the clock polarity setting signal CPOL from the corresponding device and outputs the synchronous clock signal SCLK to the SPI core of the slave device. The counter and clock execution signal (EXEC_CNT_N_SCLK_EN) is a driving signal for causing the counter 120 to execute and a driving signal for causing the synchronous clock generating section 130 to execute simultaneously. That is, the counter and clock execution signal (EXEC_CNT_N_SCLK_EN) simultaneously drives the counter 120 and the synchronous clock generator 130. The clock polarity setting signal CPOL is a signal for controlling the polarity of the synchronous clock signal SCLK as described above. The synchronous clock generating unit 130 generates a synchronous clock signal SCCLK, which is output in response to the clock polarity setting signal CPOL, Determines whether the clock signal SCLK starts at the high level or the low level and outputs the clock signal SCLK to the slave device.

The SPI logic unit 110 receives the phase setting signal CPHA, the transmission count value BCNT, the logic execution signal EXEC_SPI_LOGIC and the input data DATA_IN from the corresponding device and outputs the output data DATA_OUT to the corresponding device . The phase setting signal CPHA is a signal for adjusting the data synchronization timing, and is a signal for setting the phase of the timing for sampling data. The transmission number value BCNT is a signal for setting the number of times of performing transmission in a predetermined unit (for example, byte). The logic execution signal EXEC_SPI_LOGIC is a driving signal that causes the SPI logic unit 110 to execute, similar to the counter and clock execution signal EXEC_CNT_N_SCLK_EN.

Also, the SPI logic unit 110 transmits transmission data (SPI_WRITE), which is data in bit units corresponding to the input data (DATA_IN), to the SPI core of the slave device, and receives reception data (SPI_READ) in units of bits from the SPI core of the slave device. And obtains the output data (DATA_OUT) corresponding to the received data (SPI_READ) and outputs it to the corresponding device.

The SPI logic unit 110 outputs a unit communication completion signal NEXT_BYTE to notify the corresponding device that the unit communication is completed each time communication of a preset unit (for example, byte) is completed. On the other hand, the SPI logic unit 110 outputs the transmission completion signal CHK_FIN to the corresponding device when the transmission of the number of transmission times (BCNT) is completed.

3, the SPI core 100 of the present invention receives and sets a clock polarity setting signal CPOL and a phase setting signal CPHA from a corresponding device having the SPI core 100 have. Therefore, it is possible to smoothly perform SPI communication with various kinds of slave devices in which the clock polarity setting signal CPOL and the phase setting signal CPHA are set to be different from each other. That is, communication can be performed irrespective of the SPI core setting of the slave device.

The method according to the present invention can be implemented as a computer-readable code on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like, and a carrier wave (for example, transmission via the Internet). The computer-readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art.

Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (8)

In an SPI core embedded in a device to perform SPI communication,
A synchronous clock generator for generating a synchronous clock for synchronization in the SPI communication between the apparatus and at least one other apparatus performing SPI communication in response to a clock polarity setting signal applied from the apparatus;
A counter for generating count values for determining the number of bits of data to be transmitted and received in the SPI communication and sampling timing of data; And
Receiving and storing a control signal including a clock polarity setting signal and a phase setting signal from the apparatus and storing a control signal including a clock polarity setting signal and a phase setting signal between the apparatus and the at least one other apparatus in accordance with the stored phase setting signal and the counter values generated in the counter An SPI logic unit for transmitting and receiving data through SPI communication; The SPI core. The apparatus of claim 1, wherein the clock generator
Determines an initial level of the synchronous clock according to the clock polarity setting signal, and toggles the synchronous clock in response to a counter and a clock execution signal applied from the apparatus, and outputs the toggled synchronous clock to the other apparatus. 3. The apparatus of claim 2, wherein the counter
Wherein the SPI core counts a reset count value among the count values when the SPI core is initially driven or a reset signal is applied from the device to the SPI core. 4. The apparatus of claim 3, wherein the counter
A bit count value that is activated in response to the counter and clock execution signal applied after the reset count value reaches a predetermined stabilization time and used to determine data transmission and sampling timing in the SPI logic unit of the count values And initializes the count values in response to a counter initialization signal applied from the apparatus. 5. The apparatus of claim 4, wherein the SPI logic portion
A phase setting signal for activating in response to a logic execution signal applied from the apparatus and setting a phase of a timing for sampling data, a transmission number value for setting a number of times of performing transmission in a predetermined unit, And outputs the data as transmission data to the other apparatus in units of bits in accordance with the bit count value and outputs the reception data transmitted from the other apparatus to the apparatus as output data. core. 6. The apparatus of claim 5, wherein the SPI logic portion
A unit communication completion signal indicating that the unit communication is completed is output to the apparatus every time the communication of the predetermined unit is completed, and when the data transmission number value is transmitted by the transmission number value, And outputs the SPI core. The method of claim 1, wherein the SPI core
Activating a slave selection signal corresponding to an activated input selection signal of at least one slave selection signal when one of the at least one selection input signal from the device is activated to perform SPI communication with the device of the at least one other device Gt; SPI < / RTI > core. The method of claim 1, wherein the SPI core
Wherein the SPI core is implemented in an FPGA and embedded in the device.

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