CN115632903A - Virtual peripheral communication bus control method and device and computer equipment - Google Patents
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Abstract
The invention provides a method, a device and computer equipment for controlling a virtual peripheral communication bus, wherein the method comprises the steps of obtaining a channel mapping relation between an input/output pin and a communication interface, wherein the number of channels corresponding to the communication interface is more than one; and when the first channel meets the setting condition, the first channel carries out data transmission through a public interface processing engine, and the first channel is any channel corresponding to the communication interface. The method provided by the invention can enable a user to automatically expand the number of the communication interfaces according to the application requirement, automatically define the positions of the communication pins, increase the communication interfaces on the premise of reducing the number of IP cores and the area of a chip, improve the communication performance of the microcontroller and reduce the communication cost.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for controlling a virtual peripheral communication bus, and a computer device.
Background
In order to implement communication with an external device, the microcontroller needs a multi-channel Asynchronous Serial Interface or a synchronous Serial Interface, and commonly used interfaces include a Universal Asynchronous Receiver/Transmitter (UART) Interface, a Serial Peripheral Interface (SPI) Interface, and an I2C (Inter-Integrated Circuit) Interface. In order to process data transmitted by an interface, an Intellectual Property (IP) core is usually designed for each communication interface, so as to process input and output data of multiple communication interfaces simultaneously.
If the user requires a greater number of communication interfaces than the microcontroller contains, software or timers are typically used to capture the input pin levels and control the output pin levels to simulate the communication interfaces. Such methods are not only inconvenient to use, but also waste the processing power of the processor and the timer resources. If the method of adding the multiple communication IP cores is adopted, the chip area is increased, and the cost is increased.
Disclosure of Invention
In order to solve the problem that the existing microcontroller is inconvenient to use when an interface is expanded, and the cost is high, the application provides a virtual peripheral communication bus control method, a virtual peripheral communication bus control device and computer equipment, so that the communication performance of the microcontroller can be improved on the premise of not increasing the chip area.
In one aspect, a virtual peripheral communication bus control method is provided, the method including:
acquiring a channel mapping relation between an input pin and an output pin and a communication interface, wherein the number of channels corresponding to the communication interface is more than one;
and when the first channel meets the setting condition, the first channel carries out data transmission through an interface processing engine, and the first channel is any channel corresponding to the communication interface.
In another aspect, there is provided a virtual peripheral communication bus control apparatus, the apparatus comprising:
the mapping relation acquisition module is used for acquiring the channel mapping relation between the input/output pins and the communication interface, wherein the number of channels corresponding to the communication interface is more than one;
and the data transmission module is used for transmitting data through the interface processing engine by the first channel when the first channel meets the setting condition, wherein the first channel is any channel corresponding to the communication interface.
In another aspect, a computer device is provided, where the computer device includes a processor and a memory, where the memory stores at least one instruction, at least one program, a code set, or an instruction set, and the processor can load and execute the at least one instruction, the at least one program, the code set, or the instruction set to implement the virtual peripheral communication bus control method provided in the above-mentioned application embodiments.
In another aspect, a microcontroller is provided comprising a computer device as described above.
In another aspect, a computer-readable storage medium is provided, where at least one instruction, at least one program, a code set, or a set of instructions is stored in the computer-readable storage medium, and the processor may load and execute the at least one instruction, the at least one program, the code set, or the set of instructions to implement the virtual peripheral communication bus control method provided in the embodiments of the present application.
In another aspect, a computer program product or computer program is provided, the computer program title or computer program comprising computer program instructions stored in a computer readable storage medium. The processor reads the computer instructions from the computer readable storage medium and executes the computer instructions, so that the computer device executes the virtual peripheral communication bus control method described in any of the above embodiments.
The beneficial effect that technical scheme that this application provided brought includes at least: the embodiment of the invention provides a method, a device and computer equipment for controlling a virtual peripheral communication bus, wherein the method comprises the steps of obtaining a channel mapping relation between an input pin and an output pin and a communication interface, and the number of channels corresponding to the communication interface is more than one; and when the first channel meets the setting condition, the first channel carries out data transmission through an interface processing engine, and the first channel is any channel corresponding to the communication interface. The method provided by the embodiment of the invention can enable a user to automatically expand the number of the communication interfaces according to the application requirement, automatically define the positions of the communication pins, increase the communication interfaces on the premise of reducing the number of IP cores and the area of a chip, improve the communication performance of the microcontroller and reduce the communication cost.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart illustrating a method for controlling a virtual peripheral communication bus according to an exemplary embodiment of the present application;
fig. 2 is a schematic diagram of a communication interface controller corresponding to a virtual peripheral communication bus control method according to an exemplary embodiment of the present application;
FIG. 3 is a flowchart illustrating yet another method for controlling a virtual peripheral communication bus according to an exemplary embodiment of the present application;
FIG. 4 illustrates another flow chart of a virtual peripheral communication bus control method provided by an exemplary embodiment of the present application;
FIG. 5 is a flowchart illustrating a further method for controlling a virtual peripheral communication bus according to an exemplary embodiment of the present application;
FIG. 6 is a block diagram illustrating a virtual peripheral communication bus control apparatus according to an exemplary embodiment of the present application;
fig. 7 is a schematic structural diagram of a computer device corresponding to a virtual peripheral communication bus control method according to an exemplary embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The virtual peripheral communication bus control method can enable a user to automatically expand the number of communication interfaces according to application requirements, automatically define the positions of communication pins, increase the communication interfaces on the premise of reducing the number of IP cores and the area of a chip, improve the communication performance of a microcontroller and reduce the communication cost.
The first embodiment,
Fig. 1 shows a schematic implementation flow diagram of a virtual peripheral communication bus control method according to an embodiment of the present invention.
Referring to fig. 1, a method for controlling a virtual peripheral communication bus according to an embodiment of the present invention may include steps 101 and 102.
Step 101: and acquiring a channel mapping relation between the input/output pins and the communication interface, wherein the number of channels corresponding to the communication interface is more than one.
According to the virtual peripheral communication bus control method provided by the embodiment of the invention, the pins of the external communication channel can be mapped to any universal input/output pins through the pin mapping matrix, so that a user can conveniently define the corresponding relation according to the requirement, and the flexibility of pin configuration is increased.
In some embodiments, there is a separate clock divider for each communication interface channel, i.e., the sampling/output frequency for each channel is independently configurable and can be changed by the user.
In some embodiments, each of the lanes corresponds to a separate Output First-in-First-out (FIFO) queue and a separate Input FIFO queue. The output first-in first-out queue is used for caching at least one of output data, a command sequence and a configuration sequence; the input first-in first-out queue is used for buffering at least one of input data or state sequence.
The virtual peripheral communication bus control method provided by the embodiment of the invention connects each channel with an independent output buffer FIFO and an input buffer FIFO, and respectively stores the required data sequences.
Step 102: and when the first channel meets the setting condition, the first channel carries out data transmission through an interface processing engine, and the first channel is any channel corresponding to the communication interface.
In some embodiments, the set condition comprises an input set condition comprising the number of input samples of the channel reaching a preset threshold;
when the first channel meets the setting condition, the first channel performs data transmission, and the method comprises the following steps:
and when the input sampling number of the first channel reaches the preset threshold value, the input task position of the first channel is set, and the first channel carries out data input.
In some embodiments, the set condition comprises an output set condition comprising an internal bus outputting data to the channel;
when the first channel meets the setting condition, the first channel performs data transmission, and the method comprises the following steps:
when the internal bus outputs data to the first channel, the output task position of the first channel is set, and the first channel outputs data.
In some embodiments, the internal bus may include at least one of an AHB, APB, AXI bus.
In some embodiments, the first channel performs data transfer operations, including:
and controlling all the first channels meeting the setting conditions to transmit data according to a preset sequence based on the interface processing engine.
In the method for controlling a virtual peripheral communication bus provided in the embodiments of the present invention, a high-speed interface data engine processes input/output data of all channels of task position bits according to a user-defined priority order or a first-in first-out order.
In some embodiments, the first channel performs data transfer operations, including:
an interface processing engine acquires a sampling level in an input buffer first-in first-out queue of the first channel, converts the sampling level into input data, and stores the input data into a Static Random Access Memory (SRAM);
and/or the interface processing engine acquires the state sequence in the input buffer first-in first-out queue of the first channel, converts the state sequence into the state bit of the first channel, and stores the state bit data into the static random access memory.
The virtual peripheral communication bus control method provided by the embodiment of the invention centralizes the configuration and state data of each virtual communication IP in the SRAM, and when one virtual channel is switched, the configuration and state data are correspondingly switched at the same time so as to realize the correct operation of the virtual channel.
Specifically, for output, the interface processing engine sets the output task bit to notify the channel to output data, and the output task bit is cleared after the channel processing is completed. For input, the channel sets the input task bit to inform the interface processing engine to process the input data, and after the engine finishes processing, the input task bit is cleared.
Alternatively, the input/output task bit may be replaced by a status bit of the input/output FIFO.
Specifically, the high-speed interface processing engine converts the output data into the output level sequence and places the output level sequence in the output buffer FIFO of the corresponding channel, and for a more complex communication interface, such as an I2C interface, the output data can be converted into the command sequence according to an I2C protocol and placed in the output buffer FIFO of the corresponding channel.
In some embodiments, the high speed interface processing engine fetches the sample level from the input/output buffer FIFO of the corresponding lane and converts it into input data to be placed in the data SRAM, and the interface processing engine may also fetch the status sequence from the input buffer FIFO of the corresponding lane and convert it into status bits for the corresponding lane to be placed in the status SRAM.
In some embodiments, the peripheral bus controller communicates with a processor or a Direct Memory Access (DMA) engine of the microcontroller to transfer input and output data.
The virtual peripheral communication bus control method provided by the embodiment of the invention can realize virtual multi-path communication, can expand multi-path communication IP on one communication IP core, and each communication IP is independent from the use angle of a user, thereby simultaneously processing the transceiving data of respective input/output pins. The method can realize the sharing of the interface processing engine, switch the engine in a time-sharing way, and process the input and output data of each channel by switching the multi-channel.
Example II,
Fig. 2 is a schematic diagram of a communication interface controller corresponding to a virtual peripheral communication bus control method according to an exemplary embodiment of the present application.
Referring to fig. 2, in one specific example, the virtual multi-lane peripheral communication interface controller is divided into three parts, an interface clock domain, a data processing clock domain and a bus clock domain. The interface clock domain comprises a pin mapping function, a channel selection function and a pin level input and output function; the data processing clock domain comprises a high-speed interface processing engine processing and SRAM configuration function; the bus clock domain includes internal bus control processing functions.
The virtual peripheral communication bus control method provided by the embodiment of the invention divides the clock domain into the communication interface clock domain, the high-speed data processing clock domain and the bus control clock domain, and can realize the input and output data transmission across 3 clock domains.
In some embodiments, the communication interface clock domain, the high-speed data processing clock domain, and the bus control clock domain may be regarded as three asynchronous clock domains, or the high-speed data processing and the bus control may be combined into one clock domain, and the combined clock is also a clock source of each channel of the communication interface.
In some embodiments, multiple sets of general purpose input output pins are connected to a certain set of channels of the communication interface by a pin mapping matrix.
In some embodiments, the configuration, status and data registers of all virtual devices may be implemented as configuration SRAM and data/status SRAM, as well as register files.
Specifically, multiple groups of general input/output pins are connected with a certain group of channels of the communication interface through the pin mapping matrix, and the channels may include a plurality of sampling/IO buffer channels. And connecting the selected channel with a high-speed interface processing engine, selecting a configuration SRAM or a state/data SRAM, and finally connecting an internal bus control engine to realize a data transmission function.
Fig. 3 is a flowchart illustrating a virtual peripheral communication bus control method according to an exemplary embodiment of the present application.
Before the configuration of the input/output channels, a plurality of groups of general input/output pins are connected with a certain group of channels of the communication interface through a pin mapping matrix.
Referring to fig. 3, the workflow of the input/output channel in the present application specifically includes the following steps.
Step one, configuring parameters such as a clock source, a frequency division coefficient and the like.
Specifically, the clock source and the clock division value of each extension channel are set by a configuration sequence in the output buffer FIFO.
And step two, controlling the signal level of the bus according to the output buffered data or command sequence.
Specifically, when the output task bit of the corresponding channel is set, the corresponding channel takes out the output data or the command sequence in the buffer FIFO, controls the level of the signal pin of the communication bus according to the clock frequency set by the user, and resets the output task bit of the channel after completion.
And step three, according to the level of the clock sampling input pin, putting the level into an input buffer.
Specifically, the input pin is correspondingly sampled according to the clock frequency set by the user, and the sampling level value is placed in the input sampling buffer FIFO.
And step four, setting the task bit corresponding to the channel state when the input buffer reaches a fixed threshold value.
Specifically, when the number of level values in the input sampling buffer FIFO reaches a threshold value, the input task bit corresponding to the channel state is set, so that the high-speed interface data engine starts to process the input data.
And circularly executing the second step to the fourth step to realize the control of the input and output channel.
FIG. 4 is a flowchart illustrating another method for controlling a virtual peripheral communication bus according to an exemplary embodiment of the present application.
Referring to fig. 4, the workflow of the high speed interface processing engine in the present application specifically includes the following steps
The output data is converted into a level sequence or a command sequence and is placed in an output buffer FIFO.
Specifically, the high-speed interface processing engine converts the output data into an output level and puts the output level in an output buffer FIFO of the corresponding channel, and for a more complex communication interface, the output data can be converted into a command sequence of a bus state machine according to a bus protocol and put in the output buffer FIFO of the corresponding channel, and an output task bit of the corresponding channel is positioned.
Specifically, if the input task bit of all channel states has a set, the high-speed interface processing engine starts processing the communication interface input data.
And if the task position input by any channel is set, selecting a set channel according to the priority order or the first-in first-out order.
Specifically, the high-speed interface processing engine selects one channel from all channels with the input task position set according to a priority order or a first-in first-out order defined by a user.
The input level is taken out from the input buffer FIFO and converted into input data, and the input data is placed in the data SRAM.
The state sequence is fetched from the input buffer FIFO and placed in the state SRAM.
Specifically, the high-speed interface processing engine takes out the sampling level from the input buffer FIFO of the corresponding channel, converts the sampling level into input data and places the input data in the data SRAM. The interface processing engine can also fetch the state sequence from the input buffer FIFO of the corresponding channel, and the state bit converted into the corresponding channel is placed in the state SRAM.
Eventually notifying the internal bus control engine to receive the input data and resetting the channel input task bit.
Specifically, the high-speed interface processing engine notifies the internal bus control engine to receive the input data and resets the input task bit corresponding to the channel state.
And circularly executing the steps, and continuously processing the next channel after the current channel is finished.
Fig. 5 is a flowchart illustrating a virtual peripheral communication bus control method according to yet another exemplary embodiment of the present application.
Referring to fig. 5, the work flow of the internal bus control engine in the present application is as follows.
The method comprises the following steps: and receiving a read-write request for the specified channel specified configuration register.
Specifically, the internal bus control engine receives a read/write request of the microcontroller processor to a specific configuration register of a specific channel.
Step two: the corresponding registers are read from and written to by the configuration, data, and state SRAMs and the results returned.
Specifically, the internal bus control engine reads and writes corresponding registers from the configuration SRAM and the status/data SRAM, and transfers the results to the microcontroller processor, where the configuration SRAM and the status/data SRAM are both dual-ported SRAMs.
Step three: the received output data is placed in a data SRAM and informs an interface processing engine to process the output data.
Specifically, after receiving the output data sent from the processor or the DMA, the high-speed interface processing engine is caused to start processing the output data.
Step four: input data is received from the interface processing engine and transferred to the DMA engine.
Specifically, after receiving the input data sent from the high-speed interface processing engine, the input data is sent to the DMA.
And circularly executing the step two to the step four to realize the process of the internal bus control engine.
In summary, the virtual peripheral communication bus control method provided in the embodiments of the present invention enables a user to automatically expand the number of communication interfaces according to application requirements, and to automatically define the positions of communication pins, so as to increase the number of communication interfaces on the premise of reducing the number of IP cores and chip area, improve the communication performance of the microcontroller, and reduce the communication cost.
Example III,
Fig. 6 is a schematic structural diagram illustrating a virtual peripheral communication bus control apparatus according to an embodiment of the present invention.
Referring to fig. 6, the virtual peripheral communication bus control apparatus provided in the embodiment of the present invention may include:
a mapping relation obtaining module 201, configured to obtain a channel mapping relation between an input/output pin and a communication interface, where the number of channels corresponding to the communication interface is greater than one;
a data transmission module 202, configured to, when a first channel meets a set condition, perform data transmission on the first channel through an interface processing engine, where the first channel is any channel corresponding to the communication interface.
In some embodiments, each of the channels corresponds to an independent output fifo queue and an independent input fifo queue;
the output first-in first-out queue is used for caching at least one of output data, a command sequence and a configuration sequence;
the input FIFO queue is used for buffering at least one of input data or state sequence.
The setting condition comprises an input setting condition, and the input setting condition comprises that the input sampling number of the channel reaches a preset threshold value; in some embodiments, the data transmission module 202 is specifically configured to:
and when the input sampling number of the first channel reaches the preset threshold value, the input task position of the first channel is set, and the first channel carries out data input.
The setting condition comprises an output setting condition, and the output setting condition comprises that an internal bus outputs data to the channel; in some embodiments, the data transmission module 202 is specifically configured to:
when the internal bus outputs data to the first channel, the output task position of the first channel is set, and the first channel outputs data.
In some embodiments, the data transmission module 202 is specifically configured to:
and the interface processing engine controls all the first channels meeting the setting condition to transmit data according to a preset sequence.
In some embodiments, the data transmission module 202 is specifically configured to:
the interface processing engine acquires a sampling level from an input buffer first-in first-out queue of the first channel, converts the sampling level into input data and stores the input data into a static random access memory;
and/or the interface processing engine acquires a state sequence from the input buffer first-in first-out queue of the first channel, converts the state sequence into a state bit of the first channel, and stores the state bit data into a static random access memory.
In summary, the virtual peripheral communication bus control apparatus provided in the embodiments of the present invention enables a user to automatically extend the number of communication interfaces according to application requirements, and to automatically define the positions of communication pins, so as to increase the number of communication interfaces on the premise of reducing the number of IP cores and chip area, improve the communication performance of the microcontroller, and reduce the communication cost.
Example four,
Fig. 7 shows a schematic structural diagram of a computer device provided in an exemplary embodiment of the present application, where the computer device includes:
the processor 301 includes one or more processing cores, and the processor 301 executes various functional applications and data processing by executing software programs and modules.
The receiver 302 and the transmitter 303 may be implemented as one communication component, which may be a communication chip. Optionally, the communication component may be implemented to include signal transmission functionality. That is, the transmitter 303 may be configured to transmit a control signal to the image capturing device and the scanning device, and the receiver 302 may be configured to receive a corresponding feedback instruction.
The memory 304 is connected to the processor 301 through a bus 305.
The memory 304 may be configured to store at least one instruction, and the processor 301 is configured to execute the at least one instruction to implement steps 101 to 102 in the above-described embodiment of the virtual peripheral communication bus control method.
Examples V,
An embodiment of the present application further provides a microcontroller including the computer device as described above.
Example six,
Embodiments of the present application further provide a computer-readable storage medium, where at least one instruction, at least one program, a code set, or an instruction set is stored in the computer-readable storage medium, and the computer-readable storage medium is loaded and executed by a processor to implement the above virtual peripheral communication bus control method.
Example seven,
The present application also provides a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computer device to execute the virtual peripheral communication bus control method described in any of the above embodiments.
Optionally, the computer-readable storage medium may include: read Only Memory (ROM), random Access Memory (RAM), solid State Drive (SSD), or optical disc. The Random Access Memory may include a resistive Random Access Memory (ReRAM) and a Dynamic Random Access Memory (DRAM). The above-mentioned serial numbers of the embodiments of the present application are merely for description, and do not represent the advantages and disadvantages of the implementation.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, where the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk.
The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A virtual peripheral communication bus control method, the method comprising:
acquiring a channel mapping relation between an input pin and an output pin and a communication interface, wherein the number of channels corresponding to the communication interface is more than one;
and when the first channel meets the setting condition, the first channel performs data transmission corresponding to the input and output pins based on an interface processing engine, wherein the first channel is any channel of the communication interface.
2. The method of claim 1, wherein each of said channels corresponds to a separate output fifo queue and a separate input fifo queue;
the output first-in first-out queue is used for caching at least one of output data, a command sequence and a configuration sequence;
the input first-in first-out queue is used for buffering at least one of input data or state sequence.
3. The method according to claim 1, wherein the setting condition comprises an input setting condition, and the input setting condition comprises that the number of input samples of the channel reaches a preset threshold value;
when the first channel meets the setting condition, the first channel performs data transmission corresponding to the input/output pin based on an interface processing engine, and the data transmission comprises the following steps:
and when the input sampling number of the first channel reaches the preset threshold value, the input task position of the first channel is set, and the first channel carries out data input.
4. The method of claim 1, wherein the set condition comprises an output set condition, the output set condition comprising an internal bus outputting data to the channel;
when the first channel meets the setting condition, the first channel performs data transmission corresponding to the input and output pin based on an interface processing engine, and the data transmission method comprises the following steps:
when the internal bus outputs data to the first channel, the output task position of the first channel is set, and the first channel outputs data.
5. The method of any one of claims 1 to 4, wherein the first channel performs data transmission corresponding to the input and output pins based on an interface processing engine, and comprises:
and controlling all the first channels meeting the setting conditions to transmit data according to a preset sequence based on the interface processing engine.
6. The method of any one of claims 1 to 4, wherein the first channel performs a data transfer operation corresponding to the input/output pin based on an interface processing engine, and the method comprises:
the interface processing engine acquires a sampling level from an input buffer first-in first-out queue of the first channel, converts the sampling level into input data and stores the input data into a static random access memory;
and/or the interface processing engine acquires a state sequence from the input buffer first-in first-out queue of the first channel, converts the state sequence into a state bit of the first channel, and stores the state bit data into a static random access memory.
7. A virtual peripheral communication bus control apparatus, the apparatus comprising:
the mapping relation acquisition module is used for acquiring the channel mapping relation between the input/output pins and the communication interface, wherein the number of channels corresponding to the communication interface is more than one;
and the data transmission module is used for performing data transmission corresponding to the input and output pins on the first channel based on an interface processing engine when the first channel meets a setting condition, wherein the first channel is any one channel of the communication interface.
8. A computer device comprising a processor and a memory having stored therein at least one instruction, at least one program, set of codes, or set of instructions, which is loaded and executed by the processor to implement the virtual peripheral communication bus control method of any one of claims 1 to 6.
9. A microcontroller characterized by comprising a computer device according to claim 8.
10. A computer readable storage medium having stored therein at least one instruction, at least one program, set of codes, or set of instructions, which is loaded and executed by a processor to implement the virtual peripheral communication bus control method as claimed in claims 1 to 6.
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| CN116795755A (en) * | 2023-08-28 | 2023-09-22 | 上海移芯通信科技股份有限公司 | Equipment management method and device based on Internet of things chip |
| CN116795755B (en) * | 2023-08-28 | 2023-12-08 | 上海移芯通信科技股份有限公司 | Equipment management method and device based on Internet of things chip |
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| CN115632903B (en) | 2024-05-31 |
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