JP3260515B2 - Interface circuit for multiple port storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit used for a storage device shared by a plurality of ports, and more particularly to an interface circuit for a multi-port storage device which performs high-speed data transfer by performing priority processing of instructions. About.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of an interface circuit of a conventional multi-port storage device, and FIG. 4 is a timing chart showing the operation of the example of FIG.

A conventional interface circuit used for a storage device shared by a plurality of ports (requesters) is as follows.
As shown in FIG. 3, the instruction signals 101 to 104 output by the ports (requesters) 1 to 4 and the reset signal group 112 output by the instruction selection circuit 12 corresponding to each of the requesters 1 to 4 respectively. Wait command control circuits 5 to input and output a wait command signal group 105 from each of them.
8 and a waiting instruction signal group 105, and a busy signal 107 from the instruction processing circuit 13 to output a command execution signal 106 and a port number signal 108 to instruct the execution of the command. 12 and an instruction execution signal 106 and a port number signal 108 to execute an instruction, perform busy management and reply management, output a busy signal 107 to the instruction selection circuit 12, and send a reply go signal 109 and the current execution port. The number signal 114 is output to the reply control circuit 11,
In addition, an instruction processing circuit 13 for outputting a memory access control signal 110 and a requestor 1 through input of a reply go signal 109 and a current execution port number signal 114
4 is provided with a reply control circuit 11 for outputting a reply signal group 111 to the group No. 4.

The operation of the interface circuit of the conventional multi-port storage device configured as described above will be described with reference to FIG.

Here, for the sake of simplicity, only the requesters 1 and 2 are used, and each requester and the present storage device operate with the same clock.
Further, it is assumed that the cycle period between instructions and between requesters and the reply timing of instructions are as shown in Tables 1 and 2, respectively. One clock cycle is described as 1T.

[0006]

[Table 1]

[0007]

[Table 2]

The requester 1 issues a normal write instruction (NW) at 5T and 7T because the maximum number of instructions that can be held by the wait instruction control circuit 5 is two, and the requester 2
It is assumed that a normal read instruction (NR) is issued at 6T.

The waiting instruction control circuit 5 changes the NW from the requester 1 at 5T to the buffer 1 in its own circuit at 6T.
And outputs an instruction execution request to the instruction selection circuit 12. The instruction selecting circuit 12 recognizes that only the requester 1 has a waiting instruction, and at 6T, the NW of the requester 1
Is output to the instruction processing circuit 13. The instruction processing circuit 13 which has received this instruction is currently empty, and starts executing at 7T, and sets the busy signal 107 to "1". At 21T, in order to output a reply signal to the requester 1, a reply go signal 109 and a currently executed port number signal 114 are output.

Since the busy signal 107 is "0" (empty state) at 6T, the instruction selecting circuit 12 determines that the instruction which has output the execution instruction at 6T is executed at 7T, and wait instruction control at 6T. The reset signal is output to the corresponding line of the reset signal group 112 to the circuit 5.

Wait command control circuit 5 receiving a reset signal
Resets the buffer 1 to an empty state at 7T, but since the requester 1 has also issued an NW at 7T, the buffer 1 holds the NW at 8T.

On the other hand, the NR issued by the requester 2 in 6T
Is in the waiting state in the buffer 1 of the waiting instruction control circuit 6 from 7T.

The instruction from which the instruction selection circuit 12 outputs the next execution instruction is the NR from the requester 2 by the operation of this circuit to equalize the number of instructions processed from each requester.
However, since the currently executed port number signal 114 and the port number signal 108 do not match, the cycle period between requesters (busy period between requesters) = 15T
Is executed at 22T after elapse, and at 36T, a reply signal returns to the requester 2 to complete the processing.

The instruction to be executed for the third time is the NW of the requester 1 which has been in the waiting state from 8T in the waiting instruction control circuit 5, and also here does not match the port number being executed for the second time. Busy period between = 1
Execution starts at 37T after 5T has elapsed.

The third NW issued by the requester 1
Since the wait instruction control circuit 5 cannot respond until the reply is returned to the requester 1 at 21T, it is issued at 23T because the wait instruction control circuit 5 cannot respond unless it is issued after the processing of the first NW is completed. It will be. At this time, the buffer 1 of the waiting instruction control circuit 5 stores the second N
W, the third N in the buffer 2
W is to be held.

[0016]

The above-mentioned interface circuit of the conventional multi-port storage device, when an instruction is frequently issued from two or more requesters, causes a normal write (read) to a normal write (read). Since the cycle period 5T of (read) becomes unavailable and the cycle period 15T between requesters becomes a busy period of one instruction, there is a disadvantage that data transmission efficiency is poor. Also, when an instruction is frequently issued from only one requester, the instruction is executed during the busy period of 5T between the first instruction and the second instruction, but the issue time of the third instruction is Because of the delay, the interval between the second instruction and the third instruction is longer than the cycle period between the instructions, and the data transmission efficiency is also deteriorated.

[0017]

According to the present invention, there is provided an interface circuit for a multi-port storage device, which is connected to each of a plurality of ports and can wait for execution of up to two instructions from the corresponding port. A plurality of waiting command control circuits for outputting a waiting command signal, and resetting a waiting command that has entered execution by inputting a corresponding reset signal for each port; and a waiting command signal from the plurality of waiting command control circuits. Priority processing is performed by inputting a busy signal and an executing instruction information signal from the instruction processing circuit, and a request for an instruction to be executed next is made to the instruction processing circuit by an instruction execution signal and a port number signal. A priority processing circuit for outputting a reset signal for resetting the entered instruction to the plurality of waiting instruction control circuits; A number signal is input to execute an instruction, perform busy management and reply management, output the busy signal and the execution instruction information signal to the priority processing circuit, and control a reply go signal and a currently executed port number signal by a reply control. An instruction processing circuit for outputting a control signal for memory access to the circuit, and receiving a reply signal for each of the plurality of ports by inputting the reply go signal and the currently executed port number signal; The reply control circuit for outputting the priority command when the instruction processing circuit is executing a continuous write instruction or a continuous read instruction and the standby instruction control circuit for the same port includes an instruction to be continued. This includes receiving the waiting instruction preferentially in the processing circuit. When the circuit has started the execution of the continued write command or continuous read command, in which comprises outputting the reply signal to the immediately corresponding port in the reply control circuit.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment of FIG.

In FIG. 1, ports (requesters) 1 to
Reference numeral 4 denotes a source of an instruction to the storage device. The instruction types include a normal read instruction (normal read instruction) and a normal write instruction (normal write instruction), and a continuous read instruction and a continuous write instruction. There are four types. If you want to transfer several kilobytes of data at high speed,
Use a continuous read instruction or a continuous write instruction. The number of instructions that can be issued continuously by one requester is up to two. From the third instruction, every time it is confirmed that the reply signal is returned by the reply signal group 111 from the reply control circuit 11 , One by one.

The waiting command control circuits 5 to 8 are provided with command signals 101 output by the requesters 1 to 4 respectively connected thereto.
１０４104 are input, and two instructions issued by the corresponding requesters are held using two buffers (buffer 1 and buffer 2) provided in each circuit.
Each of the wait instruction control circuits 5 to 8 notifies the priority processing circuit 9 that there is a wait instruction by the wait instruction signal group 105.

When the notified waiting instruction enters execution, the waiting instruction is transmitted from the priority processing circuit 9 to the waiting instruction control circuits 5 to 8.
Is reset by a reset signal group 112 output to

The priority processing circuit 9 collectively receives the waiting instruction signal group 105 and outputs an instruction execution signal 106 and a port number signal 108 so as to equalize the number of instructions processed from the requesters 1-4. If the currently executing instruction is a continuous read instruction (CR) or a continuous write instruction (CW), the requester issuing the instruction waits during the inter-port cycle period. Is processed with priority. The currently executed instruction and the port number are confirmed by inputting the currently executed instruction information signal 113 output from the instruction processing circuit 10.

When the priority processing circuit 9 issues an instruction to execute an instruction and the busy signal 107 input from the instruction processing circuit 10 is "0" (empty state), it is determined that the instruction can be executed. Then, a reset signal group 112 is sent to the corresponding waiting instruction control circuits 5 to 8 to reset the waiting instruction that has entered execution.

The instruction processing circuit 10 has an instruction execution signal 106
When an instruction to execute an instruction is received by the port number signal 108 and no other instruction is being executed at that time, execution of the instruction is immediately started and the busy signal 1 is output.
07 is set to “1” and the memory access control signal 110
And outputs an executing instruction information signal 113,
Thereafter, the reply go signal 109 and the currently executed port number signal 114 are output.

When the instruction processing circuit 10 is executing another instruction, it performs busy management and waits for the execution of the instruction.

The reply control circuit 11 receives the reply go signal 109 and the currently executed port number signal 114, outputs a reply signal group 111 to the requesters 1 to 4, and returns a reply.

Next, the operation of the interface circuit of the multi-port storage device configured as described above will be described with reference to FIG.

Here, for the sake of simplicity, only the requesters 1 and 2 are used, and each requester and the present storage device operate with the same clock.
Further, it is assumed that the cycle periods between instructions and between requesters and the reply timing of instructions are as shown in Tables 3 and 4, respectively. One clock cycle is described as 1T.

[0030]

[Table 3]

[0031]

[Table 4]

To write at high speed, the requester 1
When CWs are successively issued at T and 7T, the CW issued at 5T is held in the buffer 1 in the waiting instruction control circuit 5 at 6T, and there is no other instruction currently being executed. The processing is executed by the instruction processing circuit 10 at 7T. The waiting instruction control circuit 5 is configured to execute the first C
Since W has entered execution, buffer 1 is reset at 6T, but a second CW is received at 7T and 8T is received.
Is held in the buffer 1 again.

After setting the busy signal 107 to "1" at 7T, the instruction processing circuit 10 performs an operation for returning a reply to the requester 1 at 9T.

On the other hand, the requester 2 issues an NR at 6T, but the NR has been waiting in the buffer 1 in the waiting instruction control circuit 6 since 7T.

Next, the instruction to be executed by the priority processing circuit 9 is NR of the requester 2 because there is only one instruction in the waiting state at the time of 7T. Since the second CW in the standby state is in the waiting state, there are two CWs. Here, since the currently executing instruction is a CW (continuous write) designating continuous transfer, and the next CW from the same requester 1 is in a waiting state, the priority processing circuit 9 next instructs execution. The instruction is preferentially the second CW from requester 1. Therefore, the second CW
Is executed at 12T after waiting for the cycle period 5T, and a reply is returned at 13T.

The requester 1 has 8T and 13T.
Confirms the reply at
Issued at T and 15T. Since the instruction issued at 15T is the last instruction, NW (or NR)
To obtain information about the error being processed from the normal reply signal group 111.

The third and fourth instructions that the priority processing circuit 9 instructs to execute are also the third and fourth instructions from the requester 1 due to the priority processing, and the execution of the NR from the requester 2 is as follows. The fifth one.

[0038]

As described above, the interface circuit of the multi-port storage device according to the present invention executes the continuous read command (CR) or the continuous write command (CW) with priority when they are continuously received. In order to transfer several kilobytes of data, a continuous read command or a continuous write command is issued, and finally a normal read command (N
R) or issuing a normal write instruction (NW) can save the extra time generated by switching the requestor issuing the instruction,
In addition, since the requester can quickly issue the subsequent instruction, there is an effect that data transfer efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of FIG.

FIG. 3 is a block diagram showing an example of an interface circuit of a conventional multi-port storage device.

FIG. 4 is a timing chart showing the operation of the example of FIG.

[Explanation of symbols]

 1-4 port (requester) 5-8 waiting instruction control circuit 9 priority processing circuit 10 instruction processing circuit 11 reply control circuit 12 instruction selection circuit 13 instruction processing circuit 101-104 instruction signal 105 waiting instruction signal group 106 instruction execution signal 107 busy Signal 108 Port number signal 109 Reply go signal 110 Control signal 111 Reply signal group 112 Reset signal group 113 In-process instruction information signal 114 Current execution port number signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 12/00-12/06 G06F 13/16-13/18

Claims (2)

(57) [Claims] A plurality of ports connected to each of the plurality of ports, which are capable of waiting for execution of up to two instructions from the corresponding port, outputting a wait instruction signal in accordance with the order of reception, and a corresponding reset signal for each port; A plurality of waiting instruction control circuits for resetting the waiting instruction that has entered and executed; and inputting a waiting instruction signal from the plurality of waiting instruction control circuits, a busy signal from the instruction processing circuit, and an executing instruction information signal. Priority processing is performed, a request for the next instruction to be executed is made to the instruction processing circuit by an instruction execution signal and a port number signal, and a reset signal for resetting the instruction that has entered execution is sent to the plurality of waiting instructions. A priority processing circuit for outputting to the control circuit; and an instruction execution, busy management and reply by receiving the instruction execution signal and the port number signal. And outputs the busy signal and the execution instruction information signal to the priority processing circuit, outputs a reply go signal and a currently executed port number signal to a reply control circuit, and a control signal for memory access. The command processing circuit that outputs the reply go signal and the currently executed port number signal and outputs a reply signal to each of the plurality of ports. When the circuit is executing a continuous write instruction or a continuous read instruction, and there is an instruction to be continued in the standby instruction control circuit for the same port, the priority processing circuit preferentially receives the standby instruction. An interface circuit for a multi-port storage device. 2. The method according to claim 1, wherein when the instruction processing circuit starts executing the continuous write instruction or the continuous read instruction, the reply control circuit immediately outputs a reply signal to a corresponding port. An interface circuit for a multi-port storage device according to claim 1.