JPH064401A - Memory access circuit - Google Patents

Abstract

PURPOSE:To realize a function by which an arbitrary master device can access an arbitrary memory device at a high speed, by a simple circuit configuration, in a computer system. CONSTITUTION:The memory access circuit for executing an access to an arbitrary one in M pieces of divided memories 102 from an arbitrary one in NXK pieces of master devices 101 is constituted of K pieces of memory control modules 103 for executing switching between N pieces of master devices 101 and M pieces of divided memories 102, respectively. Each memory control module 103 executes arbitration control, etc., of a competition of a memory access request from each master device 101. An interface opposed to each divided memory 102 in each memory control module 103 is selected so as to be connected successively to the divided memory 102 by a selecting means 104 provided at every divided memory 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention combines a plurality of memory devices with a plurality of master devices such as a processor and a DMA channel for accessing them in a computer system, and allows any master device to control any memory device. The present invention relates to a memory access circuit that enables access.

[0002]

2. Description of the Related Art In computer systems, processors and I / O
0 device accesses the memory system, but the increase in the number of access paths from a plurality of master devices to the memory system due to the increase in the number of processors, the increase in the number of processors, the increase in the number of processors, the increase in the number of processors, the increase in the number of processors, Speeding up is an issue.

For example, assume that the total number of processors and I / O devices is N, and memory access is performed at a speed of X bytes / second. In this case, the memory system has a total of N
It needs to be accessible at a speed of × X bytes / second.

If this speed is very high, there is no memory device that can realize this speed, or it is very expensive even if it exists, and the memory capacity per chip is small. There is a possibility that the memory system cannot be realized.

As a conventional technique for solving the above problems,
As shown in FIG. 9, the memory is divided into a plurality of divided memories 90.
Master device group 901 such as a processor divided into two
There is a method of connecting the divided memory groups 902 with a switch 903.

In this method, when the master devices 901 access different divided memories without collision, the divided memories 902 can access each other without causing a collision. Therefore, even if the required speed for each divided memory 902 is about X bytes / second, the entire memory system can have the same speed. If you look at it, higher speeds can be realized. Of course, if access concentrates on the same divided memory 902, the access speed of the entire memory system decreases, but if the concentration of access does not occur so much, practically sufficient performance can be realized.

[0007]

However, in the above-mentioned conventional technique, it is necessary to connect an arbitrary master device 901 and an arbitrary divided memory 902 with a small delay, and
The ability to process at the maximum access speed of the entire memory system is required.

Further, assuming that the number of master devices 901 is N, the number of divided memories 902 is M, the number of connection signal lines between the switch 903 and the master device 901 is Cd, and the number of connection signal lines between the switch 903 and the divided memory 902 is Cm. , The total number of connection signal lines is (N × Cd) + (M × Cm).

For example, N = M = 2, and switch 903
The data width between the master device 901 and the master device 901 and between the switch 903 and the divided memory is 36 (32 data + 4 parity, bidirectional), and the switch 903 and the master device 901.
Address width between 36, switch 903 and divided memory 9
If the address width between 02 is 24, the total number of connection signal lines is {2 × (36 + 36)} + {2 × (36 + 2).
4)} = 264 (of which 144 are bidirectional).

There is a problem in that it is difficult to realize this with an LSI such as one gate array due to the limitation of the number of pins and the number of internal input / output lines. This is especially true when high processing capacity is required as described above.

It is an object of the present invention to realize a function that allows an arbitrary master device to access an arbitrary memory device at high speed with a simple circuit configuration.

[0012]

FIG. 1 is a block diagram of the present invention. According to the present invention, from any one of the N × K (first predetermined number) master devices 101 of # 1 to # N × K, the M (second predetermined number) of # 1 to #M is selected. Split memory 102
It is premised on a memory access circuit for accessing any one of them.

First, each has K (fourth predetermined number) memory control modules 103 of # 1 to #K having the following functions. That is, first, the memory control module 103 has an interface for N master devices 101 out of N × K master devices 101 and an interface facing the M divided memories 102.

Next, the memory control module 103 has a predetermined operation clock BCLK and a predetermined mode signal MODE.
Work based on. Then, the memory control module 1
Reference numeral 03 denotes a master device 101 selected in accordance with a priority determined by a predetermined rule when a plurality of master devices 101 make memory access requests to the same divided memory 102 in the same phase of the operation clock BCLK. Based on the memory access request from the operation clock BCLK, the mode signal MODE (# 1 to
The divided memory 102 corresponding to the memory access request is accessed in a phase designated based on each of #K).

Further, when a plurality of master devices 101 make memory access requests to different divided memories 102 in the same phase of the operation clock BCLK, the memory control module 103 sends a plurality of master devices 101 from the plurality of master devices 101. Based on each memory access request, the mode signal MO of the operation clock BCLK
Different divided memories 102 corresponding to respective memory access requests are simultaneously accessed in a phase designated based on DE (each of # 1 to #K).

And, it is provided for each divided memory 102,
The divided memory 102 and K memory control modules 1
03, each of the interfaces facing the divided memory 102 is selectively connected in the phase of the operation clock BCLK at which the memory control module 103 corresponding to the interface accesses the divided memory 102. It has M selection means 104.

[0017]

In the present invention, N × K master devices 101 are used.
A memory access circuit for accessing any one of the M divided memories 102 from any one of
Each of the divided memories 102 is configured with K memory control modules 103 for switching between N master devices 101 and M divided memories 102, and an interface facing each divided memory 102 is provided for each divided memory 102. A feature is that the selection means 104 is selected so as to be sequentially connected to the divided memory 102.

With this configuration, each memory control module 103 can be easily configured by a gate array chip or the like, and furthermore, each memory control module 103 performs arbitration control of competition among a plurality of master devices 101 and selects it. The means 104 includes each memory control module 103.
Since the interfaces facing the divided memories 102 in the above are simply sequentially selected, the entire memory access control can be easily realized.

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings. In the following embodiments, the present invention is that the real memory 307 and the control memory 308 in the message communication device 103 of FIG. 3 described later are configured as divided memories, and the virtual memory controller 209 is configured to have a switch function. Most relevant. <Configuration of Embodiment of the Present Invention> Overall Configuration FIG. 2 is a configuration diagram of a network to which the embodiment of the present invention is applied.

A plurality of nodes 202 (see FIG.
Are indicated by numbers such as # 000, # ***, # %%%, etc.)
Are connected.

At node 202, processor bus 2
A plurality of processors 204 are connected to 05, and the processor bus 205 is accommodated in the message communication device 203. The message communication device 203 includes the processor bus 20.
5, the processor 204 processes the message data transmitted or received, and also processes the frame in which the message data input to or output from the optical fiber ring 206 is stored. This message communication device 203
The configuration of the buses within is most relevant to the present invention. Configuration of Message Communication Device 103 Next, FIG. 3 shows the node 2 of FIG. 2 in the embodiment of the invention.
2 is a configuration diagram of a message communication device 203 in 02. FIG.

The real memory 307 functions as a communication buffer that temporarily holds message data. Control memory 3
08 is, for each virtual page address in the virtual storage space used for message communication, the real page address and its virtual page address if the virtual page address is allocated to the real page address in the real memory 307. Data indicating the page status (communication status) of the page address is stored.

As described above, in the message communication device 103 according to the embodiment of the present invention, the memory for storing data is not configured as a single memory device, but a real memory 307 and a divided memory of the control memory 308. The feature is that it is configured as.

The processor bus interface 312 is
2 is connected to the external bus 301 and accommodates the message data and the like input from the processor 204 of FIG. 2 via the processor bus 205 via the external bus 301 and the virtual memory controller 309. 307 and vice versa, the message data and the like input from the real memory 307 via the virtual memory controller 309 and the external bus 301 are output to the processor 204 via the processor bus 205.

Further, the processor bus interface 31
2 exchanges communication control data with the CPU 313 via the external bus 301, the bus coupling unit 311, and the CPU bus 302.

Although not shown in FIG. 2, two processor buses 205 are provided for each node in FIG. Therefore, the processor bus interface 312 also
Two # 0 and # 1 are provided corresponding to each processor bus 205. Then, the # 0 processor bus interface 312 uses the control line 319 to perform contention control when the # 0 and # 1 processor bus interfaces 312 access the external bus 301. Further, the # 0 processor bus interface 312 is connected to the control lines 321 and 322.
Via a CPU bus arbiter 314 and I /
While exchanging control data regarding bus use with the O controller 315, competition control of the external bus 301 is performed, and opening / closing control of the bus coupling unit 311 is performed via the control line 320 when necessary.

The network control circuit 310 sends the frame from the CPU 313 to the CPU bus 302, I.
A control memory 308 via a control memory access bus 306 based on a transmission command input via the I / O controller 315 and the network command / result bus 303.
While accessing, read message data to be transmitted from the real memory 307 via the virtual memory controller 309 and the network data transmission bus 305, construct a transmission frame including the message data, and send it to the optical fiber ring 206. The transmission result is sent to the network command / result bus 303 and the I / O controller 31.
5 and the CPU 313 via the CPU bus 302.

Further, the network control circuit 310 receives the frame from the optical fiber ring 206, and the control memory 308 via the control memory access bus 306.
Access the received frame to another node 2
Relay to 02. Alternatively, the message data in the received frame is extracted and the network data reception bus 30
4 to the real memory 307 via the virtual memory controller 309, and the reception result is notified to the CPU 313 via the network command / result bus 303, the I / O controller 315, and the CPU bus 302.

The CPU 313 is connected to the CPU bus 302, and is connected to the CPU bus 302 at the start of operation.
It operates according to a control program written from the PROM 316 to the program RAM 317 connected to the CPU bus 302.

The CPU 313 has a CPU bus 302,
Communication control data is exchanged with the processor bus interface 312 via the bus coupling unit 311 and the external bus 301.

Further, the CPU 313, when transmitting a frame, uses the CPU bus 302, the I / O controller 315,
And output a send command to the network control circuit 310 via the network command / result bus 303, and thereafter
From the network control circuit 310, a network command /
Result bus 303, I / O controller 315, and CP
The transmission result notification is received via the U bus 302. Conversely, the CPU 313 receives from the network control circuit 310 the network command / result bus 303, the I / O controller 315, and the CPU bus 3 when receiving a frame.
A reception result notification is received via 02.

Further, the CPU 313 has a CPU bus 302.
The page state data (data indicating the communication state) of each virtual page address in the control memory 308 is accessed via the CPU memory 302 and the virtual page address of each virtual page address in the control memory 308 is accessed via the CPU bus 302 and the virtual memory controller 309. The page address data and the real memory 307 are accessed.

The I / O controller 315 is connected to the CPU bus 302 and accommodates a peripheral device bus 318 to which external peripheral devices are connected. In addition, I / O controller 3
As described above, the relay unit 15 relays the transmission command, the transmission result notification, or the reception result notification exchanged between the CPU 313 and the network control circuit 310 via the CPU bus 302 and the network command / result bus 303.

Further, the I / O controller 315 is a CP
The address that U313 uses to access the external bus 301 is C
When specified for the PU bus 302, the control line 322
To the processor bus interface 312 of # 0 via
Outputs an external bus access request.

The CPU bus arbiter 314 is a C bus from the processor bus interface 312 via the control line 321.
When the PU bus access request (bus grant request) is received, the bus use request (bus grant request) is output to the CPU 313 via the control line 323, and the CPU 3
13 receives a bus use permission (bus grant acknowledge) from the control line 323 through the control line 323, and based on that, the CPU
Bus access permission (bus grant acknowledge) is sent via the control line 321 to the # 0 processor bus interface 3
Return to 12.

The virtual memory controller 309 is
Processor bus interface 312 and real memory 307
Data exchanged with the external bus 301 via the external bus 301, C
Data transmitted and received between the PU 313 and the real memory 307 or the control memory 308 via the CPU bus 302, and between the network control circuit 310 and the real memory 307 via the network data reception bus 304 or the network data transmission bus 305. The switching control and the contention control of the exchanged data are performed. Configuration of Periphery of Virtual Memory Controller 309 FIG. 4 is a more detailed configuration diagram of the periphery of the virtual memory controller 309 of FIG.

The virtual memory controller 309 is
It is composed of two virtual memory control modules (VMC) 401 of # 0 and # 1. # 0 VMC 401
Is a CPU bus 302 and a network data transmission bus 3
05 performs switching control and contention arbitration control when the real page address in the real memory 307 or the control memory 308 is accessed, and is connected to the real memory 307 by the address bus 407 and the data bus 403, and via the data bus 404. It is connected to the real page address input / output terminal of the control memory 308.

The VMC 401 of # 1 performs switching control and arbitration control of contention when the external bus 301 and the network data reception bus 304 access the real page address in the real memory 307 or the control memory 308, and the address bus 408 and It is connected to the real memory 307 by the data bus 403, and is connected to the real page address data input / output terminal of the control memory 308 via the data bus 404.

The VMCs 401 of # 0 and # 1 are clocked by the clock BCL.
It operates in synchronization with K and a clock B2CLK that is in synchronization with K. MODE signal is input to VMC401 of # 0,
The signal obtained by inverting the MODE signal by the inverter is input to the VMC 401 of # 1.

The address selector 411 provided in the actual memory 307 operates from the # 0 VMC 401 to the address bus 4
The address designated via 07 and the address designated from the VMC 401 of # 1 via the address bus 408 are alternately selected based on the clocks BCLK and B2CLK.

The data bus portion 405 of the CPU bus 302
And the data bus portion 40 of the control memory access bus 306
6 is connected to a page state data input / output terminal of the control memory 308 via a buffer 402 (not shown in FIG. 3).

The address selector 412 provided in the control memory 308 has an address designated by the address bus portion 409 of the CPU bus 302 and an address designated by the address bus portion 410 of the control memory access bus 306. And the clocks BCLK, B2C
Alternately select based on LK. Configuration of Virtual Memory Control Module 401 FIG. 5 is a configuration diagram common to the virtual memory control modules 401 of # 0 and # 1 in FIG.

The local bus interface 501 has a C
The PU bus 302 or the external bus 301 is accommodated, and the network data bus interface 502 accommodates the network data transmission bus 305 or the network data reception bus 304.

The real memory interface 506 accommodates a data bus 403 and an address bus 407 or 408 connected to the real memory 307, respectively. The control memory interface 507 accommodates the data bus 404 connected to the control memory 308.

A local bus interface 501 and a real memory interface 506, a network data bus interface 502 and a real memory interface 506.
Are connected by a bus including a data bus and an address bus, and the local bus interface 501 and the control memory interface 507, and the network 201 data bus and the control memory interface 507 are connected by a data bus.

The control circuit 503 controls the clocks BCLK and BCLK.
2CLK, MODE signal or its inversion (MODE
-) Operating on the basis of a signal, controlling the local bus interface 501 or the network data bus interface 502 by the control line 504, and controlling the real memory interface 506 and the control memory interface 507 via the control line 505, while the CPU bus 302 Alternatively, the external bus 301 and the network data transmission bus 305
Alternatively, the network data reception bus 304 may be the real memory 3
07 or switching control when accessing the control memory 308 separately, and arbitration control of competition when these access the real memory 307 or the control memory 308 simultaneously.

The operation of the embodiment of the present invention having the above configuration will be described. <Overall operation of inter-processor communication> Now, in FIG. 2 and FIG. 3, for example, message data is sent from one processor 204 in the node 202 of # 000 to another processor 204 in the node 202 of # ***. The overall operation when transmitting will be described.

In this case, the message data transmitted from one processor 204 in the node # 000 is the message communication device 203 in that node (hereinafter, the message communication device 203 in # 000) via the processor bus 205. Call)) to the real memory 307,
It is sent to the real memory 307 of the message communication device 203 in the node 202 of # *** (hereinafter referred to as the message communication device 203 of # ***), and then the destination from the real memory 307 via the processor bus 205. The processor 204
Transferred to. That is, the real memory 307 of each message communication device 203 functions as a communication buffer. Communication Method Between Message Communication Devices 203 Here, a special method called a network virtual storage method is applied to communication of message data between the message communication devices 203.

First, in the entire network 201 of FIG.
A virtual memory space is defined. This virtual storage space is divided into a plurality of virtual pages, and message data is communicated via these virtual pages. For example, the virtual storage space is divided into virtual page addresses of 0000 to FFFF pages (hexadecimal number). One virtual page has a fixed length (for example, 8 kilobyte length) data length that can sufficiently accommodate a packet that is one unit of message data. Unless otherwise specified, the virtual page address and the dictated real page address are represented by hexadecimal numbers.

Next, the message communication device 203 of each node 202 connected to the network 201 is allocated every predetermined number of pages, for example, every 16 pages, of this virtual storage space. For example, the message communication device 203 of the # 000th node 202 is allocated to the 0000 to 000F page, the message communication device 203 of the # 001th node 202 is allocated to the 0010 to 001F page, and so on. ** 0-*** F page and %%% 0-%%% F page (3 digit *
And% are arbitrary numbers in hexadecimal numbers 0 to F), the message communication device 203 of each node 202 of the # *** th and # %%% th is assigned.

Therefore, in the above example, the network 20
1, a maximum of 3096 message communication devices 203 from # 000 to #FFF can be connected. On the other hand, the real memory 307 in each message communication device 203 is divided into a plurality of real pages each having the same data length as the above-mentioned virtual page. The page capacity of the real memory 307 may be much smaller than the page capacity of the virtual storage space, and may be, for example, about 64 to 256 pages.

Next, in the control memory 308 of each message communication device 203, as shown in FIG. 6, control data for all virtual page addresses are stored. As shown in FIG. 6, the control data of each virtual page address indicates the real page address data of the real memory 307 in the own message communication device 203 associated with the virtual page address and the communication state of the virtual page address. And page status data shown.

Then, as an initial state, each node 202
In the control memory 308 of the message communication device 203 in the internal message communication device 203, the virtual page address assigned to the node 202 is set to an arbitrary empty page in the real memory 307 of the message communication device 203 by the network reception control function of the CPU 313. The real page address of the network receiving buffer provided in the above and the receiving buffer allocation state VP as the page state are respectively written in advance. The network reception control function is a CP
This is realized by the U313 executing the control program stored in the program RAM 317.

For example, the # 000 message communication device 203
In the control memory 308 of the own message communication device 2
As shown in FIG. 6, each virtual page address of 0000,0001, ..., 000F pages allocated to the 03 is assigned to each real page of s, q, ..., p in the real memory 307. The address has been written and the page status VP indicating the receive buffer allocation status has been written.

In the control memory 308 of the message communication device 203 of # ***, the own message communication device 20
As shown in FIG. 6, for each virtual page address of **** 0, *** 1, ..., *** F page assigned to
The page status indicating the receive buffer allocation status in which each real page address of v, u, ..., T in the real memory 307 is written.
VP is written.

Similarly, the message communication device 203 of # %%%
In the control memory 308 of the own message communication device 2
The %%% 0, %%% 1, ..., %%% F virtual page addresses allocated to 03 are assigned to y, w, and w in the real memory 307 as shown in FIG. , X are written, and the page state VP indicating the receive buffer allocation state is written.

Now, by the transfer operation described later, for example, # 000
Message data is transferred from one processor 204 in the node # 000 202 to a network transmission buffer (to be described later) whose real page address is r in the real memory 307 of the message communication device 203 of FIG. To do.

The network transmission control function of the CPU 313 analyzes the destination address part in the header of the message data stored in the network transmission buffer in the real memory 307 via the CPU bus 302 and the virtual memory controller 309. By doing so, the virtual page address assigned to the node 202 in which the processor 204 corresponding to the destination address is accommodated is determined as the one whose page state is the buffer unallocated state NA. In the example of FIG. 6, for example, the virtual page address *** 2 is determined. The network transmission control function is realized by the CPU 313 executing the control program stored in the program RAM 317.

Next, the network transmission control function of the CPU 313 writes the real page address of the network transmission buffer in which the above-mentioned message data is stored in the determined virtual page address in the control memory 308, and the page Change the status from the buffer unallocated status NA to the transmission status SD. In the example of FIG. 6, the real page address r and the transmission state SD are set to the virtual page address *** 2, for example.

The network transmission control function of the CPU 313 is the transmission F function in the I / O controller 315.
The virtual page address and the transfer length of the message data described above are written to the IFO via the CPU bus 302 together with the transmission command.

When the network control circuit 310 reads the above-mentioned transmission command or the like from the transmission FIFO in the I / O controller 315 via the network command / result bus 303, the virtual page added to the transmission command. An address is designated to the control memory 308 via the control memory access bus 306, the real page address set to the above-mentioned virtual page address is read from the control memory 308, and DMA transfer (not shown) in the virtual memory controller 309 is performed. Set to the register for use.

Then, the network control circuit 310 is
The page data of the real page address in the real memory 307 including the message data to be transmitted to the virtual memory controller 309 is transferred to the network control circuit 310 via the network data transmission bus 305.
To DMA transfer.

The network control circuit 310 extracts message data corresponding to the transfer length of the message data added to the send command from the page data described above, and the virtual page address added to the message data and the send command. And a transmission frame including the transfer length of the message data and generating the transmission frame.
Send to 6. The token ring network method is adopted as the frame transmission method of the optical fiber ring 206, and the network control circuit 310 can send a transmission frame only when a free token circulating on the optical fiber ring 206 is acquired. .

In the example of FIG. 6, a transmission frame including the virtual page address *** 2 and the message data stored in the real page address r in the real memory 307 from the message communication device 203 of # 000 is It is sent to the optical fiber ring 206.

The above-mentioned transmission frame is transmitted to another node 202 (see FIG. 2) connected to the optical fiber ring 206.
Are sequentially transferred to. When the network control circuit 310 of the message communication device 203 in each node 202 fetches the transmission frame from the optical fiber ring 206, the page state corresponding to the virtual page address stored in the transmission frame is set to the control memory access bus 306. Read from the control memory 308 via the, and whether the page status is the receive buffer allocation status VP, that is, whether the virtual page address is assigned to the message communication device 203 of the own node 202, or the page It is determined whether or not the state is the transmission state SD, that is, whether or not the transmission frame is transmitted by the own network control circuit 310.

When the network control circuit 310 determines that the page state of the virtual page address stored in the transmission frame is the reception buffer allocation state VP,
The message data stored in the transmission frame is taken into the real memory 307 as follows.

That is, the network control circuit 310 first designates the virtual page address stored in the transmission frame to the control memory 308 via the control memory access bus 306, and the control memory 308 changes the virtual page address to the above virtual page address. The set real page address is read out and set in a DMA transfer register (not shown) in the virtual memory controller 309. Then, the network control circuit 310 causes the virtual memory controller 309 to DMA-transfer the message data included in the transmission frame to the above-mentioned real page address in the real memory 307 via the network data reception bus 304.

After that, the network control circuit 310
The virtual page address stored in the transmission frame is
Control memory 30 via control memory access bus 306
8 is specified, and the page status of the virtual page address is changed from the reception buffer allocation status VP to the reception completion status RD.

Further, the network control circuit 310 is
The virtual page address extracted from the transmission frame and the transfer length of the message data are written into the reception FIFO in the / O controller 315 via the network command / result bus 303 together with the result code indicating the success or failure of the reception.

Finally, the network control circuit 310
After writing the reception success notification in the response area in the above-mentioned transmission frame received from the optical fiber ring 206, the transmission frame is sent to the optical fiber ring 206 again.

For example, in the example of FIG. 6, the network control circuit 310 of the message communication device 203 of # *** is # 000.
The message stored in the transmission frame is determined by determining that the page state on the control memory 308 of the virtual page address *** 2 stored in the transmission frame from the node 202 is the reception buffer allocation state VP. The data is transferred to the real memory 30 having the real page address u set to the virtual page address *** 2 of the control memory 308.
After fetching in the network reception buffer in 7, the page state of the virtual page address *** 2 of the control memory 308 is changed from the reception buffer allocation state VP to the reception completion state RD.

The above-mentioned reception result notification is received by the CPU 313 via the CPU bus 302. That is, CP
The U313 network reception control function uses the reception F in the I / O controller 315 via the CPU bus 302.
When the above reception result notification is received from the IFO and if the result code is successful in reception, the virtual page address which is a part of the reception result notification is designated to the control memory 308 via the CPU bus 302, and the page state Read the real page address.

If the page state described above is the reception completion state RD, the network reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309, and Separates the real page specified by the page address from the network receive buffer and connects it to the processor send-wait buffer queue.

Thereafter, the network reception control function of the CPU 313 controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to connect an arbitrary empty page to the network reception buffer, and further Control memory 3 via CPU bus 302 with a virtual page address that is part of the reception result notification
08 is accessed, and the real page address of the above-mentioned empty page and the reception buffer allocation state VP as the page state are written to the virtual page address.

After that, the processing for the processor transmission waiting buffer queue in the real memory 307 is performed by the CPU 31.
3 from the network reception control function to the processor transmission control function described later.

On the other hand, the network control circuit 310 reads the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, and as a result, the page state is neither the reception buffer allocation state VP nor the transmission state SD. If it is determined that the transmission frame is transmitted, the transmission frame is directly transmitted to the optical fiber ring 206.

For example, in the example of FIG. 6, the network control circuit 310 of the # %%% message communication device 203 uses # 000
By determining that the page state on the control memory 308 of the virtual page address *** 2 stored in the transmission frame from the node 202 of the node 202 is neither the reception buffer allocation state VP nor the transmission state SD, the transmission frame is left as it is. It is sent to the optical fiber ring 206.

Optical fiber ring 206 as described above
The transmission frame sequentially transferred above returns to the network control circuit 310 of the message communication device 203 in the node 202 which is the transmission source.

The network control circuit 310 of the transmission source
As a result of reading out the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, by determining that it is the transmission state SD,
It is determined that the transmission frame is the transmission frame transmitted by the own network control circuit 310.

In this case, the network control circuit 310
After confirming that the reception success notification is written in the response area of the received transmission frame, the control memory 308 of the control memory 308 corresponding to the virtual page address stored in the transmission frame is transmitted via the control memory access bus 306. The page state is changed from the transmission state SD to the transmission completion state SC.

Then, the network control circuit 310 is
The virtual page address extracted from the transmission frame is written to the reception FIFO in the I / O controller 315 via the network command / result bus 303 together with the result code indicating the success or failure of the transmission.

The above-mentioned transmission result notification is received by the CPU 313 via the CPU bus 302. That is, CP
The network transmission control function of the U313 is performed by the reception F in the I / O controller 315 via the CPU bus 302.
When the above result notification is received from the IFO, if the result code is successful, the virtual page address that is a part of the result notification is specified in the control memory 308 via the CPU bus 302, and the page status is changed. Read the real page address.

If the above-mentioned page state is the transmission completion state SC, the network transmission control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to make the above-mentioned real state. The real page specified by the page address is separated from the network send buffer and used as a free page.

After that, the network transmission control function of the CPU 313 controls the control memory 3 via the CPU bus 302 with the virtual page address which is a part of the above-mentioned transmission result notification.
08 is accessed, and the buffer unallocated state NA is written as the page state of the virtual page address.

As described above, the network 201 (see FIG.
In the above, one virtual storage space is defined, and a virtual page having a fixed data length that constitutes this space is assigned to each message communication device 203. Communication of message data between the message communication devices 203 is performed using this virtual page. As a result, blocking control and sequence control that are performed in normal packet communication are not required.

When the network control circuit 310 of the message communication device 203 in each node 202 on the optical fiber ring 206 receives a transmission frame, the network control circuit 310 in the control memory 308 uses the virtual page address stored in the transmission frame. By accessing the page state, the received transmission frame can be processed at high speed.

In addition, a response area is provided in the transmission frame transferred on the optical fiber ring 206, and the network control circuit 310 of the message communication device 203 in the node 202 on the reception side transmits the reception result of the transmission frame. It writes in the response area of the frame and sends it out again to the optical fiber ring 206. Therefore, by the time this transmission frame is transferred on the optical fiber ring 206 and returned to the transmission source, the message data transmission processing is completed, and the response from the reception side to the transmission source is sent using another frame. No need to notify. As a result, the communication protocol can be simplified and high-speed response processing can be performed.

Further, the communication of the message data between the message communication devices 203 is performed using the real memory 307 while the network control circuit 310 in the message communication device 203 accesses the control memory 308, and the processor 204 and the message communication device 203 communicate with each other. The communication of message data between 203 is performed by the message communication device 2 as described later.
The processor bus interface 312 in 03 uses the real memory 307 independently of the operation of the network control circuit 310 described above. Further, the correspondence between the message data stored in the real page address in the real memory 307 and the virtual page address in the virtual storage space is as described below, in which the CPU 313 sends the destination address in the header added to the message data. Based on. Therefore, between the processor 204 and the message communication device 203,
Message communication device 203 and message communication device 203
It is possible to efficiently perform the processing between them at high speed. From the processor 204 at the sender to the message communication device
Operation of Transferring Message Data to Device 203 Next, from one processor 204 in the source node 202 (# 202 node 202 in the example of FIG. 6) to the real memory 307 of the message communication device 203 in that node, The operation when the message data is transferred will be described.

First, the processor reception control function of the CPU 313 accesses the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to connect the processor reception buffer queue to the free buffer queue in the real memory 307. Connect the free buffer that is being used. The processor reception control function is a function realized by the CPU 313 executing the control program stored in the program RAM 317.

The processor reception control function of the CPU 313 activates, for example, the # 0 processor bus interface 312 via the CPU bus 302, the bus coupling unit 311, and the external bus 301, and sends a command to the interface 312. The start address of the above-mentioned processor receive buffer queue is notified.

The processor bus interface 312 is
The message data transferred from the processor 204 via the processor bus 205 is received, and the received message data described above is updated while sequentially updating the buffer address with the start address as the reception start address.
External bus 301 and virtual memory controller 30
9 is sequentially transferred to an empty buffer connected to the processor reception buffer queue in the real memory 307.

The processor bus interface 312 is
When there is no free buffer connected to the processor reception buffer queue, the free buffer is automatically stopped, and the fact is notified to the CPU 313 via the external bus 301, the bus coupling unit 311, and the CPU bus 302.

The processor reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to separate the above-mentioned received buffer from the processor reception buffer queue and transmit it to the network. Connect to a buffer. Thereafter, the processing for the network transmission buffer in the real memory 307 is transferred from the processor reception control function of the CPU 313 to the network transmission control function described above, and the transmission source of the transmission source is transmitted in accordance with the communication method between the message communication devices 203 described above. From the real memory 307 in the message communication device 203 of the node 202 (# 000 message communication device 203 in the example of FIG. 6), the message communication device 203 of the node 202 (in the example of FIG. 6) in which the destination processor 204 is accommodated # *** message communication device 20
The message data transfer operation to the real memory 307 in 3) is executed. From the message communication device 203 on the receiving side to the process
Transfer Operation of Message Data to Server 204 Next, the real memory 3 of the message communication device 203 in the receiving node 202 (# 202 node 202 in the example of FIG. 6)
07 to one processor 204 in that node 202
The operation when the message data is transferred will be described below.

When the network control circuit 310 succeeds in receiving the transmission frame, as described above, the CPU 313.
The network reception control function of (1) connects the received message data to the processor transmission waiting buffer queue in the real memory 307.

On the other hand, the CPU transmission control function of the CPU 313 is the CPU bus 302 and the bus coupling unit 31.
For example, the # 0 processor bus interface 312 is activated via 1 and the external bus 301, and the interface 312 is notified of the start address of the above-mentioned processor transmission waiting buffer queue.

The processor bus interface 312 is
While sequentially updating the buffer address with the start address as the transmission start address, the real memory 30 is accessed via the external bus 301 and the virtual memory controller 309.
7 sequentially reads the message data stored in the buffer connected to the processor transmission waiting buffer queue, analyzes the destination address part in the header of the message data, and transfers the message data to the processor bus 205. Via the destination processor 204. <Operation centering on virtual memory controller 309> As described above, in the embodiment of the present invention, the communication of message data between the message communication devices 203 is performed by the network control circuit 310 in the message communication device 203 through the control memory 308. Message data communication between the processor 204 and the message communication device 203 is performed using the real memory 307 while accessing, and the processor bus interface 312 in the message communication device 203 is used.
However, the real memory 307 is used independently of the operation of the network control circuit 310 described above. Furthermore, the CPU 313 associates the message data stored at the real page address on the real memory 307 with the virtual page address on the virtual memory space by the control memory 308 and the real memory 30.
7 is used.

Network control circuit 31 as described above
0, processor bus interface 312, and CPU
In order to efficiently access the control memory 308 or the real memory 307 by the 313, in the message communication device 103 of FIG. 3, first, the real memory 307 and the control memory 308 are configured as physically divided memories, and The memory controller 309 controls access to the real memory 307 and the control memory 308.

That is, the virtual memory controller 30
Reference numeral 9 denotes data exchanged between the processor bus interface 312 and the real memory 307 via the external bus 301, the CPU 313 and the real memory 307 or the control memory 30.
8, switching control of data transmitted / received via the CPU bus 302, data exchanged between the network control circuit 310 and the real memory 307 via the network data reception bus 304 or the network data transmission bus 305, and Performs competition control.

Further, in the embodiment of the present invention, the virtual memory controller 309 is configured not by one LSI chip but by two virtual memory control modules (VMC) 401 of # 0 and # 1. The address selector 411 in the memory 307 and the address selector 412 in the control memory 308 have VMCs # 0 and # 1.
By alternately selecting each address output of 401,
A feature is that the system configuration is improved with a simple configuration and simple control. Operation of VMC 401 of # 0 First, the VMC 401 of # 0 is the CPU 313 via the CPU bus 302 or the network data transmission bus 305.
In accordance with a request from the network control circuit 310 via the, the access control of the data in the real memory 307 or the real page address data in the control memory 308 is performed.

First, when the CPU 313 accesses the data in the real memory 307 via the CPU bus 302 and the VMC 401 of # 0, for example, as described above, 1) the CPU 313 receives data for the processor on the real memory 307. When controlling the buffer queue, the network transmission buffer, the network reception buffer, the processor transmission waiting buffer queue, or the empty buffer queue, 2) the CPU 313 is stored in the network transmission buffer in the real memory 307. For example, when the destination address part in the header of the message data is analyzed.

In this case, the address designated from the # 0 VMC 401 via the address bus 407 is designated to the real memory 307 via the address selector 411, and the # 0 VMC 401 and the real memory 307 are designated via the data bus 403. Message data and the like are exchanged between the memories 307.

When the CPU 313 accesses the real page address data in the control memory 308 via the CPU bus 302 and the VMC 401 of # 0, for example, as described above, 1) the network reception control function of the CPU 313 is , The node 202 including the own CPU 313 in the initial state
When the real page address of the network reception buffer provided in an arbitrary free page in the real memory 307 is written in advance in the virtual page address (see FIG. 6) on the control memory 308 assigned to 2), the network of the CPU 313 Since the message transmission control function puts the message data to be transmitted into the transmission state, the real page address of the network transmission buffer in which the message data to be transmitted is stored is stored in a predetermined virtual page address on the control memory 308. When allocating the communication buffer by writing, 3) the network reception control function of the CPU 313 separates the memory data, which has been successfully received, from the network reception buffer and connects it to the processor transmission waiting buffer queue. A given virtual page If you read the real page address from the address, and the like.

In this case, the address directly designated from the address bus portion 409 of the CPU bus 302 is designated to the control memory 308 via the address selector 412, and the # 0 VMC 401 and the real memory are designated via the data bus 404. Real page address data is exchanged between 307.

On the other hand, when the network control circuit 310 accesses the data in the real memory 307 via the network data transmission bus 305 and the VMC 401 of # 0, the network control circuit 310, as described above,
The message data to be transmitted in the real memory 307 may be received by the DMA transfer.

In this case, the address designated by the # 0 VMC 401 through the address bus 407 is designated by the real memory 307 through the address selector 411, and the real memory 307 through the # 0 by the data bus 403. VM
The message data is transferred to C401.

When the network control circuit 310 accesses the real page address data in the control memory 308 via the network data transmission bus 305 and the VMC 401 of # 0, as described above, the network control circuit 310 DM of the above transmission message data
Before the A transfer, the virtual page address added to the transmission command is specified in the control memory 308 via the control memory access bus 306, and the real page address set in the above-mentioned virtual page address is set from the control memory 308. A DMA (not shown) in the VMC 401 that is read and # 0
It may be set in the transfer register.

In this case, the control memory access bus 3
The address directly specified from the address bus portion 410 of the control memory 30 via the address selector 412.
8 and the real memory 3 via the data bus 404.
The real page address data is transferred from 07 to the VMC 401 of # 0. Operation of VMC 401 of # 1 Next, the VMC 401 of # 1 uses the processor bus interface 312 via the external bus 301 or the network control circuit 3 via the network data receiving bus 304.
According to the request from 10, the access control of the data in the real memory 307 or the real page address data in the control memory 308 is performed.

The processor bus interface 312 connects the real memory 3 via the external bus 301 and the VMC 401 of # 1.
When accessing the data in 07, for example, as described above, 1) the processor bus interface 312 transfers the message data received from the processor 204 to the real memory 30.
When sequentially transferring to the empty buffer connected to the processor reception buffer queue in 7, the processor bus interface 312 is
In the case where message data stored in a buffer connected to the processor transmission waiting buffer queue in 07 are sequentially read and transferred to the processor 204,
and so on.

In this case, the address designated from the # 1 VMC 401 via the address bus 408 is designated to the real memory 307 via the address selector 411, and the # 1 VMC 401 and the real memory 307 are designated via the data bus 403. Message data and the like are exchanged between the memories 307.

Further, the processor bus interface 31
It is not specified in the embodiment of the present invention when the No. 2 accesses the real page address data in the control memory 308 via the external bus 301 and the VMC 401 of # 1.

On the other hand, when the network control circuit 310 accesses the real memory 307 via the network data reception bus 304 and the VMC 401 of # 1, as described above, the network control circuit 310 causes the optical fiber ring 206 (see FIG. The message data addressed to the own node 202 included in the transmission frame received from (see 2) may be DMA-transferred to the real memory 307.

In this case, the address designated by the # 1 VMC 401 through the address bus 408 is designated by the real memory 307 through the address selector 411, and the # 1 VMC 401 through the data bus 403. The message data is transferred to the memory 307.

When the network control circuit 310 accesses the control memory 308 via the network data receiving bus 304 and the VMC 401 of # 1, the network control circuit 310 transfers the received message data by DMA as described above. Previously, the virtual page address stored in the transmission frame that contained the message data was designated to the control memory 308 via the control memory access bus 306, and set to the above-mentioned virtual page address from the control memory 308. There is a case where the actual page address is read and set in a DMA transfer register (not shown) in the VMC 401 of # 1.

In this case, the control memory access bus 3
The address directly specified from the address bus portion 410 of the control memory 30 via the address selector 412.
8 and the real memory 3 via the data bus 404.
The real page address data is transferred from 07 to # 1 VMC 401. Access operation of page state data in control memory 308: CPU 313 via CPU bus 302; and network control circuit 310: control memory access bus 30
When accessing the page state data in the control memory 308 via 6 respectively, there are many cases as described above.

In the embodiment of the present invention, first, the CPU 313
Access the page state data in control memory 308, address bus portion 40 of CPU bus 302
The address directly specified by 9 is the address selector 41
2 is designated to the control memory 308 via the CPU bus 3
The page state data is directly transmitted and received between the CPU 313 and the control memory 308 via the data bus portion 405 of No. 02 and the buffer 402.

When the network control circuit 310 accesses the page state data in the control memory 308, the address directly designated by the address bus portion 410 of the control memory access bus 306 is controlled by the address selector 412. The page state data is directly exchanged between the network control circuit 310 and the control memory 308 via the data bus portion 406 of the control memory access bus 306 and the buffer 402. The actual memory access between VMC401 of # 0 and VMC401 of # 1.
Relationship between Process Cycles Next, the # 0 VMC 401 and the # 1 VMC 401 operate in synchronization with the clocks BCLK and B2CLK.

In this case, # 0 VMC 401 and # 1 VMC 401
The timing relationship of the actual memory access cycle between C401 will be described with reference to the timing chart of FIG.
7 (a) shows the system clock CLK (φ1, φ2), and FIG. 7 (b) shows the clock B generated based on CLK.
Indicates CLK. Each control signal for bus access control is output in synchronization with this clock BCLK. In this clock BCLK, each section sandwiched by "↑" indicates a bus cycle. FIG. 7C shows a clock B2CLK obtained by dividing the clock BCLK by two.

The VMCs 401 of # 0 and # 1 have the same configuration, but the MODE signal or (M
Depending on the logic state of the ODE-) signal, it operates based on different combinations of the timing of the clock BCLK and the timing of B2CL.

That is, first, the logic "0" is input to the control circuit 503 (see FIG. 5) of the # 0 VMC 401 as a MODE signal, for example. In this case, # 0 VMC40
As shown in FIGS. 7 (b), (c), and (d), the control circuit 503 of No. 1 has a bus cycle starting from the rising timing “↑” of the clock BCLK within the period in which the clock B2CLK is at the high level. The real memory interface 506 is controlled via the control line 505, and the real memory address (real page address) is output to the address bus 407 in response thereto.

In synchronization with this, the address selector 411 in the real memory 307 of FIG. 4 determines that the bus selector immediately before the bus cycle starting from the rising timing "↑" of the clock BCLK within the period in which the clock B2CLK is at the low level. In the cycle, the real memory address output from the # 0 VMC 401 to the address bus 407 is latched in an address register (not shown) in the real memory 307.

In the same bus cycle as the above-mentioned bus cycle in which the actual memory address is latched, VMC4 of # 0
The control circuit 503 of 01 controls the real memory interface 506 via the control line 505 as shown in FIGS. 7 (b), (c), and (d), and causes the data bus 403 to be used for it. Real memory data (message data, etc.) is exchanged with the real memory 307.

On the other hand, the control circuit 503 of the # 1 VMC 401
For example, the logic "1" is input to (see FIG. 5) as a (MODE-) signal obtained by inverting the logic of the MODE signal by an inverter (see FIG. 4).

In this case, the control circuit 5 of the # 1 VMC 401
03 is the clock BCL within the period in which the clock B2CLK is at the low level, as shown in FIGS.
In the bus cycle starting from the rising timing "↑" of K, the real memory interface 506 is controlled via the control line 505, and the real memory address is output to the address bus 407 in response thereto.

In synchronization with this, the address selector 411 in the real memory 307 of FIG. 4 determines that the bus immediately preceding the bus cycle starting from the rising timing "↑" of the clock BCLK within the period in which the clock B2CLK is at the high level. In the cycle, the real memory address output from the # 1 VMC 401 to the address bus 408 is latched in an address register (not shown) in the real memory 307.

In the same bus cycle as the above-mentioned bus cycle in which the actual memory address is latched, the VMC4 of # 1
The control circuit 503 of 01 controls the real memory interface 506 via the control line 505 as shown in FIGS. 7 (b), (e), and (f), and causes the data bus 403 to be used for it. Real memory data is exchanged with the real memory 307.

As can be seen from the above operation, the VMCs 401 of # 0 and # 1 can store the real memory 30 in the shortest two bus cycles.
7 can be accessed. When access is performed over a plurality of bus cycles, the VMCs 401 of # 0 and # 1 can alternately access the real memory 307 every other bus cycle. Control memory between # 0 VMC401 and # 1 VMC401
Relationship access cycle will now be described timing relationship between the control memory access cycle between VMC401 of VMC401 and # 1 and # 0.

When the control memory 308 is accessed via the VMC 401, the control memory 3 is accessed as described above.
This is the case where the real page address data in 08 is accessed.

Although the timing relationship in this case is not shown in particular, the control memory 308 has the same bus cycle as the bus cycle in which the address is designated when the address is designated through the address selector 412 in FIG. Real page address data can be exchanged within a cycle.

First, the address selector 412 in the control memory 308, for example, in the bus cycle starting from the rising timing of the clock BCLK within the period in which the clock B2CLK is at the high level, in the same bus cycle as the address of the CPU bus 302, for example. The control memory address (virtual page address) specified in the bus portion 409 is latched in an address register (not shown) in the control memory 308.

In the same bus cycle in which the control memory address is latched, the VMC of # 0
The control circuit 503 of 401 controls the control memory interface 507 via the control line 505, and uses the data bus 404 for the control memory interface 507 to send / receive real page address data to / from the control memory 308.

On the other hand, the address selector 412 in the control memory 308, for example, in the bus cycle starting from the rising timing of the clock BCLK within the period in which the clock B2CLK is at the low level, for example, the address of the control memory access bus 306 in the same bus cycle. The control memory address (virtual page address) specified in the bus portion 410 is latched in an address register (not shown) in the control memory 308.

In the same bus cycle in which the control memory address is latched, the VMC of # 1
The control circuit 503 of 401 controls the control memory interface 507 via the control line 505, and uses the data bus 404 for it to transfer the real page address data from the control memory 308.

As can be seen from the above operation, regarding the real page address data, the VMCs 401 of # 0 and # 1 can access the control memory 308 in one bus cycle at the shortest. If the access spans multiple bus cycles, # 0 and
The # 1 VMC 401 can alternately access the control memory 308 every other bus cycle. Between the CPU bus 302 and the control memory access bus 306
Of control memory access cycles via buffer 402
Relationship Next, the CPU bus 302 and the control memory access bus 30
The timing relationship of the control memory access cycle via the buffer 402 between the 6 will be described.

Control memory 308 via buffer 402
Access to the control memory 3 as described above.
This is the case when the page state data in 08 is accessed. Although the timing relationship in this case is not particularly shown, the control memory 308 uses the address selector 4 of FIG. 4 as in the case of accessing real page address data.
When an address is designated via 12, page status data can be exchanged within the same bus cycle as the bus cycle in which the address is designated.

First, the address selector 412 in the control memory 308, for example, in the bus cycle starting from the rising timing of the clock BCLK within the period in which the clock B2CLK is at the high level, as in the case of accessing the real page address data, In the same bus cycle, for example, the address bus portion 4 of the CPU bus 302
The control memory address (virtual page address) designated by 09 is latched in an address register (not shown) in the control memory 308.

In the same bus cycle in which the control memory address is latched, the VMC of # 0
The control circuit 503 of 401 controls the buffer 402 via a control line (not shown), and transmits / receives page state data to / from the data bus portion 405 of the CPU bus 302.

On the other hand, the address selector 412 in the control memory 308 is the same in the bus cycle starting from the rising timing of the clock BCLK within the period in which the clock B2CLK is at the low level, as in the case of accessing the real page address data. In the bus cycle, for example, the control memory address (virtual page address) specified in the address bus portion 410 of the control memory access bus 306 is latched in an address register (not shown) in the control memory 308.

In the same bus cycle in which the control memory address is latched, the VMC of # 0
The control circuit 503 of 401 controls the buffer 402 via a control line (not shown), and transmits / receives page state data to / from the data bus portion 406 of the control memory access bus 306.

As can be seen from the above operation, in the page state, the CPU bus 302 and the control memory access bus 306 can access the control memory 308 in the shortest one bus cycle as in the case of accessing the real page address data. . When the access extends over a plurality of bus cycles, the VMCs 401 of # 0 and # 1 can alternately access the control memory 308 every other bus cycle. Arbitration control of access conflict in the # 0 or # 1 VMC 401. For example, at the same time when the CPU 313 accesses the real memory 307, the network control circuit 310 causes the control memory 3 to operate.
When the real page address data in 08 is accessed, the control circuit 503 in the VMC 401 # 0 sets the local bus interface 501 to the real memory interface 5
06, and the network data bus interface 502 to the control memory interface 507, so that the CPU 313 accesses the real memory 307 and the network control circuit 310 controls the control memory 3.
08 accesses can be performed simultaneously.

Similarly, the CPU 313 accesses the control memory 308, the network control circuit 310 accesses the real memory 307, the processor bus interface 312 accesses the real memory 307, and the network control circuit 310 accesses the control memory 308 at the same time. Can be made.

On the other hand, in the # 0 VMC 401, between the CPU bus 302 and the network data transmission bus 305,
When an access conflict occurs for the real memory 307 at the same time, or an access conflict occurs for the real memory 307 between the external bus 301 and the network data receiving bus 304 in the VMC 401 of # 1. In this case, the control circuit 503 of FIG. 5 performs contention arbitration control according to a predetermined arbitration algorithm, and gives priority to the operation of either the local bus interface 501 or the network data bus interface 502 via the control line 504.

In the # 0 VMC 401, between the CPU bus 302 and the network data transmission bus 305,
When access conflicts occur simultaneously for the control memory 308, or in the # 1 VMC 401, the external bus 301
When the access memory 308 and the network data receiving bus 304 simultaneously contend for access to the control memory 308, the control circuit 503 controls the clock B as described above.
Based on 2 CLK, the operation of either the local bus interface 501 or the network data bus interface 502 is alternately prioritized via the control line 504. Specific Example of Real Memory Access Finally, a timing example when the CPU 313 acquires real memory data from the real memory 307 will be described with reference to the timing chart of FIG.

In FIG. 8, the shaded period is the range in which the change of the signal can fluctuate due to signal rounding or bus delay. The signals shown in FIGS. 6 (d), (i), and (j) are assumed to be active when they become low level.

Similar to FIG. 7A, FIG. 8A shows the system clock CLK (φ1, φ2), and FIG.
Similar to (b), clock BC generated based on CLK
LK, and each section sandwiched by "↑" indicates a bus cycle.

First, the address designated by the CPU 313 on the address bus of the CPU bus 302 is shown in FIG.
Confirm as shown in (c). Immediately after that, the address strobe signal AS- of the CPU bus 302 becomes active as shown in FIG. 8 (d), and after an appropriate delay time, the data strobe signal DS- of the CPU bus 302 becomes as shown in FIG. ), It becomes active.

In the nth bus cycle in which the address strobe signal AS- is active, the VMC4 whose address designated by the CPU bus 302 is # 0.
After being taken in by the local bus interface 501 in 01 (see FIG. 5), it is output to the address bus 407 from the real memory interface 506 in the VMC 401 # 0 in the same bus cycle as shown in FIG. 8 (e). To be done. Then, in the latter half period within the same bus cycle, the above-mentioned address on the address bus 407 is determined as shown in FIG. 8 (e).

In synchronism with this, the address selector 411 in the real memory 307 of FIG. 4 operates at the head timing of the bus cycle next to the bus cycle in which the address of the nth bus cycle is output to the address bus 407. Figure 8 (f)
As shown in (4), the address of the nth bus cycle on the address bus 407 is latched, and after an appropriate delay time, the latch content is fixed.

Then, in the same bus cycle as the bus cycle in which the above-mentioned address latch operation is performed,
As shown in (g), the real memory data corresponding to the address of the n-th bus cycle described above is output from the real memory 307 to the data bus 403, and its contents are determined in the latter half period of the bus cycle.

The control circuit 503 of the # 0 VMC 401 (see FIG. 5)
The control circuit 503 controls the real memory interface 506 via the control line 505 so that the real memory interface 506 is loaded with the real memory data on the data bus 403.
Controls the local bus interface 501 via the control line 504 and causes the real memory interface 506 to transfer the real memory data described above.

As a result, the local bus interface 5
01 is a data complete signal DS on the CPU bus 302 after an appropriate delay time, as shown in FIG. 8 (j).
-Is activated, and real memory data corresponding to the address of the nth bus cycle is output to the data bus on the CPU bus 302 after an appropriate delay time, as shown in FIG. 8 (h).

The CPU 313 corresponds to the address of the nth bus cycle output to the data bus on the CPU bus 302 after an appropriate delay time from the activation of the data complete signal DS- on the CPU bus 302. The actual strobe signal DS- is processed after the appropriate delay time as shown in FIG. 8 (i).
Back to inactive.

Here, as shown in FIGS. 8 (f) and 8 (g), the real memory 30 is specified by the address of the nth bus cycle.
In the bus cycle in which 7 is accessed, VMC4 of # 1 is placed on the address bus 408 as shown in FIG. 8 (e).
The address of the (n + 1) th bus cycle is output from 01, and in the next bus cycle, the address of the (n + 1) th bus cycle described above is used, as shown in FIG.
The real memory 307 is accessed as shown in (g).

In this way, the # 0 and # 1 VMCs 401 can alternately access the real memory 307 every other bus cycle.

[0154]

According to the present invention, a memory access circuit for switching between a plurality of master devices and a plurality of divided memories can be constituted by a plurality of memory control modules and a plurality of selecting means. Becomes

As a result, each memory control module can be easily configured with a gate array chip or the like, and each memory control module performs arbitration control of competition among a plurality of master devices, and each selection means uses each Since the interfaces facing the divided memories in the memory control module are simply sequentially selected, the entire memory access control can be easily realized.

Therefore, it is possible to realize the function of allowing any master device to access any memory device at high speed with a simple circuit configuration and simple control. Furthermore, it becomes possible to connect a plurality of master devices and a plurality of divided memories in an optimum form according to the system requirements.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a configuration diagram of a network to which an embodiment of the present invention is applied.

FIG. 3 is a configuration diagram of a message communication device according to an embodiment of the present invention.

FIG. 4 is a configuration diagram around a virtual memory controller.

FIG. 5 is a configuration diagram of a virtual memory control module.

FIG. 6 is an explanatory diagram of message communication.

FIG. 7 is a diagram showing an example (part 1) of a timing chart of actual memory access.

FIG. 8 is a diagram showing an example (No. 2) of a timing chart of actual memory access.

FIG. 9 is a configuration diagram of a conventional technique.

[Explanation of symbols]

 101 master device 102 divided memory 103 memory control module 104 selecting means BCLK operation clock MODE mode signal

Claims (1)

[Claims] 1. An arbitrary one of a first predetermined number (N × K) of master devices (101) to a second predetermined number (M).
Of the divided memory (102) for accessing any one of the divided memories (102), each of the first predetermined number (N × K) of master devices (10).
3) less than the first predetermined number (N × K) of 1)
A predetermined number (N) of interfaces to the master device (101) and an interface facing the second predetermined number of divided memories (102), and a predetermined operation clock (BCLK) and a predetermined mode signal. When a memory access request is issued from the plurality of master devices (101) to the same divided memory (102) at the same phase of the operation clock (BCLK), a predetermined operation is performed. A phase specified based on the mode signal (MODE) of the operation clock (BCLK) based on the memory access request from the master device (101) selected according to the priority order determined by the rule of Accessing the divided memory (102) corresponding to the memory access request, When memory access requests to different divided memories (102) are made from the plurality of master devices (101) in the same phase of the clock (BCLK), respective memories from the plurality of master devices (101). The different divided memories (102) corresponding to the respective memory access requests are simultaneously accessed in a phase specified based on the mode signal (MODE) of the operation clock (BCLK) based on an access request. A fourth predetermined number (K) of memory control modules (103) smaller than a predetermined number (N × K) of 1 and each of the divided memories (102) are provided, and the divided memory (102) and the The divided memory (102) in each of a predetermined number (K) of memory control modules (103) The memory control module and an interface, corresponding to the interface (1
03) includes the second predetermined number (M) of selection means (104) selectively connecting in the phase of the operation clock (BCLK) for accessing the divided memory (102). Memory access circuit.