JPH0619855A - Method and device for queueing message - Google Patents

Abstract

PURPOSE:To provide method/device for queueing a message, by which communication control at the time of using a message communication function is off- loaded on a message communication controller so as to simplify a procedure and the transfer of the message is ensured on the method/device for queueing the message on the message communication device controlling communication between multiprocessors. CONSTITUTION:When the message is transmitted from a processor in the multiprocessor, a message buffer 1 in the message communication device stores the received message, and queues the buffer for respective destinations for the message communication device which the message indicates. A table 2 stores lists which are enqueued in an arrival order for respective multiprocessor ID of the destinations. A ring buffer 3 stores destination addresses, namely, multiprocessor ID in the arrival order of the message. A transmission means 4 reads the destination address stored in the ring buffer at the time of receiving the messages from the processor, and transmits the message stored in the buffer which is enqueued by the table corresponding to the destination.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of computers are connected by a message communication device, and more particularly, to a message queuing method of a message communication device for controlling communication between multiprocessors and its device. .

[0002]

2. Description of the Related Art With the increase in speed of data communication devices, a so-called multiprocessor system has been developed in which a plurality of computers are grouped into one group and the groups are connected by a message communication device. Such computer systems are widely used in front & processors, fault tolerant systems, online transaction processors and the like.

In such a multiprocessor system, a so-called distributed system, it is desirable to realize performance proportional to the number of computers, and it is possible to extend the distance and increase the number of computers by the message communication device transmitting and processing the message at high speed. To do.

FIG. 12 is a block diagram of a multiprocessor system. The computers 101, 102, the computers 111, 112, and the computers 121, 122 are connected to the message communication devices 103, 113, 123 via local processor buses or the like.

The message communication devices 103, 113,
123 is connected to a network such as a token link, and is connected to each of the computers 101, 102, 11
1, 112, 121, 122 are the message communication devices 103, 113, 12 for the target computer.
Send data via 3. In the communication at this time, the message communication devices 103, 113, and 123 have a single queue for storing from which computer the message was sent, and the communication via the message communication device is performed using this queue.

When a message enters a communication device from one processor, it is stored in a buffer and connected to a transmission queue. Then, the message communication device transmits using a single queue for the transmission path. Then, the message communication device or computer corresponding to the purpose generates a queue for each destination, controls after arrival confirmation for each destination, and the message communication device that receives the message sends it to the target computer.

FIG. 13 is an explanatory diagram of conventional queuing. The message communication devices 103, 113, 123 first manage the first issued message by the buffer address, and secondly store the storage address of the next buffer in the header part of the message, and again store the next message in the header. Stores the start address of the buffer. Then, the position of the buffer is sequentially designated by this address and is queued.

[0008]

In the above-mentioned conventional apparatus, a computer manages each destination as shown in FIG. That is, the message communication device is a device for performing message communication, and only performs communication between the message communication devices, and a computer connected to the message communication device confirms communication for each computer. However, in the control for confirming the arrival for each computer, a complicated procedure is required when communication that requires the use of the message communication device is performed as compared with the case where the communication is unnecessary. For this reason, there is a problem that the target performance is not achieved due to this communication being limited, and the processing capacity proportional to the number of machines cannot be derived.

An object of the present invention is to provide a message queuing method and apparatus for offloading communication control when a message communication function is used to a message communication control device to simplify the procedure and to guarantee message transfer. .

[0010]

FIG. 1 is a block diagram showing the principle of the present invention. The present invention relates to a message communication device that couples a plurality of multiprocessors including a plurality of processors by message communication.

Message buffer 1 stores messages received from the processors in the multiprocessor. Table 2 stores a list in which the messages are queued for each destination and enqueued in order of arrival for each multiprocessor ID of the destination.

The ring buffer 3 stores the destination addresses in the order of arrival of the messages. This is a FIFO, for example. The sending means 4 reads the destination address stored in the ring buffer and sends the message stored in the buffer enqueued in the table corresponding to the destination.

[0013]

The basic principle of the present invention is as follows. In the first step, a message received from a processor in the multiprocessor is stored in a buffer, and a list structure is formed for each destination multiprocessor ID to be sent and queued. At the same time, in the second step, the received messages are sent to the multiprocessor I of the destination in the order of arrival.
Store in the ring buffer at the address corresponding to D. And
The destination stored in the second step is read, the buffer queued in the first step is searched, and the message is sent in the third step.

The operation of the device of the present invention is as follows. When a message is transmitted from the processor in the multiprocessor, the message buffer 1 in the message communication device stores the received message. Then, the buffer is queued for each destination to the message communication device indicated by the message, and the table 2 stores a list of enqueues in order of arrival for each multiprocessor ID of the destination. At the same time, the ring buffer 3 stores the destination address, that is, the multiprocessor ID in the order of arrival of the messages.

When the sending means 4 receives these messages from the processor, it first reads the destination address stored in the ring buffer 3 and stores it in the buffer enqueued in the table 2 corresponding to the destination. Send a message.

Prior to this transmission, the computer, that is, the processor does not need to manage the inside of the processor for each message communication device, that is, for each multiprocessor ID, and can collectively manage the communication device.

[0017]

The present invention will be described in detail below with reference to the drawings. <Queuing Method of the Present Invention> FIG. 2 is a diagram of a table for each destination provided in the message communication device. The number of messages, the head buffer address, and the last buffer address are stored in correspondence with the destinations T1 to Tn of the message to be sent to the message communication device.

In the communication from the message communication device to another computer via the other message communication device, the number of messages to be transmitted corresponds to the destination T1 of the target message communication device from the message communication device, that is, the multiprocessor. It is the number of messages received corresponding to the ID.

The head address of the buffer a in which the first received message is stored is stored in the list head buffer address of the destination T1. In the embodiment of the present invention, communication is managed by the multiprocessor ID and the processor ID. The destinations T1 to Tn here represent multiprocessor IDs. Then, the last buffer address of the list of the destination T1 is also set to the top address of the buffer a in which the message is stored. When the next message is sent from the computer and added to the message communication device before being sent subsequently, it is stored in the buffer a + 1 and the head address of the buffer is stored in the header of the buffer a. And the last buffer address is a +
Set to the beginning of 1. Further, when the message is received, it is stored in the buffer a + 2. The head address of this buffer a + 2 is stored in the header part of the buffer a + 1. Then, the destination T1 of the leading address of the buffer a + 2
Store in the last buffer address of the list. At this time, the number of messages is three.

By the above operation, a total of three messages are stored corresponding to the destination T1. On the other hand, at this time, similarly, the number of messages and the destinations are stored in the ring buffer in association with the received destinations in order in the ring buffer.

FIG. 3 is a block diagram of the ring buffer. The effective part start point and effective part end point of the ring buffer and the number of messages so far are stored in table X. Destinations are stored in the shaded areas in the figure, but are stored in the order input from the processor without depending on the destinations. For example, when messages are input from a computer in the order of destination T2, destination T3, destination T1, T2, T3, T are stored in the ring buffer.
Destinations to be transmitted are stored in the order of 1.

FIG. 4 is a relationship diagram between the destination table and the ring buffer. From the computer to the message communication device, messages for each T1, followed by messages for Tn, and then T
Suppose that you have entered a message addressed to 3. For example, the message addressed to T1 is addressed to the message communication device 113 in FIG.
The address of Tn is addressed to the message communication device 123. At this time, the ring buffer Z stores the destinations in the order of T1, Tn, and T1. Then, the number of messages addressed to T1 and the storage address buffers thereof are stored in the destination table W in the order of arrival. That is, the message is stored in the buffer for the message addressed to T1 and the message is stored in the buffer addressed to Tn. The message communication device uses this table and ring buffer Z.
First, read the destination to be sent, read the storage address of the message from the corresponding destination table,
Send the message to the network.

As described above, since the message communication device on the sending side manages the destination of the message communication device on the receiving side, the management by the computer connected to the message communication device is not necessary, and the message communication is required when necessary. Just send it to the device.

In the following, the invention will be described using a more detailed network system. <Second Embodiment of the Present Invention> FIG. 5 is a configuration diagram of a network according to an embodiment of the present invention.

A network 201 constructed around an optical fiber ring 206 has a plurality of nodes 202 (see FIG. 5).
Are indicated by numbers such as # 000, # ***, # %%%, etc.)
Are connected. This side is, for example, a token ring.

At node 202, processor bus 2
A plurality of processors 204 are connected to 05, and the processor bus 205 is accommodated in the message communication device 203, that is, the message communication control module. The message communication device 203 processes message data transmitted or received by the processor 204 via the processor bus 205, and also processes a frame in which message data input to or output from the optical fiber ring 206 is stored. The configuration of the bus in the message communication device 203 is most relevant to the present invention.

Next, FIG. 6 is a configuration diagram of the message communication device 203 in the node 202 of FIG. 5 in the embodiment of the present invention. The present invention is in the management of messages during this messaging.

The real memory 307 functions as a communication buffer for temporarily holding the message data and as a table for storing the address of the message communication device of the communicating party.

The control memory 308, for each virtual page address in the virtual storage space used for message communication, if that virtual page address is assigned to the real page address in the real memory 307, the real page address. The address and data indicating the page state (communication state) of the virtual page address are stored.

The processor bus interface 312 is
5 is connected to the external bus 301 while accommodating the processor bus 205 shown in FIG. 5, and message data or the like input from the processor 204 shown in FIG. 5 via the processor bus 205 is real memory via the external bus 301 and the virtual memory controller 309. 307 and vice versa, the message data and the like input from the real memory 307 via the virtual memory controller 309 and the external bus 301 are output to the processor 204 via the processor bus 205.

Further, the processor bus interface 31
2 exchanges communication control data with the CPU 313 via the external bus 301, the bus coupling unit 311, and the CPU bus 302. Normally, the bus coupling unit 311 does not connect the external bus 301 and the CPU bus 302, and the # 0 or # 1 processor bus interface 312 exchanges message data and the like with the real memory 307. The operation of accessing the external bus 301 and the operation of accessing the CPU bus 302 for the CPU 313 to access the real memory 307 or the control memory 308 can be performed independently and in parallel. As a result, the throughput of the entire message communication device 203 is improved.

Although not explicitly shown in FIG. 5, in FIG. 6, two processor buses 205 are provided for each node. Therefore, the processor bus interface 312 also
Two # 0 and # 1 are provided corresponding to each processor bus 205. Then, the # 0 processor bus interface 312 uses the control line 319 to perform contention control when the # 0 and # 1 processor bus interfaces 312 access the external bus 301. Further, the # 0 processor bus interface 312 is connected to the control lines 321 and 322.
Via a CPU bus arbiter 314 and I /
While exchanging control data regarding bus use with the O controller 315, competition control of the external bus 301 is performed, and opening / closing control of the bus coupling unit 311 is performed via the control line 320 when necessary.

The network control circuit 310 sends the frame from the CPU 313 to the CPU bus 302, I.
A control memory 308 via a control memory access bus 306 based on a transmission command input via the I / O controller 315 and the network command / result bus 303.
While accessing, read message data to be transmitted from the real memory 307 via the virtual memory controller 309 and the network data transmission bus 305, construct a transmission frame including the message data, and send it to the optical fiber ring 206. The transmission result is sent to the network command / result bus 303 and the I / O controller 31.
5 and the CPU 313 via the CPU bus 302. Communication management between these network communication devices will be described later.

Further, the network control circuit 310 receives the frame from the optical fiber ring 206, and the control memory 308 via the control memory access bus 306.
Access the received frame to another node 2
Relay to 02. Alternatively, the message data in the received frame is extracted and the network data reception bus 30
4 to the real memory 307 via the virtual memory controller 309, and the reception result is notified to the CPU 313 via the network command / result bus 303, the I / O controller 315, and the CPU bus 302.

The CPU 313 is connected to the CPU bus 302, and is connected to the CPU bus 302 at the start of operation.
It operates according to a control program written from the PROM 316 to the program RAM 317 connected to the CPU bus 302.

The CPU 313 has a CPU bus 302,
Communication control data is exchanged with the processor bus interface 312 via the bus coupling unit 311 and the external bus 301.

Further, the CPU 313, when transmitting a frame, uses the CPU bus 302, the I / O controller 315,
And output a send command to the network control circuit 310 via the network command / result bus 303, and thereafter
From the network control circuit 310, a network command /
Result bus 303, I / O controller 315, and CP
The transmission result notification is received via the U bus 302. Conversely, the CPU 313 receives from the network control circuit 310 the network command / result bus 303, the I / O controller 315, and the CPU bus 3 when receiving a frame.
A reception result notification is received via 02.

Further, the CPU 313 has a CPU bus 302.
The page state data (data indicating the communication state) of each virtual page address in the control memory 308 is accessed via the CPU memory 302 and the virtual page address of each virtual page address in the control memory 308 is accessed via the CPU bus 302 and the virtual memory controller 309. The page address data and the real memory 307 are accessed.

The I / O controller 315 is connected to the CPU bus 302 and accommodates a peripheral device bus 318 to which external peripheral devices are connected. In addition, I / O controller 3
As described above, the relay unit 15 relays the transmission command, the transmission result notification, or the reception result notification exchanged between the CPU 313 and the network control circuit 310 via the CPU bus 302 and the network command / result bus 303.

Further, the I / O controller 315 is a CP
The address that U313 uses to access the external bus 301 is C
When specified for the PU bus 302, the control line 322
To the processor bus interface 312 of # 0 via
Outputs an external bus access request.

The CPU bus arbiter 314 is a C bus from the processor bus interface 312 via the control line 321.
When the PU bus access request (bus grant request) is received, the bus use request (bus grant request) is output to the CPU 313 via the control line 323, and the CPU 3
13 receives a bus use permission (bus grant acknowledge) from the control line 323 through the control line 323, and based on that, the CPU
Bus access permission (bus grant acknowledge) is sent via the control line 321 to the # 0 processor bus interface 3
Return to 12.

The virtual memory controller 309 is
Processor bus interface 312 and real memory 307
Data exchanged with the external bus 301 via the external bus 301, C
Data transmitted and received between the PU 313 and the real memory 307 or the control memory 308 via the CPU bus 302, and between the network control circuit 310 and the real memory 307 via the network data reception bus 304 or the network data transmission bus 305. The switching control and the contention control of the exchanged data are performed.

The operation of the embodiment of the present invention having the above configuration will be described. <Overall operation of inter-processor communication> Now, referring to FIGS. 5 and 6, for example, message data is sent from one processor 204 in the node 202 of # 000 to another processor 204 in the node 202 of # ***. The overall operation when transmitting will be described.

In this case, the message data transmitted from one processor 204 in the node # 000 is the message communication device 203 in the node (hereinafter, the message communication device 203 in # 000) via the processor bus 205. Call)) to the real memory 307,
It is sent to the real memory 307 of the message communication device 203 in the node 202 of # *** (hereinafter referred to as the message communication device 203 of # ***), and then the destination from the real memory 307 via the processor bus 205. The processor 204
Transferred to. That is, the real memory 307 of each message communication device 203 functions as a communication buffer. <Communication method between message communication apparatuses 203> Here, a special method called a network virtual storage method is applied to communication of message data between the message communication apparatuses 203.

First, in the entire network 201 of FIG.
A virtual memory space is defined. This virtual storage space is divided into a plurality of virtual pages, and message data is communicated via these virtual pages. For example, the virtual storage space is divided into virtual page addresses of 0000 to FFFF pages (hexadecimal number). One virtual page has a fixed length (for example, 8 kilobyte length) data length that can sufficiently accommodate a packet that is one unit of message data. Unless otherwise specified, the virtual page address and the dictated real page address are represented by hexadecimal numbers.

Next, the message communication device 203 of each node 202 connected to the network 201 is allocated every predetermined number of pages of the virtual storage space, for example, every 16 pages. For example, the message communication device 203 of the # 000th node 202 is allocated to the 0000 to 000F page, the message communication device 203 of the # 001th node 202 is allocated to the 0010 to 001F page, and so on. ** 0-*** F page and %%% 0-%%% F page (3 digit *
And% are arbitrary numbers in hexadecimal numbers 0 to F), the message communication device 203 of each node 202 of the # *** th and # %%% th is assigned.

Therefore, in the above example, the network 20
1, a maximum of 3096 message communication devices 203 from # 000 to #FFF can be connected. On the other hand, the real memory 307 in each message communication device 203 is divided into a plurality of real pages each having the same data length as the above-mentioned virtual page. The page capacity of the real memory 307 may be much smaller than the page capacity of the virtual storage space, and may be, for example, about 64 to 256 pages.

Next, in the control memory 308 of each message communication device 203, as shown in FIG. 7, control data for all virtual page addresses are stored. As shown in FIG. 7, the control data of each virtual page address indicates the real page address data of the real memory 307 in the own message communication device 203 associated with the virtual page address and the communication state of the virtual page address. And page status data shown.

Then, as an initial state, each node 202
In the control memory 308 of the message communication device 203 in the internal message communication device 203, the virtual page address assigned to the node 202 is set to an arbitrary empty page in the real memory 307 of the own message communication device 203 by the network reception control function of the CPU 313. The real page address of the network receiving buffer provided in the above and the receiving buffer allocation state VP as the page state are respectively written in advance. The network reception control function is a CP
This is realized by the U313 executing the control program stored in the program RAM 317.

For example, # 000 message communication device 203
In the control memory 308 of the own message communication device 2
As shown in FIG. 7, each virtual page address of 0000,0001, ..., 000F pages allocated to the 03 is assigned to each real page of s, q, ..., p in the real memory 307. The address has been written and the page status VP indicating the receive buffer allocation status has been written.

Also, in the control memory 308 of the message communication device 203 of # ***, the own message communication device 20
As shown in FIG. 7, each virtual page address of **** 0, *** 1, ..., *** F page assigned to
The page status indicating the receive buffer allocation status in which each real page address of v, u, ..., T in the real memory 307 is written.
VP is written.

Similarly, the message communication device 203 of # %%%
In the control memory 308 of the own message communication device 2
As shown in FIG. 7, the virtual page addresses of the %%% 0, %%% 1, ..., %%% F pages allocated to the 03 are y, w, and y in the real memory 307. , X are written, and the page state VP indicating the receive buffer allocation state is written.

Now, by the transfer operation described later, for example, # 000
Message data is transferred from one processor 204 in the node # 000 202 to a network transmission buffer (to be described later) whose real page address is r in the real memory 307 of the message communication device 203 of FIG. To do.

The network transmission control function of the CPU 313 analyzes the destination address part in the header of the message data stored in the network transmission buffer in the real memory 307 via the CPU bus 302 and the virtual memory controller 309. By doing so, the virtual page address assigned to the node 202 in which the processor 204 corresponding to the destination address is accommodated is determined as the one whose page state is the buffer unallocated state NA. In the example of FIG. 7, for example, the virtual page address *** 2 is determined. The network transmission control function is realized by the CPU 313 executing the control program stored in the program RAM 317.

Next, the network transmission control function of the CPU 313 writes the real page address of the network transmission buffer in which the above-mentioned message data is stored in the determined virtual page address in the control memory 308, and the page Change the status from the buffer unallocated status NA to the transmission status SD. In the example of FIG. 7, the real page address r and the transmission state SD are set to the virtual page address *** 2, for example.

The network transmission control function of the CPU 313 is the transmission F function in the I / O controller 315.
The virtual page address and the transfer length of the message data described above are written to the IFO via the CPU bus 302 together with the transmission command.

When the network control circuit 310 reads the above-mentioned transmission command or the like from the transmission FIFO in the I / O controller 315 via the network command / result bus 303, the virtual page added to the transmission command. An address is designated to the control memory 308 via the control memory access bus 306, the real page address set in the above-mentioned virtual page address is read from the control memory 308, and set in the DMA transfer register in the virtual memory controller 309. To do.

Then, the network control circuit 310 is
The page data of the real page address in the real memory 307 including the message data to be transmitted to the virtual memory controller 309 is transferred to the network control circuit 310 via the network data transmission bus 305.
To DMA transfer.

The network control circuit 310 extracts message data corresponding to the transfer length of the message data added to the send command from the above page data, and the virtual page address added to the message data and the send command. And a transmission frame including the transfer length of the message data and generating the transmission frame.
Send to 6. The token ring network method is adopted as the frame transmission method of the optical fiber ring 206, and the network control circuit 310 can send a transmission frame only when a free token circulating on the optical fiber ring 206 is acquired. .

In the example of FIG. 7, a transmission frame including the virtual page address *** 2 and the message data stored in the real page address r in the real memory 307 from the message communication device 203 of # 000 is transmitted. It is sent to the optical fiber ring 206.

The above-mentioned transmission frame is transmitted to another node 202 (see FIG. 5) connected to the optical fiber ring 206.
Are sequentially transferred to. When the network control circuit 310 of the message communication device 203 in each node 202 fetches the transmission frame from the optical fiber ring 206, the page state corresponding to the virtual page address stored in the transmission frame is set to the control memory access bus 306. Read from the control memory 308 via the, and whether the page status is the receive buffer allocation status VP, that is, whether the virtual page address is assigned to the message communication device 203 of the own node 202, or the page It is determined whether or not the state is the transmission state SD, that is, whether or not the transmission frame is transmitted by the own network control circuit 310.

When the network control circuit 310 determines that the page state of the virtual page address stored in the transmission frame is the reception buffer allocation state VP,
The message data stored in the transmission frame is taken into the real memory 307 as follows.

That is, the network control circuit 310 first designates the virtual page address stored in the transmission frame to the control memory 308 via the control memory access bus 306, and the control memory 308 sets the virtual page address to the above virtual page address. The set real page address is read out and set in the DMA transfer register in the virtual memory controller 309. Then, the network control circuit 310 causes the virtual memory controller 309 to
The message data included in the transmission frame is DMA-transferred to the above-mentioned real page address in the real memory 307 via the network data reception bus 304.

After that, the network control circuit 310
The virtual page address stored in the transmission frame is
Control memory 30 via control memory access bus 306
8 is specified, and the page status of the virtual page address is changed from the reception buffer allocation status VP to the reception completion status RD.

Further, the network control circuit 310 is
The virtual page address extracted from the transmission frame and the transfer length of the message data are written into the reception FIFO in the / O controller 315 via the network command / result bus 303 together with the result code indicating the success or failure of the reception.

Finally, the network control circuit 310
After writing the reception success notification in the response area in the above-mentioned transmission frame received from the optical fiber ring 206, the transmission frame is sent to the optical fiber ring 206 again.

For example, in the example of FIG. 7, the network control circuit 310 of the message communication device 203 of # *** is # 000.
The message stored in the transmission frame is determined by determining that the page state on the control memory 308 of the virtual page address *** 2 stored in the transmission frame from the node 202 is the reception buffer allocation state VP. The data is transferred to the real memory 30 having the real page address u set to the virtual page address *** 2 of the control memory 308.
After fetching in the network reception buffer in 7, the page state of the virtual page address *** 2 of the control memory 308 is changed from the reception buffer allocation state VP to the reception completion state RD.

The above-mentioned reception result notification is received by the CPU 313 via the CPU bus 302. That is, CP
The U313 network reception control function uses the reception F in the I / O controller 315 via the CPU bus 302.
When the above reception result notification is received from the IFO and if the result code is successful in reception, the virtual page address which is a part of the reception result notification is designated to the control memory 308 via the CPU bus 302, and the page state Read the real page address.

If the above-mentioned page state is the reception completion state RD, the network reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to make the above-mentioned real state. Separates the real page specified by the page address from the network receive buffer and connects it to the processor send-wait buffer queue.

Thereafter, the network reception control function of the CPU 313 controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to connect an arbitrary empty page to the network reception buffer, and further Control memory 3 via CPU bus 302 with a virtual page address that is part of the reception result notification
08 is accessed, and the real page address of the above-mentioned empty page and the reception buffer allocation state VP as the page state are written to the virtual page address.

Thereafter, the processing for the processor transmission waiting buffer queue in the real memory 307 is performed by the CPU 31.
3 from the network reception control function to the processor transmission control function described later.

On the other hand, the network control circuit 310 reads the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, and as a result, the page state is neither the reception buffer allocation state VP nor the transmission state SD. If it is determined that the transmission frame is transmitted, the transmission frame is directly transmitted to the optical fiber ring 206.

For example, in the example of FIG. 7, the network control circuit 310 of the # %%% message communication device 203 is
By determining that the page state on the control memory 308 of the virtual page address *** 2 stored in the transmission frame from the node 202 of the node 202 is neither the reception buffer allocation state VP nor the transmission state SD, the transmission frame is left as it is. It is sent to the optical fiber ring 206.

Optical fiber ring 206 as described above
The transmission frame sequentially transferred above returns to the network control circuit 310 of the message communication device 203 in the node 202 which is the transmission source.

The network control circuit 310 of the transmission source
As a result of reading out the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, by determining that it is the transmission state SD,
It is determined that the transmission frame is the transmission frame transmitted by the own network control circuit 310.

In this case, the network control circuit 310
After confirming that the reception success notification is written in the response area of the received transmission frame, the control memory 308 of the control memory 308 corresponding to the virtual page address stored in the transmission frame is transmitted via the control memory access bus 306. The page state is changed from the transmission state SD to the transmission completion state SC.

Then, the network control circuit 310
The virtual page address extracted from the transmission frame is written to the reception FIFO in the I / O controller 315 via the network command / result bus 303 together with the result code indicating the success or failure of the transmission.

The above-mentioned transmission result notification is received by the CPU 313 via the CPU bus 302. That is, CP
The network transmission control function of the U313 is performed by the reception F in the I / O controller 315 via the CPU bus 302.
When the above result notification is received from the IFO, if the result code is successful, the virtual page address that is a part of the result notification is specified in the control memory 308 via the CPU bus 302, and the page status is changed. Read the real page address.

If the above-mentioned page state is the transmission completion state SC, the network transmission control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to make the above-mentioned real state. The real page specified by the page address is separated from the network send buffer and used as a free page.

After that, the network transmission control function of the CPU 313 controls the control memory 3 via the CPU bus 302 with the virtual page address which is a part of the above-mentioned transmission result notification.
08 is accessed, and the buffer unallocated state NA is written as the page state of the virtual page address.

As described above, the network 201 (see FIG.
In the above, one virtual storage space is defined, and a virtual page having a fixed data length that constitutes this space is assigned to each message communication device 203. Communication of message data between the message communication devices 203 is performed using this virtual page. As a result, blocking control and sequence control that are performed in normal packet communication are not required.

When the network control circuit 310 of the message communication device 203 in each node 202 on the optical fiber ring 206 receives a transmission frame, the network control circuit 310 in the control memory 308 uses the virtual page address stored in the transmission frame. By accessing the page state, the received transmission frame can be processed at high speed.

In addition, a response area is provided in the transmission frame transferred on the optical fiber ring 206, and the network control circuit 310 of the message communication device 203 in the node 202 on the reception side transmits the reception result of the transmission frame. It writes in the response area of the frame and sends it out again to the optical fiber ring 206. Therefore, by the time this transmission frame is transferred on the optical fiber ring 206 and returned to the transmission source, the message data transmission processing is completed, and the response from the reception side to the transmission source is sent using another frame. No need to notify. As a result, the communication protocol can be simplified and high-speed response processing can be performed.

Further, the communication of the message data between the message communication devices 203 is performed using the real memory 307 while the network control circuit 310 in the message communication device 203 accesses the control memory 308, and the communication with the processor 204 and the message communication device 203 is performed. The communication of message data between 203 is performed by the message communication device 2 as described later.
The processor bus interface 312 in 03 uses the real memory 307 independently of the operation of the network control circuit 310 described above. Further, the correspondence between the message data stored in the real page address in the real memory 307 and the virtual page address in the virtual storage space is as described below, in which the CPU 313 sends the destination address in the header added to the message data. Based on. Therefore, between the processor 204 and the message communication device 203,
Message communication device 203 and message communication device 203
It is possible to efficiently perform the processing between them at high speed. <Transfer Operation of Message Data from Processor 204 to Message Communication Device 203 at Source> Next, the source node 202 (in the example of FIG. 7, the node # 000 20)
The operation when the message data is transferred from one processor 204 in 2) to the real memory 307 of the message communication device 203 in the node will be described.

First, the processor reception control function of the CPU 313 accesses the real memory 307 through the CPU bus 302 and the virtual memory controller 309 to connect the processor reception buffer queue to the free buffer queue in the real memory 307. Connect the free buffer that is being used. The processor reception control function is a function realized by the CPU 313 executing the control program stored in the program RAM 317.

The processor reception control function of the CPU 313 activates, for example, the # 0 processor bus interface 312 via the CPU bus 302, the bus coupling unit 311, and the external bus 301, while The start address of the above-mentioned processor receive buffer queue is notified.

The processor bus interface 312 is
The message data transferred from the processor 204 via the processor bus 205 is received, and the received message data described above is updated while sequentially updating the buffer address with the start address as the reception start address.
External bus 301 and virtual memory controller 30
9 is sequentially transferred to an empty buffer connected to the processor reception buffer queue in the real memory 307.

The processor bus interface 312 is
When there is no free buffer connected to the processor receive buffer queue, or when a small amount of data has been stored and a specific time has elapsed, reception is automatically stopped, to that effect, the external bus 301, the bus coupling unit 311, and the CPU bus. 302
To the CPU 313 via.

The processor reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to separate the above-mentioned received buffer from the processor reception buffer queue and transmit it to the network. Connect to a buffer. The connection of this buffer is the connection in the embodiment of the present invention, in which the number # *** of the destination message communication device is read from the ring buffer in the order received from the processor,
From that number # ***, the corresponding enqueued buffer is connected to the send buffer. Thereafter, the processing for the network transmission buffer in the real memory 307 is transferred from the processor reception control function of the CPU 313 to the network transmission control function described above, and the transmission source of the transmission source is transmitted in accordance with the communication method between the message communication devices 203 described above. The message communication device 203 of the node 202 (see FIG. 7)
Of the message communication device 203 of # 000), the message communication device 203 of the node 202 in which the destination processor 204 is accommodated (the message communication device 203 of # *** in the example of FIG. 7) Real memory 30
The message data transfer operation to 7 is executed. <Operation of Transferring Message Data from Message Communication Device 203 to Processor 204 on Receiving Side> Next, the receiving side node 202 (in the example of FIG. 7, the node 20 of # ***)
The operation when the message data is transferred from the real memory 307 of the message communication device 203 in 2) to one processor 204 in the node 202 will be described.

When the network control circuit 310 succeeds in receiving the transmission frame, the CPU 313 as described above.
The network reception control function of (1) connects the received message data to the processor transmission waiting buffer queue in the real memory 307.

On the other hand, the processor transmission control function of the CPU 313 includes a CPU bus 302 and a bus coupling unit 31.
For example, the # 0 processor bus interface 312 is activated via 1 and the external bus 301, and the interface 312 is notified of the start address of the above-mentioned processor transmission waiting buffer queue.

The processor bus interface 312 is
While sequentially updating the buffer address with the start address as the transmission start address, the real memory 30 is accessed via the external bus 301 and the virtual memory controller 309.
7 sequentially reads the message data stored in the buffer connected to the processor transmission waiting buffer queue, analyzes the destination address part in the header of the message data, and transfers the message data to the processor bus 205. Via the destination processor 204. As will be described later in detail, the buffer is connected to the queue for each processor instead of being managed by one queue even when receiving. <Priority of Communication between Message Communication Devices> In the system of the present invention, communication is managed by the processor ID and the multiprocessor ID. Processor ID
Is the number of the processor in the multi-communication device, and the multiprocessor ID is the number of the communication device.

FIG. 8 is a destination-specific table chart having priorities. Address of each node of the message communication device 203 in FIG. 5, that is, multiprocessor IDCMP
Corresponding to # 0 to CMP # 1024, each table W is CM
The high level message (the number of HMSG) to be sent to P # 0, the head buffer address for each CMP # 0, the final buffer address, the number of the low level messages (the number of LMSG) to be sent to CMP # 0 next, and the head of each Buffer address, last buffer address, and C
The number of DATA (DATA) to be transmitted to MP # 0, and the corresponding start address and end buffer address are stored. In addition, this multiprocessor IDCMP
In addition to # 0, up to multi-processor IDCMP # 1024 in 3 levels as above, namely HMSG, LMS
The number of buffers corresponding to G and DATA, the head buffer address, and the last buffer address are stored.

FIG. 8 shows the destination table W shown in the first embodiment, which has three levels (HNS) for each node #n.
G, LMSG, DATA). FIG. 9 is a block diagram of a ring buffer having priorities. This ring buffer comprises a register X3 corresponding to a total of three types of HMSG, LMSG, and DATA, and ring buffers Z1 to Z3 for storing each destination.

Each of the ring buffers Z1 to Z3 is H
There are n + 1 buffers for storing each CMP-ID for MSG, LMSG, and DATA, that is, the destination. And
The number of connected buffers corresponding to each of them, the element number to be processed next, and the element number of the array last stored so far are set in register X3 corresponding to HMSG, LMSG, and DATA.
-11 to X3-33.

Number X3-11 for the HMSG connected to the queue, element number X3 of the HMSG array to be processed next
-12, element number X3-13 of the last processed sequence is for the first level (HMSG). Further, the number of LSGs connected to the queue X3-21, the CMP-I to be processed next
Element number X-22 of D array, last processed CMP-I
Element number X-23 of the D array is at the second level (LMSG)
, Then DATA number X-31, then CMP to be processed
-ID array element number X3-32, the last processed CM
The element number S-33 of the P-ID array is the third level (DA
It is a table for TA).

Correspondingly, HMSG,
Weighting is provided to the LMSG and the ring buffers Z1 to Z3 for data, and the HMSG is the highest level, and when transmitting, the HMS connected at this level is connected.
CMP-ID to determine the number of G and process next when it is other than 0
The element number is obtained from the element number X-12 of the array, and the destination address corresponding to the array element number is obtained. And
From this destination, the head buffer of each destination shown in FIG. 8 is obtained and transmitted. This is not limited to HMSG but LMS
The same applies to G and DATA. That is, HMS
LMSG number is detected when G number is 0, LMS is detected when it is not 0
Transmission corresponding to G is performed, and when 0, transmission corresponding to DATA is performed.

In the embodiment of the present invention, data is transferred in the VMS structure as described above. Each node, that is, (CMP) has a VMS structure as shown in FIG. 10, and directly maps and transfers a buffer in the shared virtual memory space. The tables shown in FIGS. 8 and 9 described above are stored in the real memory 307. Then, as shown in FIG. 10, the correspondence between the buffer and the virtual memory is stored in the control memory 308 for direct mapping to the shared virtual memory space in communication. Each time one buffer is sent out, the CPU 313 is provided with the FI provided in the I / O controller.
The next transfer instruction is added to FO to change the corresponding address in the virtual space of the control memory 308.

By the above operation, data is transferred to the target multiprocessor address, so-called message communication device in the node 202. When the message communication device receives these data, the message communication device similarly queues corresponding to the processor IDs of the processors in the node, and if it has processors 0 to m, for example, as shown in FIG. , The number of messages, the list head buffer address and the list end buffer address are provided and managed correspondingly. This communication is performed by the communication between the message communication device and the processor described above. Incidentally, if the number of elements of the ring buffer is equal to or larger than the number of buffers for storing the message, there will be no problem in communication.

To summarize the operations described above, when a message is first received from the processor, the destination is analyzed and enqueued, and the destination is entered in the ring buffer. The send routine reads the destination from the ring buffer and sends the first buffer in the list corresponding to that destination. When this sending process ends normally, the corresponding buffer is released, and when it cannot be sent normally, it is retried immediately or the list is left as it is and the message is sent to the ring buffer to set the sending order of messages. The number of reserved and queuing messages in the ring buffer is equal to the number enqueued in the list, and no retrieval is required, which enables fast and reliable message transmission.

[0101]

As described above, even if a message cannot be normally transferred to a destination by managing the queue for each destination and entering the destination in the ring buffer,
Message transfer can be assured only by performing exactly the same transmission processing, and since complicated processing such as queue rearrangement is not necessary compared to control with a single queue, communication control can be speeded up, reliable and high speed communication It can be performed.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a table diagram for each address of the message communication device.

FIG. 3 is a configuration diagram of a ring buffer.

FIG. 4 is a relationship diagram between a destination table and a ring buffer.

FIG. 5 is a configuration diagram of a network according to a second embodiment of this invention.

FIG. 6 is a configuration diagram of a message communication device according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram of message communication.

FIG. 8 is a table chart by destination having priorities.

FIG. 9 is a configuration diagram of a ring buffer having priorities.

FIG. 10 is a relationship diagram of VMS and buffer.

FIG. 11 is an explanatory diagram of a reception side queue in the message communication device.

FIG. 12 is a configuration diagram of a multiprocessor system.

FIG. 13 is an explanatory diagram of conventional queuing.

FIG. 14 is an explanatory diagram of conventional message transmission.

[Explanation of symbols]

 1 message buffer 2 table 3 ring buffer 4 sending means

Claims (5)

[Claims] 1. A message communication system in which a plurality of multiprocessors including a plurality of processors are coupled by message communication, wherein a message received from the processor in the multiprocessor is stored in a buffer, and each multiprocessor ID to be sent out. The first to structure and queue the list
And a second step of storing the received messages in a ring buffer in the order of arrival at destination addresses, and reading the destination stored in the second step and reading the buffer queued in the first step. And a message queuing method comprising the step of sending a message. 2. A message communication device for coupling a plurality of multiprocessors, each of which is composed of a plurality of processors, by message communication, and a message buffer (1) for storing a message received from the processor in the multiprocessor, and the message destination. A table (2) for storing a list of queues for each destination and enqueued for each destination multiprocessor ID in the order of arrival; a ring buffer (3) for storing destination addresses in the order of arrival of the messages; and a ring buffer (3) stored in the ring buffer. A message queuing device, comprising: a sending means (4) for reading a destination address, and sending a message stored in a buffer enqueued in a table corresponding to the destination. 3. The message queuing apparatus according to claim 2, wherein the message has a plurality of transmission priorities, and a plurality of the tables and ring buffers are provided corresponding to the priorities. 4. The message queuing device according to claim 2, wherein the number of elements of the ring buffer is equal to or larger than the number of buffers for storing the message. 5. The message queuing device according to claim 2, wherein the ring buffer is a FIFO.