JPH064462A - Bus coupling system - Google Patents

Abstract

PURPOSE:To improve the throughput of the system by connecting plural bus masters to plural buses so that an access between each bus can be executed, with regard to the bus coupling system for coupling plural buses. CONSTITUTION:In the case where a first bus master means 104 designates an address for accessing a second bus 102 to a first bus 101, an inter-bus access control means 109 outputs a second bus access request 107 to a second bus master means 108. A second bus master means 108 executes arbitration of a competition between a first bus 101 and a second bus 102, and controls a switch means 103. In the case a second bus master means 108 designates an address for accessing a first bus to a second bus 102, a first bus access request 105 is executed to a first bus master means 104, and after waiting for a bus opening notice 106 therefrom, a second bus 102 is accessed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus coupling system for coupling a plurality of buses.

[0002]

2. Description of the Related Art In a computer system, a bus consisting of an address line, a data line and a control line is used to connect a processor, a memory, an input / output device or the like.

If many devices are connected to the bus, especially a bus master device (hereinafter simply referred to as a bus master) that actively accesses the bus, such as a processor, the bus masters compete for access to the bus. However, there is a problem in that the throughput of the entire system cannot be improved beyond the processing capacity of the bus because the probability of communication becomes higher.

For example, two bus masters and two slave devices such as memories are connected to the bus, and the above-mentioned 2
It is assumed that one bus master may access the above two slave devices. In this case, while the first bus master is accessing the bus, the second bus master cannot access the bus and needs to wait for the completion of the execution of the bus cycle of the first bus master. Also, the first bus master accesses the first slave device,
Even when the bus master of the above accesses the second slave device, the right to execute the bus cycle is given to only one bus master at the same time. Therefore, the bus master not given the right must wait for the execution of the bus cycle. I have to.

In the conventional computer system, the bus master is often one processor, and the above-mentioned problem is not serious, but it is an important problem in a multiprocessor system in which a plurality of processors are connected by a bus.

Further, the number of bus masters other than processors is increasing due to the intelligentization of disk controllers and network controllers, and the same problem as described above occurs when connecting them to the bus.

According to the present invention, by connecting a plurality of bus masters to a plurality of buses and enabling access between the buses,
The purpose is to improve the throughput of the system.

[0008]

The first aspect of the present invention has the following configuration. First, it has a switch means for selectively connecting a plurality of buses.

Next, there is an in-bus access control means that is provided for each bus and that performs closed bus access control within its own bus. Further, it has a bus access request output means which is provided corresponding to each bus and outputs a bus access request of the other bus to a bus other than the own bus.

Further, there is provided inter-bus access control means which is provided corresponding to each bus and which controls the bus access of its own bus in response to a bus access request of its own bus from a bus access request output means other than the own bus. .

Further, there is provided switch control means for connecting the buses related to the bus access to the switch means when the bus access is made over two or more of the above-mentioned buses. The second aspect of the present invention has the following configuration.

FIG. 1 is a block diagram of the second aspect of the present invention. First, the switch means 103 selectively connects the first and second buses 101 and 102.

Next, the first bus master means 104 is connected to the first bus 101. And the first bus 10
It has a function of accessing the first bus 101 when 1 is not released. Further, when the first bus 101 is not accessed, the first bus access request 10 from the outside is sent.
5 has the function of opening the first bus 101 and outputting the first bus release notification 106 to the outside. Further, it has a function of securing the first bus 101 when the access to the first bus 101 from the outside is completed.

Then, the second bus master means 108
It is connected to the second bus 102. First, it has a function of accessing the second bus 102 when the second bus 102 is not open. Next, it has a function of releasing the second bus 102 in response to a second bus access request 107 from the outside when the second bus 102 is not being accessed. Further, it has a function of securing the second bus 102 when the access to the second bus 102 from the outside is completed. Further, it has a function of connecting the first bus 101 and the second bus 102 to the switch means 103 when the second bus 102 is opened. In addition, when the access to the second bus 102 by the first bus master means 104 is completed, the switch means 103 is provided with the first bus 101 and the second bus 102.
Has a function of disconnecting the bus 102. Furthermore, the first
Address for accessing the bus 101 of the second bus 10
2 when the second bus access request 107 from the outside is not input, the first bus access request 105 is sent to the first bus master unit 1
04 has the function of outputting. After that, after waiting for the first bus release notification 106 from the first bus master means 104, the first bus 101 and the second bus 1 are sent to the switch means 103.
02 has the function of connecting. Then the first bus 1
It has a function of designating an address for accessing 01 to the second bus 102. Then, it has a function of causing the switch means 103 to disconnect the first bus 101 and the second bus 102 when the access is completed.

Further, the inter-bus access control means 109 is
First bus master means 1 connected to the first bus 101
04 assigns the first address to access the second bus 102
It has a function of outputting the second bus access request 107 to the second bus master means 108 when the bus 101 is designated.

In the second aspect of the present invention described above, the second
Bus master means 108 to first bus master means 10
The first bus access request 105 to the fourth bus 4 and the first bus release notification 106 from the first bus master means 104 to the second bus master means 108, which is a response thereto, are transmitted via the inter-bus access control means 109. It may be configured to be notified.

The third aspect of the present invention has the following configuration. FIG. 2 is a block diagram of the third aspect of the present invention. First, the switch means 203 selectively connects the first and second buses 201 and 202.

The first bus master means 208 is connected to the first bus 201. And first, the first bus 20
It has a function of accessing the first bus 201 when 1 is not released. Next, the first bus access request 20 from the outside when the first bus 201 is not accessed
4 has a function of releasing the first bus 201 and outputting a first bus release notification 205 to the outside. Also, when the access to the first bus 201 from the outside is completed, the first
It has a function of securing the bus 201. Subsequently, it has a function of stopping access to the second bus 202 via the first bus 201 in response to an external second bus access stop signal 206. Furthermore, after the cancellation, the first bus 201
Has a function of releasing the first bus release notification 205 to the outside. After the suspension, it has a function of restarting access to the second bus 202 via the suspended first bus 201 in response to a second bus access retry signal 207 from the outside.

The second bus master means 213 is connected to the second bus 202. And first, the second bus 20
It has a function of accessing the second bus 202 when the 2 is not released. Next, the second bus access request 20 from the outside when the second bus 202 is not accessed
9 has a function of releasing the second bus 202 and outputting a second bus release notification 210 to the outside. In addition, when the external access to the second bus 202 is completed, the second
Has a function of securing the bus 202. Subsequently, it has a function of stopping access to the first bus 201 via the second bus 202 in response to a first bus access stop signal 211 from the outside. Furthermore, after the cancellation, the second bus 202
To release the second bus release notification 210 to the outside. After the suspension, it has a function of restarting access to the first bus 201 via the suspended second bus 202 in response to an external first bus access retry signal 212.

The first inter-bus access control means 215 is
The first bus master unit 208 has a function of outputting a second bus access request 209 to the second bus master unit 213 when the first bus 201 specifies an address for accessing the second bus 202. Next, in response to the second bus access request cancellation signal 214 from the outside, the first
Second bus access stop signal 206 to the second bus access means 209 and second bus access request 209.
With the function of withdrawing. Also, in response to the first bus release notification 205 from the first bus master unit 208, the switch unit 203 is provided with the first bus 201 and the second bus 202.
Has the function of connecting. Further, when the access to the first bus 201 by the second bus master unit 213 is completed, the switch unit 203 is provided with the first bus 201 and the second bus 201.
It has a function of disconnecting the bus 202. A second bus access retry signal 207 is output to the first bus master unit 208 when the access to the first bus 201 by the second bus master unit 213 is completed after the output of the second bus access stop signal 206. Have the function to

The second inter-bus access control means 217 is
It has a function of outputting the first bus access request 204 to the first bus master unit 208 when the second bus master unit 213 specifies an address for accessing the first bus 201 for the second bus 202. Then, in response to the first bus access request withdrawal signal 216 from the outside, the second
Of the first bus access stop signal 211 to the first bus access request 204
With the function of withdrawing. Further, in response to the second bus release notification 210 from the second bus master unit 213, the switch unit 203 is provided with the first bus 201 and the second bus 202.
Has the function of connecting. Further, when the access to the second bus 202 by the first bus master unit 208 is completed, the switch unit 203 is provided with the first bus 201 and the second bus 202.
It has a function of disconnecting the bus 202. Then, when the access to the second bus 202 by the first bus master unit 208 is completed after the output of the first bus access stop signal 211, the first bus access retry signal 212 is output to the second bus master unit 213. Have the function to

The inter-bus access competition arbitration means 218 outputs the second bus access request 209 from the first inter-bus access control means 215 and the second inter-bus access control means 217 to the first bus access request 204. Is output, the first bus access request 20
When priority is given to No. 4, the second inter-bus access control means 2
17 has a function of outputting the first bus access request cancellation signal 216. Then, the second bus access request 2
When the priority is given to 09, it has a function of outputting the second bus access request cancellation signal 214 to the first inter-bus access control means 215.

In the above configuration of the first, second or third aspect of the present invention, after the bus which is the target of the bus access request is connected to another bus by the switch means,
The device connected to the bus that is the target of the bus access request processes the control signal such as the address strobe signal that has disappeared on the bus to another control signal such as the data strobe signal that has not disappeared on the bus. Can be configured to be based on.

Alternatively, the switch control means may be configured to reproduce a control signal such as an address strobe signal that has disappeared on the connected buses when connecting the two or more buses to the switch means. You can also

[0025]

In the first aspect of the present invention, normally, the switch control means does not connect a plurality of buses to the switch means, and the intra-bus access control means connected to each bus is its own bus. Internal bus access control can be performed independently and in parallel. As a result, the throughput of the entire device can be improved.

When a device connected to an arbitrary bus accesses another bus, the bus access request output means outputs a bus access request to another bus other than the own bus.
As a result, the inter-bus access control means for the other bus performs bus access for the other bus based on the bus access request. Also, the switch control means connects the buses related to the above-mentioned bus access to the switch means.

In the second aspect of the present invention, the first bus 10
1 is connected to a first bus master unit 104 such as a general-purpose CPU having no other bus access function, and the second bus 10
In the configuration in which the second bus master unit 108 having the other bus access function is connected to 2, the mutual access between the first bus 101 and the second bus 102 is realized.

Here, the address for the first bus master means 104 to access the second bus 102 is the first bus 1
If 01 is specified, inter-bus access control means 1
09 outputs the second bus access request 107 to the second bus master unit 108. As a result, the second bus master unit 108 performs appropriate arbitration control of the competition between the first bus 101 and the second bus 102, and also controls the switch unit 103. As a result, the first bus master unit 104 can access the second bus 102 via the first bus 101.

On the other hand, the second bus master means 108 is the first
Address for accessing the bus 101 of the second bus 10
In the case of specifying for 2, first, the second bus master unit 108 itself outputs the first bus access request 105 to the first bus master unit 104. Then, the second bus master unit 108 waits for the bus release notification 106 from the first bus master unit 104, and specifies the address for accessing the first bus 101 to the second bus 102. As a result, the second bus master unit 108 becomes the second bus master unit 108.
The first bus 101 can be accessed via this bus 102.

In the third aspect of the present invention, the first bus 20
First bus master unit 208 such as a general-purpose CPU having no other bus access function on both the first and second buses 202
And the second bus master unit 209 are connected, mutual access between the first bus 201 and the second bus 202 is realized.

Here, the address for the first bus master unit 208 to access the second bus 202 is the first bus 2
When 01 is designated, the first inter-bus access control means 215 outputs the second bus access request 209 to the second bus master means 213. As a result, the second inter-bus access control means 217 controls the switch means 203 according to the second bus release notification 210 from the second bus master means 213. As a result, the first bus master unit 208 causes the second bus 2 via the first bus 201.
02 becomes accessible.

Similarly, the address for the second bus master unit 213 to access the first bus 201 is set to the second bus 2
In the case of specifying 02, the second inter-bus access control means 217 outputs the first bus access request 204 to the first bus master means 208. As a result, the first inter-bus access control means 215 controls the switch means 203 according to the first bus release notification 205 from the first bus master means 208. As a result, the second bus master unit 213 causes the first bus 2 via the second bus 202.
01 becomes accessible.

When the second bus access request 209 and the first bus access request 204 conflict, the inter-bus access conflict arbitration means 218 arbitrates. And
The inter-bus access contention arbitration means 218 outputs the first bus access request withdrawal signal 216 to the second inter-bus access control means 217 when giving priority to the second bus access request 209. Upon receiving this, the second inter-bus access control means 217, the second bus master means 213.
And outputs the first bus access stop signal 211 to the first bus access request 204 and withdraws the first bus access request 204. As a result, the first bus master unit 208 can access the second bus 202 via the first bus 201.

Similarly, inter-bus access contention arbitration means 21.
When giving priority to the first bus access request 204, 8 outputs the second bus access request withdrawal signal 214 to the first inter-bus access control means 215. Upon receiving this, the first inter-bus access control means 215 sends the second bus access stop signal 2 to the first bus master means 208.
06 is output and the second bus access request 209 is canceled. As a result, the second bus master unit 213
Makes it possible to access the first bus 201 via the second bus 202.

Here, after the bus targeted for the bus access request is connected to another bus by the switch means, the device connected to the bus targeted for the bus access request disappears on the bus. Processing for control signals such as address strobe signals cannot be performed. Therefore, if these devices are configured to perform the processing based on other control signals such as a data strobe signal that has not disappeared on the bus, the same processing as that for the address stove signal can be performed. Become.

Alternatively, when the switch control means connects two or more buses to the switch means, the switch control means reproduces a control signal such as an address strobe signal disappearing on the connected buses. A device connected to the bus that is the target of the bus access request can perform processing on the address stove signal.

[0037]

Embodiments of the present invention will now be described in detail with reference to the drawings. <Overall Configuration of First Embodiment> FIG. 3 is a configuration diagram of a network to which the first embodiment of the present invention is applied.

A network 301 constructed around an optical fiber ring 306 has a plurality of nodes 302 (see FIG. 3).
Are indicated by numbers such as # 000, # ***, # %%%, etc.)
Are connected.

At node 302, processor bus 3
A plurality of processors 304 are connected to 05, and a processor bus 305 is accommodated in the message communication device 303. The message communication device 303 has a processor bus 30.
5, the processor 304 processes the message data transmitted or received, and processes the frame in which the message data input to or output from the optical fiber ring 306 is stored. This message communication device 303
The configuration of the buses within is most relevant to the present invention.

Next, FIG. 4 shows FIG. 3 in the first embodiment.
3 is a configuration diagram of a message communication device 303 in the node 302 of FIG. The real memory 407 functions as a communication buffer that temporarily holds message data.

The control memory 408, for each virtual page address in the virtual storage space used for message communication, if the virtual page address is assigned to the real page address in the real memory 407, the real page The address and data indicating the page state (communication state) of the virtual page address are stored.

The processor bus interface 412 is
3 is connected to the external bus 401 while accommodating the processor bus 305 of FIG. 3, and message data and the like input from the processor 304 of FIG. 3 via the processor bus 305 is real memory via the external bus 401 and the virtual memory controller 409. 407, and conversely, message data and the like input from the real memory 407 via the virtual memory controller 409 and the external bus 401 are output to the processor 304 via the processor bus 305.

Further, the processor bus interface 41
2 exchanges communication control data with the CPU 413 via the external bus 401, the bus coupling unit 411, and the CPU bus 402.

Although not explicitly shown in FIG. 3, in FIG. 4, two processor buses 305 are provided per node. Therefore, the processor bus interface 412 also
Two # 0 and # 1 are provided corresponding to each processor bus 305. Then, the # 0 processor bus interface 412 uses the control line 419 to perform contention control when the # 0 and # 1 processor bus interfaces 412 access the external bus 401. Further, the processor bus interface 412 of # 0 has control lines 421 and 422.
Via a CPU bus arbiter 414 and I /
While exchanging control data regarding bus use with the O controller 415, competition control of the external bus 401 is performed, and opening / closing control of the bus coupling unit 411 is performed via the control line 420 when necessary.

The network control circuit 410 sends the frame from the CPU 413 to the CPU bus 402, I.
/ O controller 415 and control command 408 via control memory access bus 406 based on send commands input via network command / result bus 403.
While accessing, read message data to be transmitted from the real memory 407 via the virtual memory controller 409 and the network data transmission bus 405, construct a transmission frame including the message data, and send it to the optical fiber ring 306. The transmission result is sent to the network command / result bus 403 and I / O controller 41.
5 and the CPU 413 via the CPU bus 402.

Further, the network control circuit 410, when receiving a frame from the optical fiber ring 306, controls the control memory 408 via the control memory access bus 406.
Access the received frame to another node 3
Relay to 02. Alternatively, the message data in the received frame is extracted and the network data reception bus 40
4 to the real memory 407 via the virtual memory controller 409, and the reception result is notified to the CPU 413 via the network command / result bus 403, the I / O controller 415, and the CPU bus 402.

The CPU 413 is connected to the CPU bus 402 and is connected to the CPU bus 402 at the start of operation.
It operates according to the control program written in the program RAM 417 connected from the PROM 416 to the CPU bus 402.

This CPU 413 has a CPU bus 402,
Communication control data is exchanged with the processor bus interface 412 via the bus coupling unit 411 and the external bus 401.

The CPU 413, when transmitting a frame, uses the CPU bus 402, the I / O controller 415,
And output a send command to the network control circuit 410 via the network command / result bus 403, and thereafter
From the network control circuit 410, a network command /
Result bus 403, I / O controller 415, and CP
The transmission result notification is received via the U bus 402. Conversely, the CPU 413 receives from the network control circuit 410 the network command / result bus 403, the I / O controller 415, and the CPU bus 4 when receiving a frame.
A reception result notification is received via 02.

Further, the CPU 413 has a CPU bus 402.
The page state data (data indicating the communication state) of each virtual page address in the control memory 408 is accessed via the control memory 408, and the realization of each virtual page address in the control memory 408 is performed via the CPU bus 402 and the virtual memory controller 409. The page address data and the real memory 407 are accessed.

The I / O controller 415 is connected to the CPU bus 402 and accommodates a peripheral device bus 418 to which external peripheral devices are connected. In addition, I / O controller 4
As described above, the relay unit 15 relays the transmission command, the transmission result notification, or the reception result notification exchanged between the CPU 413 and the network control circuit 410 via the CPU bus 402 and the network command / result bus 403.

Further, the I / O controller 415 uses the CP
U413 is the address for accessing the external bus 401 to C
When specified for the PU bus 402, the control line 422
To the processor bus interface 412 of # 0 via
Outputs an external bus access request.

The CPU bus arbiter 414 is C from the processor bus interface 412 via the control line 421.
When the PU bus access request (bus grant request) is received, the bus use request (bus grant request) is output to the CPU 413 via the control line 423, and the CPU 4
13 receives a bus use permission (bus grant acknowledge) from the control line 423 via the control line 423.
Bus access permission (bus grant acknowledge) is sent via the control line 421 to the # 0 processor bus interface 4
Return to 12.

The virtual memory controller 409 is
Processor bus interface 412 and real memory 407
Data exchanged with the external bus 401, C
Data transmitted and received between the PU 413 and the real memory 407 or the control memory 408 via the CPU bus 402, and between the network control circuit 410 and the real memory 407 via the network data reception bus 404 or the network data transmission bus 405. The switching control and the contention control of the exchanged data are performed.

The operation of the first embodiment having the above configuration will be described. <Overall operation of inter-processor communication> Now, in FIG. 3 and FIG. 4, for example, message data is sent from one processor 304 in the node 302 of # 000 to another processor 304 in the node 302 of # ***. The overall operation when transmitting will be described.

In this case, the message data transmitted from one processor 304 in the node # 000 is the message communication device 303 in that node (hereinafter, the message communication device 303 in # 000) via the processor bus 305. Call)) to the real memory 407,
The message is sent to the real memory 407 of the message communication device 303 in the node 302 of # *** (hereinafter referred to as the message communication device 303 of # ***), and then the destination from the real memory 407 via the processor bus 305. The processor 304
Transferred to. That is, the real memory 407 of each message communication device 303 functions as a communication buffer. Communication method between message communication apparatuses 303 Here, a special method called a network virtual storage method is applied to communication of message data between the message communication apparatuses 303.

First, in the entire network 301 of FIG.
A virtual memory space is defined. This virtual storage space is divided into a plurality of virtual pages, and message data is communicated via these virtual pages. For example, the virtual storage space is divided into virtual page addresses of 0000 to FFFF pages (hexadecimal number). One virtual page has a fixed length (for example, 8 kilobyte length) data length that can sufficiently accommodate a packet that is one unit of message data. Unless otherwise specified, the virtual page address and the dictated real page address are represented by hexadecimal numbers.

Next, the message communication device 303 of each node 302 connected to the network 301 is allocated for every predetermined number of pages of this virtual storage space, for example, every 16 pages. For example, the message communication device 303 of the # 000th node 302 is allocated to the 0000 to 000F page, the message communication device 303 of the # 001th node 302 is allocated to the 0010 to 001F page, and so on. ** 0-*** F page and %%% 0-%%% F page (3 digit *
And% are arbitrary numbers in hexadecimal numbers from 0 to F), the message communication device 303 of each of the # *** th and # %%% th nodes 302 is assigned.

Therefore, in the above example, the network 30
1, a maximum of 4096 message communication devices 303 from # 000 to #FFF can be connected. On the other hand, the real memory 407 in each message communication device 303 is divided into a plurality of real pages each having the same data length as the above-mentioned virtual page. The page capacity of the real memory 407 may be much smaller than the page capacity of the virtual storage space, and may be, for example, about 64 to 256 pages.

Next, as shown in FIG. 5, control data for all virtual page addresses is stored in the control memory 408 of each message communication device 303. As shown in FIG. 5, the control data of each virtual page address indicates the real page address data of the real memory 407 in the own message communication device 303 associated with the virtual page address and the communication state of the virtual page address. And page status data shown.

Then, as an initial state, each node 302
In the control memory 408 of the message communication device 303 in the internal message communication device 303, an arbitrary empty page in the real memory 407 of the message communication device 303 is assigned to the virtual page address assigned to the node 302 by the network reception control function of the CPU 413. The real page address of the network receiving buffer provided in the above and the receiving buffer allocation state VP as the page state are written in advance. The network reception control function is a CP
This is realized by the U413 executing the control program stored in the program RAM 417.

For example, # 000 message communication device 303
In the control memory 408 of the self message communication device 3
As shown in FIG. 5, each virtual page address of 0000,0001, ..., 000F pages allocated to the 03 is assigned to each real page of s, q, ..., p in the real memory 407. The address has been written and the page status VP indicating the receive buffer allocation status has been written.

In the control memory 408 of the # *** message communication device 303, the own message communication device 30
As shown in FIG. 5, each virtual page address of **** 0, *** 1, ..., *** F page assigned to
The page status indicating the receive buffer allocation status in which each real page address of v, u, ..., T in the real memory 407 is written.
VP is written.

Similarly, # %%% message communication device 303
In the control memory 408 of the self message communication device 3
, %%% 0, %%% 1, ..., %%% F, the virtual page addresses assigned to pages 03, y, w, in real memory 407 are as shown in FIG. , X are written, and the page state VP indicating the receive buffer allocation state is written.

Now, by the transfer operation described later, for example, # 000
The message data is transferred from one processor 304 in the node # 000 302 to the network transmission buffer (to be described later) whose real page address is r in the real memory 407 of the message communication device 303 of FIG. To do.

The network transmission control function of the CPU 413 analyzes the destination address part in the header of the message data stored in the network transmission buffer in the real memory 407 via the CPU bus 402 and the virtual memory controller 409. By doing so, the virtual page address assigned to the node 302 accommodating the processor 304 corresponding to the destination address, which has the page state of the buffer unallocated state NA, is determined. In the example of FIG. 5, for example, the virtual page address *** 2 is determined. The network transmission control function is realized by the CPU 413 executing the control program stored in the program RAM 417.

Next, the network transmission control function of the CPU 413 writes the real page address of the network transmission buffer in which the above-mentioned message data is stored in the determined virtual page address in the control memory 408, Change the status from the buffer unallocated status NA to the transmission status SD. In the example of FIG. 5, the real page address r and the transmission state SD are set to the virtual page address *** 2, for example.

The transmission control function for the network of the CPU 413 is the transmission F function in the I / O controller 415.
The virtual page address described above and the transfer length of the message data described above are written into the IFO via the CPU bus 402 together with the transmission command.

When the network control circuit 410 reads the above-mentioned transmission command or the like from the transmission FIFO in the I / O controller 415 via the network command / result bus 403, the virtual page added to the transmission command. The address is specified in the control memory 408 via the control memory access bus 406, the real page address set in the above virtual page address is read from the control memory 408, and set in the DMA transfer register in the virtual memory controller 409. To do.

Then, the network control circuit 410
The page data of the real page address in the real memory 407 including the message data to be transmitted to the virtual memory controller 409 is transferred via the network data transmission bus 405 to the network control circuit 410.
To DMA transfer.

The network control circuit 410 extracts message data corresponding to the transfer length of the message data added to the send command from the above page data, and the message data and the virtual page address added to the send command. And a transmission frame including the transfer length of the message data and generating the transmission frame.
Send to 6. The token ring network method is adopted as the frame transmission method of the optical fiber ring 306, and the network control circuit 410 can send the transmission frame only when a free token circulating on the optical fiber ring 306 is acquired. .

In the example of FIG. 5, the transmission frame including the virtual page address *** 2 and the message data stored in the real page address r in the real memory 407 is sent from the message communication device 303 of # 000. It is sent to the optical fiber ring 306.

The above-mentioned transmission frame is transmitted to another node 302 (see FIG. 3) connected to the optical fiber ring 306.
Are sequentially transferred to. When the network control circuit 410 of the message communication device 303 in each node 302 fetches the transmission frame from the optical fiber ring 306, the page state corresponding to the virtual page address stored in the transmission frame is controlled by the control memory access bus 406. Read from the control memory 408 via, and whether or not the page state is the receive buffer allocation state VP, that is, whether or not the virtual page address is assigned to the message communication device 303 of the own node 302, or the page It is determined whether or not the state is the transmission state SD, that is, whether or not the transmission frame is transmitted by the own network control circuit 410.

When the network control circuit 410 determines that the page state of the virtual page address stored in the transmission frame is the reception buffer allocation state VP,
The message data stored in the transmission frame is fetched in the real memory 407 as follows.

That is, the network control circuit 410 first designates the virtual page address stored in the transmission frame to the control memory 408 via the control memory access bus 406, and the control memory 408 changes the virtual page address to the above virtual page address. The set real page address is read out and set in the DMA transfer register in the virtual memory controller 409. Then, the network control circuit 410 causes the virtual memory controller 409 to
The message data included in the transmission frame is DMA-transferred to the above-mentioned real page address in the real memory 407 via the network data reception bus 404.

After that, the network control circuit 410
The virtual page address stored in the transmission frame is
Control memory 40 via control memory access bus 406
8 is specified, and the page status of the virtual page address is changed from the reception buffer allocation status VP to the reception completion status RD.

Further, the network control circuit 410 is
The virtual page address extracted from the transmission frame and the transfer length of the message data are written to the reception FIFO in the / O controller 415 via the network command / result bus 403 together with the result code indicating the success or failure of the reception.

Finally, the network control circuit 410
After writing the reception success notification in the response area in the above-mentioned transmission frame received from the optical fiber ring 306, the transmission frame is sent to the optical fiber ring 306 again.

For example, in the example of FIG. 5, the network control circuit 410 of the message communication device 303 of # *** is # 000.
The message stored in the transmission frame is determined by determining that the page state on the control memory 408 of the virtual page address *** 2 stored in the transmission frame from the node 302 is the reception buffer allocation state VP. The data is transferred to the real memory 40 having the real page address u set to the virtual page address *** 2 of the control memory 408.
After being fetched into the network receive buffer in 7, the page state of the virtual page address *** 2 of the control memory 408 is changed from the receive buffer allocation state VP to the reception completion state RD.

The above-mentioned reception result notification is received by the CPU 413 via the CPU bus 402. That is, CP
The reception control function for the network of U413 is the reception F in the I / O controller 415 via the CPU bus 402.
When the above result notification is received from the IFO and if the result code is successful, the virtual page address that is a part of the result notification is specified in the control memory 408 via the CPU bus 402, and the page status Read the real page address.

If the page state described above is the reception completion state RD, the network reception control function of the CPU 413 first controls the real memory 407 via the CPU bus 402 and the virtual memory controller 409 to make the above-mentioned real state. Separates the real page specified by the page address from the network receive buffer and connects it to the processor send-wait buffer queue.

After that, the network reception control function of the CPU 413 controls the real memory 407 via the CPU bus 402 and the virtual memory controller 409 to connect an arbitrary empty page to the network reception buffer. Control memory 4 via CPU bus 402 with a virtual page address that is part of the reception result notification
08 is accessed, and the real page address of the above-mentioned empty page and the reception buffer allocation state VP as the page state are written to the virtual page address.

Thereafter, the processing for the processor transmission waiting buffer queue in the real memory 407 is performed by the CPU 41.
3 from the network reception control function to the processor transmission control function described later.

On the other hand, the network control circuit 410 reads out the page state corresponding to the virtual page address stored in the transmission frame from the control memory 408, and as a result, the page state is neither the reception buffer allocation state VP nor the transmission state SD. If it is determined that the transmission frame is transmitted, the transmission frame is directly transmitted to the optical fiber ring 306.

For example, in the example of FIG. 5, the network control circuit 410 of the # %%% message communication device 303 uses the # 000
By determining that the page state on the control memory 408 of the virtual page address *** 2 stored in the transmission frame from the node 302 of the node 302 is neither the reception buffer allocation state VP nor the transmission state SD, the transmission frame is left as it is. It is sent to the optical fiber ring 306.

Optical fiber ring 306 as described above.
The transmission frame sequentially transferred above returns to the network control circuit 410 of the message communication device 303 in the node 302 which is the transmission source.

The source network control circuit 410 is
As a result of reading the page state corresponding to the virtual page address stored in the transmission frame from the control memory 408, by determining that it is the transmission state SD,
It is determined that the transmission frame is the transmission frame transmitted by the own network control circuit 410.

In this case, the network control circuit 410
After confirming that the reception success notification is written in the response area of the received transmission frame, the control memory 408 of the control memory 408 corresponding to the virtual page address stored in the transmission frame is transmitted via the control memory access bus 406. The page state is changed from the transmission state SD to the transmission completion state SC.

Then, the network control circuit 410
The virtual page address extracted from the transmission frame is written to the reception FIFO in the I / O controller 415 via the network command / result bus 403 together with the result code indicating the success or failure of the transmission.

The above-mentioned transmission result notification is received by the CPU 413 via the CPU bus 402. That is, CP
The network transmission control function of the U413 is performed by the reception F in the I / O controller 415 via the CPU bus 402.
When the above result notification is received from the IFO, if the result code is successful, the virtual page address that is a part of the result notification is specified in the control memory 408 via the CPU bus 402, and the page status is changed. Read the real page address.

If the above-mentioned page state is the transmission completion state SC, the network transmission control function of the CPU 413 first controls the real memory 407 via the CPU bus 402 and the virtual memory controller 409 to make the above-mentioned real state. The real page specified by the page address is separated from the network send buffer and used as a free page.

After that, the network transmission control function of the CPU 413 controls the control memory 4 via the CPU bus 402 with the virtual page address which is a part of the above-mentioned transmission result notification.
08 is accessed, and the buffer unallocated state NA is written as the page state of the virtual page address.

As described above, the network 301 (see FIG.
In the above, one virtual storage space is defined, and a virtual page having a fixed data length that constitutes this space is assigned to each message communication device 303. Then, the communication of the message data between the message communication devices 303 is performed using this virtual page. As a result, blocking control and sequence control that are performed in normal packet communication are not required.

When the network control circuit 410 of the message communication device 303 in each node 302 on the optical fiber ring 306 receives a transmission frame, the virtual page address stored in the transmission frame causes the network control circuit 410 on the control memory 408. By accessing the page state, the received transmission frame can be processed at high speed.

In addition, a response area is provided in the transmission frame transferred on the optical fiber ring 306, and the network control circuit 410 of the message communication device 303 in the node 302 on the reception side transmits the reception result of the transmission frame. It writes in the response area of the frame and sends it out again to the optical fiber ring 306. Therefore, by the time this transmission frame is transferred on the optical fiber ring 306 and returned to the transmission source, the message data transmission processing is completed, and the response from the reception side to the transmission source is sent using another frame. No need to notify. As a result, the communication protocol can be simplified and high-speed response processing can be performed.

Further, the communication of the message data between the message communication devices 303 is performed using the real memory 407 while the network control circuit 410 in the message communication device 303 accesses the control memory 408, and the processor 304 and the message communication device 303 communicate with each other. Communication of message data between the 303 is performed by the message communication device 3 as described later.
The processor bus interface 412 in 03 uses the real memory 407 independently of the operation of the network control circuit 410 described above. Furthermore, the correspondence between the message data stored at the real page address in the real memory 407 and the virtual page address in the virtual memory space is as described below, by the destination address in the header added by the CPU 413 to the message data. Based on. Therefore, between the processor 304 and the message communication device 303,
Message communication device 303 and message communication device 303
It is possible to efficiently perform the processing between them at high speed. From the processor 304 at the sender to the message communication device
Operation of Transferring Message Data to Device 303 Next, from one processor 304 in the source node 302 (node # 302 in the example of FIG. 5) to the real memory 407 of the message communication device 303 in that node, The operation when the message data is transferred will be described.

First, the processor reception control function of the CPU 413 accesses the real memory 407 via the CPU bus 402 and the virtual memory controller 409 to connect the processor reception buffer queue to the free buffer queue in the real memory 407. Connect the free buffer that is being used. The processor reception control function is a function realized by the CPU 413 executing the control program stored in the program RAM 417.

Then, the processor reception control function of the CPU 413 activates, for example, the # 0 processor bus interface 412 via the CPU bus 402, the bus coupling unit 411, and the external bus 401, and The start address of the above-mentioned processor receive buffer queue is notified.

The processor bus interface 412 is
The message data transferred from the processor 304 via the processor bus 305 is received, the buffer address is sequentially updated with the start address as the reception start address, and the received message data is
External bus 401 and virtual memory controller 40
9 is sequentially transferred to a free buffer connected to the processor reception buffer queue in the real memory 407.

The processor bus interface 412 is
When there is no free buffer connected to the processor reception buffer queue, the free buffer is automatically stopped, and the fact is notified to the CPU 413 via the external bus 401, the bus coupling unit 411, and the CPU bus 402.

The processor reception control function of the CPU 413 first controls the real memory 407 via the CPU bus 402 and the virtual memory controller 409 to separate the above-mentioned received buffer from the processor reception buffer queue and transmit it to the network. Connect to a buffer. After that, the processing for the network transmission buffer in the real memory 407 is handed over from the processor reception control function of the CPU 413 to the network transmission control function described above, and the transmission source according to the communication method between the message communication devices 303 described above. From the real memory 407 in the message communication device 303 of the node 302 (# 000 message communication device 303 in the example of FIG. 5), the message communication device 303 of the node 302 (in the example of FIG. 5) in which the destination processor 304 is accommodated # *** message communication device 30
The message data transfer operation to the real memory 407 in 3) is executed. From the message communication device 303 on the receiving side to the process
Transfer Operation of Message Data to Server 304 Next, the real memory 4 of the message communication device 303 in the receiving node 302 (# *** node 302 in the example of FIG. 5)
07 to one processor 304 within that node 302
The operation when the message data is transferred will be described below.

When the network control circuit 410 succeeds in receiving the transmission frame, as described above, the CPU 413
The network reception control function of (1) connects the received message data to the processor transmission waiting buffer queue in the real memory 407.

On the other hand, the processor transmission control function of the CPU 413 includes the CPU bus 402 and the bus coupling unit 41.
For example, the # 0 processor bus interface 412 is activated via 1 and the external bus 401, and the interface 412 is notified of the start address of the above-mentioned processor transmission waiting buffer queue.

The processor bus interface 412 is
While sequentially updating the buffer address with the start address as the transmission start address, the real memory 40 is passed through the external bus 401 and the virtual memory controller 409.
7 sequentially reads the message data stored in the buffer connected to the processor transmission waiting buffer queue, analyzes the destination address part in the header of the message data, and transfers the message data to the processor bus 305. Via the destination processor 304. <Connection control operation between the external bus 401 and the CPU bus 402> Next, the external bus 401 and the CPU particularly related to the present invention
The connection control operation between the buses 402 will be described. When the external bus 401 and the CPU bus 402 are connected In the first embodiment, normally, the bus coupling unit 411 does not connect the external bus 401 and the CPU bus 402, and
The # 1 processor bus interface 412 is the real memory 4
07, the operation of accessing the external bus 401 to exchange message data and the like and the operation of the CPU 413 accessing the CPU bus 402 to access the real memory 407 or the control memory 408 are independent and parallel. You can do it. As a result, the throughput of the entire message communication device 303 can be improved.

On the other hand, as the first case, as described above, when the transfer operation of the message data between the processor 304 and the message communication device 303 is started, the CPU 413
Activates, for example, the # 0 processor bus interface 412 from the CPU bus 402 over the bus coupling unit 411 via the external bus 401, and sends a processor receive buffer queue or processor send wait buffer to the interface 412. Notify the start address of the queue.

In the second case, as described above, the processor bus interface 412 is connected to the processor reception buffer queue during the transfer of the message data from the processor 304 at the transmission source to the message communication device 303. When there are no free buffers,
Automatically stop and connect external bus 401 to bus 411
To that effect via the CPU bus 402
Notify 13

In the above case, the bus coupling unit 411
Connects the external bus 401 and the CPU bus 402, and operates so that one bus can access the other bus.
In this case, if the bus cycle of the other bus is being executed at the time when the access to the other bus occurs, it is necessary to arbitrate the contention for the bus access. The arbitration control is performed by the # 0 processor bus interface 41.
2. The CPU bus arbiter 414 and the I / O controller 415 are realized by executing the operations as described below. Case where CPU 413 Accesses External Bus 401 First, the case where the CPU 413 accesses the external bus 401, as in the case where the CPU 413 activates the # 0 processor bus interface 412 in the above-described first case, will be described.

In this case, the CPU 413 determines that the external bus 40
An address for accessing 1 is designated to the CPU bus 402. I / O connected to CPU bus 402
In the controller 415, the CPU 413 is the CPU bus 40.
It monitors the address specified for 2, and CPU4
13 uses the address for accessing the external bus 401 as the CPU
When the bus 402 is designated, an external bus access request is output to the # 0 processor bus interface 412 via the control line 422.

In response to this access request, the external bus 40
# 0 processor bus interface 41 connected to 1
2 is the processor bus interface 412 of # 0 and # 1
Immediately open the external bus 401 when both are not accessing the external bus 401, and either the processor bus interface 412 of # 0 or # 1 releases the external bus 4
When 01 is being accessed, the external bus 401 is released after waiting for the end of the access. After that, the # 0 processor bus interface 412 controls the bus coupling unit 411 via the control line 420 to connect the external bus 401 and the CPU bus 402. As a result, the CPU 413 can access the external bus 401 after taking appropriate timing.

# 0 processor bus interface 412
Secures the external bus 401 again when the access to the external bus 401 by the CPU 413 ends. Also, # 0
The processor bus interface 412 of the CPU 41
When the access to the external bus 401 by 3 is completed, the bus coupling unit 411 is controlled via the control line 420 to disconnect the external bus 401 and the CPU bus 402. A tool for the CPU 413 to access the external bus 401
Body Example A specific example of the timing when the CPU 413 accesses the external bus 401 will be described with reference to the timing chart of FIG. In addition, in FIG.
The shaded period is a range in which the change of the signal can fluctuate based on signal rounding or bus delay. Also,
It is assumed that the signals shown in FIGS. 6D to 6H become active when they become low level.

FIG. 6A shows the system clock CLK (φ
6 (b) is a bus clock BCLK generated based on CLK. Each control signal for bus access control is these clocks CLK or BCL
It is output in synchronization with K.

When accessing the CPU bus 402, the CPU 413 first sends CP as shown in FIG. 6 (d).
In the U bus 402, the signal BS- indicating that it is valid is activated. In synchronization with this, the state of the CPU bus 402 is determined at the timing shown in FIG. 6 (c).

When the state of the CPU bus 402 is confirmed, C
The PU 413, as shown in FIG. 6 (e), is an address strobe signal for displaying the valid period of the address bus.
AS- is activated, and subsequently, as shown in FIG. 6 (f), the data strobe signal DS- for indicating that the data bus is valid and for indicating the period of the bus cycle is activated.

Here, the CPU 413 determines that the external bus 401
When an address to access the CPU bus 402 is designated, the I / O controller 415 causes the # 0 processor bus interface 4 to pass through the control line 422.
The external bus access request output to 12 is activated as shown in FIG. 6 (g).

In response to this access request, the external bus 40
# 0 processor bus interface 41 connected to 1
2 is the processor bus interface 412 of # 0 and # 1
When both of them are not accessing the external bus 401, the external bus 401 is released, and the bus coupling unit 411
A signal for controlling the buffer connection output via the control line 420 is activated as shown in FIG. 6 (h) to connect the external bus 401 and the CPU bus 402.

In synchronization with this, the state of the external bus 401 is determined at the timing shown in FIG.
13 is an external bus 40 after taking appropriate timing.
1 becomes accessible.

Here, in the example of FIG. 6, when the state of the external bus 401 is determined as shown in FIG. 6 (i), the address strobe signal AS on the external bus 401 connected to the CPU bus 402 is connected. Since-has already returned to the inactive state, the processor bus interface 412 cannot discriminate the address strobe signal AS- in the active state. Therefore, the processor bus interface 412 is activated by the data strobe signal DS- as shown in FIG. 6 (f).
Execute the bus cycle based on

Alternatively, immediately before the signal for controlling the buffer connection on the control line 420 becomes active, the external bus 4
A circuit that activates the address strobe signal AS- on 01 for a certain period based on the bus specifications is provided, and the processor bus 105 uses the external bus 4 as in the normal operation.
The bus cycle may be executed based on the active address strobe signal AS- on 01.

In response to an external bus access request from the I / O controller 415, when the # 0 or # 1 processor bus interface 412 connected to the external bus 401 is accessing the external bus 401, the access Since the external bus 401 is released and the bus coupling unit 411 is controlled after waiting for the end, the timing for the signal for buffer connection control to become active and the state of the external bus 401 to be determined is shown in FIGS. 6 (h) and 6 (i). Is later than the timing of. The processor bus interface 412 is the CPU bus 40.
2. When accessing the processor bus interface 412 that accesses the CPU bus 402 as in the case of the # 0 or # 1 processor bus interface 412 notifying the CPU 413 in the above-described second case. explain.

First, when the # 0 processor bus interface 412 accesses the CPU bus 402 and no external bus access request is input from the CPU bus arbiter 414, the # 0 processor bus interface 412 transfers to the CPU bus arbiter 414. In response, a CPU bus access request (bus grant request) is output via the control line 421. When the # 1 processor bus interface 412 accesses the CPU bus 402 and no external bus access request is input from the CPU bus arbiter 414, first, the # 1 processor bus interface 412 passes through the control line 419. # 0
The CPU bus access request is output to the processor bus interface 412 of # 1, and based on this, the # 0 processor bus interface 412 outputs the CPU bus access request to the CPU bus arbiter 414 via the control line 421.

When the CPU bus arbiter 414 receives the CPU bus access request, it outputs a bus use request (bus grant request) to the CPU 413 via the control line 423. The CPU 413 is the CPU bus 4
02 when not accessing or CPU bus 4
02 when the access to the CPU bus 402 is completed.
To output a bus use permission (bus grant acknowledge) to the CPU bus arbiter 414 via the control line 423. Upon receiving the bus use permission, the CPU bus arbiter 414 returns a CPU bus access permission (bus grant acknowledge) to the # 0 processor bus interface 412 via the control line 421 based on the permission.

# 0 processor bus interface 412
Upon receiving the above-mentioned CPU bus access permission, controls the bus coupling unit 411 via the control line 420 to connect the external bus 401 and the CPU bus 402.

After that, when the processor bus interface 412 of # 0 itself accesses the CPU bus 402, it specifies an address for accessing the CPU bus 402 to the external bus 401. Further, the # 0 processor bus interface 412 is connected to the # 1 processor bus interface 412 when the # 1 processor bus interface 412 accesses the CPU bus 402.
A bus access permission is output via the control line 419. As a result, # 1 processor bus interface 4
Reference numeral 12 designates an address for accessing the CPU bus 402 to the external bus 401.

# 0 processor bus interface 412
Is the processor bus interface 4 of itself or # 1
When 12 has finished accessing the CPU bus 402, it controls the bus coupling unit 411 via the control line 420 to disconnect the external bus 401 and the CPU bus 402. The processor bus interface 412 is the CPU bus 40.
2. Specific Example of Accessing 2 A specific example of the timing when the processor bus interface 412 accesses the CPU bus 402 will be described with reference to the timing chart of FIG. In FIG. 7, the shaded period is a range in which the change in the signal can fluctuate based on the signal rounding or the bus delay. The signals shown in FIGS. 7 (c) to 7 (e) are assumed to be active when they become low level.

FIG. 7A shows the system clock CLK (φ
1 and φ2), and FIG. 7B shows the bus clock BCLK generated based on CLK. Each control signal for bus access control is these clocks CLK or BCL
It is output in synchronization with K.

When the # 0 or # 1 processor bus interface 412 accesses the CPU bus 402, the # 0 processor bus interface 412 outputs a CP to the CPU bus arbiter 414 via the control line 421.
The U bus access request is activated as shown in FIG. 6 (c).

When the CPU bus arbiter 414 receives the CPU bus access request, it outputs a bus use request to the CPU 413 via the control line 423, and the CPU
CPU bus access permission is received from the control bus 413 via the control line 423 and is returned to the # 0 processor bus interface 412 via the control line 421 based on the permission to activate the CPU bus access permission as shown in FIG. 6 (d). To do.

# 0 processor bus interface 412
When receiving the above-mentioned CPU bus access permission, activates the signal for buffer connection control output to the bus coupling unit 411 via the control line 420 as shown in FIG. Bus 401 and CPU bus 40
Connect 2

In synchronization with this, the state of the external bus 401 is determined at the timing shown in FIG.
The processor bus interface 412 of the external bus 4
01 becomes accessible. <Structure and Operation of Second Embodiment> FIG. 8 shows a second embodiment of the present invention.
It is a block diagram of the Example of.

In the message communication device 103 of FIG. 4 in the above-mentioned first embodiment, the processor bus interface 412 of # 0 connected to the external bus 401 is
It is realized as a dedicated circuit having an arbitration function of competition between the external bus 401 and the CPU bus 402 and having a control function of the bus coupling unit 411. The use of such a dedicated circuit enables mutual access between two buses in which a general-purpose CPU is connected to one bus.

On the other hand, in the second embodiment shown in FIG. 8, when a general-purpose CPU is connected to both of the two buses, a configuration that enables mutual access between the two buses is shown. Has been done.

In FIG. 8, the buses 801 # 1 and # 2 are connected by a bus coupling unit 802. A # 1 CPU 803 and a # 1 bus arbiter 804 are connected to the # 1 bus 801, and a # 2
A # 2 CPU 803 and a # 2 bus arbiter 804 are connected to this bus 801. The bus arbiter 804 of # 1 and # 2 is
Connected to each other by control line 808, and each # 1
And the control line 809 of # 2 controls the opening / closing of the bus coupling unit 802.

The bus arbiter 804 of # 1 and # 2 has # 1 and # 2.
Bus access contention arbitration unit 81 via the control line 811 of
0 is connected. CPUs 803 of # 1 and # 2 are # 1 respectively
And memory controller 80 connected to bus 801 of # 2
Both of the # 1 and # 2 memories 806 can be accessed via the S.

Now, normally, the bus coupling unit 802 does not connect the buses 801 of # 1 and # 2, and the CPU 803 of # 1 passes the memory 8 of # 1 (or # 2) via the memory controller 805.
06 access, and the # 2 CPU 803 via the memory controller 805 the # 2 (or # 1) memory 80
The operation of accessing 6 can be done independently and in parallel. As a result, the throughput of the entire system can be improved.

On the other hand, for example, the CPU 803 of # 1 changes the C of # 2
When the # 2 bus 801 is accessed in order to communicate with the PU 803, the following control operation is executed.
First, the # 1 bus arbiter 804
When the address designated to the bus 801 of # 1 is monitored and the CPU 803 of # 1 designates the address to access the bus 801 of # 2 to the bus 801 of # 1, # 2
Bus arbiter 804 of # 2 via control line 808
The bus 801 access request is output.

The # 2 bus arbiter 804 outputs the above-mentioned # 2 when it does not output the access request for the # 1 bus 801.
CPU # 2 receives the access request of the bus 801 of
A bus use request is output to 803 via the # 2 control line 807.

As a result, the # 2 CPU 803 receives the above-mentioned bus use request, or when the access to the # 2 bus 801 is completed after receiving the bus use request, and then the # 2 bus 801.
The bus arbiter 804 of # 2 to release the bus permission to # 2
Is output via the control line 807 of.

When the # 2 bus arbiter 804 receives the above-mentioned bus use permission, the # 2 control line 809 receives it.
The bus coupling unit 802 is controlled via the
Connect 1

As a result, the # 1 CPU 803 can access the # 2 bus 801 via the # 1 bus 801 after taking appropriate timing. # 2 Bus Arbiter 80
When the access to the bus 801 of # 2 by the CPU 803 of # 1 is completed, the control unit 4 controls the bus coupling unit 802 via the control line 809 of # 2 to disconnect the bus 801 of # 1 and # 2. .

The # 2 CPU 803 secures the # 2 bus 801 when the # 1 CPU 803 finishes accessing the # 2 bus 801. The above access control operation is similarly applied when the # 2 CPU 803 accesses the # 1 bus 801 in order to communicate with the # 1 CPU 803. In this case, the # 1 CPU 803 is used. And C of # 2
The operation relationship between the PU 803 and the # 1 bus arbiter 804 and the # 2 bus arbiter 804 is opposite to the above-described operation relationship.

Next, the # 1 bus arbiter 804 outputs the access request for the # 2 bus 801 and the # 2 bus arbiter 804 outputs the # 1 bus 801 access request at the same time. In this case, the following contention arbitration control is executed.

First, the inter-bus access contention arbitration unit 810.
Is the # 1 bus arbiter 804 via the # 1 control line 811.
It is detected that the access request of the bus 801 of # 2 is output from the same, and at the same time, the access request of the bus 801 of # 1 is output from the bus arbiter 804 of # 2 via the control line 811 of # 2. In this case, contention arbitration is performed according to a predetermined contention arbitration algorithm.

Then, the inter-bus access contention arbitration unit 810.
When giving priority to the access request of the # 2 bus 801 output from the # 1 bus arbiter 804, outputs an access request withdrawal signal to the # 2 bus arbiter 804 via the # 2 control line 811.

As a result, the # 2 bus arbiter 804 responds to the above access request withdrawal signal by the # 2 CPU 80.
A bus access stop signal is output to the No. 3 via the # 2 control line 807 and the access request of the # 1 bus 801 is withdrawn.

The # 2 CPU 803 operates the # 1 bus 8 via the # 2 bus 801 based on the above-mentioned bus access stop signal.
The access to 01 is stopped, then the bus 801 of # 2 is opened, and the bus use permission is output to the bus arbiter 804 of # 2 via the control line 807 of # 2.

Upon receiving the above-mentioned bus use permission, the # 2 bus arbiter 804 receives the # 2 control line 809 based on it.
The bus coupling unit 802 is controlled via the
Connect 1

As a result, the # 1 CPU 803 can access the # 2 bus 801 via the # 1 bus 801 after taking appropriate timing. # 2 Bus Arbiter 80
When the access to the bus 801 of # 2 by the CPU 803 of # 1 is completed, the control unit 4 controls the bus coupling unit 802 via the control line 809 of # 2 to disconnect the bus 801 of # 1 and # 2. At the same time, a retry signal is output to the # 2 CPU 803 via the # 2 control line 807.

The # 2 CPU 803 responds to the above-mentioned retry signal by sending the # 2 bus 801 through the # 2 bus 801 that has been stopped.
Resume access to 01. On the other hand, when prioritizing the access request of the # 1 bus 801 output from the # 2 bus arbiter 804, the inter-bus access conflict arbitration unit 810 sends the # 1 bus arbiter 804 to the # 1 control line 811. And outputs an access request withdrawal signal.

As a result, the # 1 bus arbiter 804 responds to the above access request withdrawal signal by the # 1 CPU 80.
A bus access stop signal is output to the # 3 via the # 1 control line 807 and the access request of the # 2 bus 801 is withdrawn.

The # 1 CPU 803 sends the # 2 bus 8 via the # 1 bus 801 based on the above-mentioned bus access stop signal.
The access to 01 is stopped, then the bus 801 of # 1 is opened, and the bus use permission is output to the bus arbiter 804 of # 1 via the control line 807 of # 1.

Upon receiving the above-mentioned bus use permission, the # 1 bus arbiter 804 receives the # 1 control line 809 based on it.
The bus coupling unit 802 is controlled via the, and the bus 80 of # 2 and # 1 is controlled.
Connect 1

As a result, the # 2 CPU 803 can access the # 1 bus 801 via the # 2 bus 801 after taking appropriate timing. # 1 bus arbiter 80
When the access to the bus 801 of # 1 by the CPU 803 of # 2 ends, the control unit 4 controls the bus coupling unit 802 via the control line 809 of # 1 to disconnect the bus 801 of # 2 and # 1. At the same time, a retry signal is output to the # 1 CPU 803 via the # 1 control line 807.

The # 1 CPU 803 responds to the above-described retry signal by sending the # 2 bus 8 via the canceled # 1 bus 801.
Resume access to 01. In the above second embodiment,
For example, # 1 (or # 2) bus 801 has # 1 (or # 2) CP
When a slave CPU other than the U803 is connected, the # 1 (or # 2) bus arbiter 801 is connected to the # 1 (or #
It can be configured to also perform arbitration of competition between the CPU 803 of 2) and other slave CPUs and the like.

[0154]

According to the first aspect of the present invention, normally,
The switch control means does not connect a plurality of buses to the switch means, and the intra-bus access control means connected to each bus independently and in parallel performs bus access control closed in its own bus. be able to. As a result, the throughput of the entire device can be improved.

According to the second aspect of the present invention, the first bus such as a general-purpose CPU having no other bus access function is provided.
Is connected to the second bus, and the second bus master means having the other bus access function is connected to the second bus, the first and second buses normally connected to the first and second buses, respectively. Similarly to the case of the first aspect of the present invention, the second bus master unit can perform the bus access control closed in its own bus independently and concurrently, and at the same time, the first bus and the second bus master unit. Mutual access to the bus is possible. As a result, the throughput of the entire device can be improved.

According to the third aspect of the present invention, the first bus master means and the second bus master means such as a general-purpose CPU having no other bus access function are provided on both the first bus and the second bus. In the connected configuration, normally, the first and second bus master means connected to each of the first and second buses are closed in their own bus, as in the case of the first aspect of the present invention. The bus access control can be performed independently and in parallel, and mutual access between the first bus and the second bus is possible. As a result, the throughput of the entire device can be improved.

Here, after the bus which is the target of the bus access request is connected to another bus by the switch means, the device which is connected to the bus which is the target of the bus access request disappears on the bus. The processing for the control signal such as the address strobe signal can be performed based on another control signal such as the data strobe signal which has not disappeared on the bus.

Alternatively, when the switch control means is configured to reproduce the control signal such as the address strobe signal disappearing on the connected buses when connecting the two or more buses to the switch means. The device connected to the bus that is the target of the bus access request can process the address stove signal.

[Brief description of drawings]

FIG. 1 is a block diagram (1) of the present invention.

FIG. 2 is a block diagram (2) of the present invention.

FIG. 3 is a configuration diagram of a network to which the first embodiment of the present invention is applied.

FIG. 4 is a configuration diagram of a message communication device according to a first embodiment.

FIG. 5 is an explanatory diagram of message communication.

FIG. 6 is a diagram showing an example of a timing chart when a CPU accesses an external bus.

FIG. 7 is a processor bus interface having a CPU bus 2;
It is a figure showing an example of a timing chart when accessing 02.

FIG. 8 is a configuration diagram of a second embodiment.

[Explanation of symbols]

101, 201 first bus 102, 202 second bus 103, 203 switch means 104, 208 first bus master means 105, 204 first bus access request 106 bus release notification 107, 209 second bus access request 108 213 second bus master means 109 inter-bus access control means 205 first bus release notification 206 second bus access stop signal 207 second bus access retry signal 210 second bus release notification 211 first bus access stop Signal 212 First bus access retry signal 214 Second bus access request withdrawal signal 215 First inter-bus access control means 216 First bus access request withdrawal signal 217 Second inter-bus access control means 218 Inter-bus access competition Mediation means

Claims (8)

[Claims] 1. A switch means for selectively connecting a plurality of buses, an intra-bus access control means provided for each of the buses and for performing bus access control closed in its own bus, and each of the buses. And bus access request output means for outputting a bus access request of the other bus to another bus other than the own bus, and the bus access other than the own bus provided corresponding to each bus. An inter-bus access control means for controlling the bus access of the own bus in response to a bus access request of the own bus from the request output means; A bus coupling method comprising: a switch control unit for connecting buses to each other. 2. A device connected to the bus that is the target of the bus access request after the bus that is the target of the bus access request is connected to another bus by the switch unit, 2. The bus coupling method according to claim 1, wherein the processing for the control signal that has disappeared on the bus is performed based on another control signal that has not disappeared on the bus. 3. The switch control means, when connecting the two or more buses to the switch means, reproduces a control signal disappearing on the connected buses. The bus coupling method according to claim 1, wherein 4. First and second buses (101, 102)
Switch means (103) for selectively connecting the first bus (101) and the first bus (101) when not connected to the first bus (101).
01) and the first bus (10
In response to the first bus access request (105) from the outside when not accessing the first bus (1), the first bus (1
01) to output the first bus release notification (106) to the outside, and the first bus (101) from the outside.
When the access to the first bus (10
1) A first bus master unit (104) having a function of securing the second bus (102) and the second bus master unit (104) connected to the second bus (102) when the second bus (102) is not opened. Bus (1
02) and the second bus (10
In response to the second bus access request (107) from the outside when the second bus (1) is not accessed, the second bus (1
02), a function of reserving the second bus (102) when an external access to the second bus (102) is completed, and a function of the second bus (10).
And a function of connecting the first bus (101) and the second bus (102) to the switch means (103) when the second bus master means (10) is opened.
4) a function of causing the switch means (103) to disconnect the first bus (101) and the second bus (102) when the access to the second bus (102) is completed, When an address for accessing the first bus (101) is to be designated to the second bus (102) and the second bus access request (107) from the outside is not input. And a function of outputting the first bus access request (105) to the first bus master means (104), and then the first bus release notification (106) from the first bus master means (104). And a function of connecting the first bus (101) and the second bus (102) to the switch means (103), and then an address for accessing the first bus (101). To the second bus (102) and disconnecting the first bus (101) and the second bus (102) to the switch means (103) when the access is completed. A second bus master unit (108) having a function of causing the first bus master unit (104) to access an address for accessing the second bus (102). The second bus master means (108) when specified for the first bus (101)
And a bus access control means (109) having a function of outputting the second bus access request (107). 5. First and second buses (201, 202)
A switch means (203) for selectively connecting the first bus (201) and the first bus (201) when not connected to the first bus (201).
01) and the first bus (20)
1) is not accessed, the first bus (20) is received in response to the first bus access request (204) from the outside.
1) to release the first bus release notification (205) to the outside, and the first bus (201) when the access to the first bus (201) from the outside is completed.
And a function of stopping access to the second bus (202) via the first bus (201) in response to an external second bus access stop signal (206). In response to a function of releasing the first bus (201) after the suspension and notifying the first bus release notification (205) to the outside, and a second bus access retry signal (207) from the outside after the suspension. First bus master means (208) having a function of resuming access to the second bus (202) via the suspended first bus (201), and the second bus (202) ) Is connected to the second bus (202) and the second bus (202) is not opened.
02) and the second bus (20
2) When the second bus access request (209) from outside is not accessed, the second bus (20
2) to release the second bus release notification (210) to the outside, and the second bus (202) when the external access to the second bus (202) is completed.
And a function of canceling access to the first bus (201) via the second bus (202) in response to an external first bus access stop signal (211). In response to a function of releasing the second bus (202) and outputting the second bus release notification (210) to the outside after the stop, and a first bus access retry signal (212) from the outside after the stop. Second bus master means (213) having a function of resuming access to the first bus (201) via the suspended second bus (202), and the first bus master means ( If the second bus master means (213) designates an address for accessing the second bus (202) to the first bus (201), the second bus access request (20)
9) and a second bus access stop signal (206) to the first bus master means (208) in response to a second bus access request withdrawal signal (214) from the outside. The function of withdrawing the second bus access request (209), and the first bus release notification (20) from the first bus master means (208).
5) the function of connecting the first bus (201) and the second bus (202) to the switch means (203), and the first bus () by the second bus master means (213). 201) to the switch means (203) when the access to the first bus (201) is completed.
And the function of disconnecting the second bus (202) from each other, and the access to the first bus (201) by the second bus master means (213) after the output of the second bus access stop signal (206). First inter-bus access control means (215) having a function of outputting the second bus access retry signal (207) to the first bus master means (208) when completed, and the second bus master When the means (213) designates an address for accessing the first bus (201) to the second bus (202), the first bus access request ( 20
4) and the function of outputting the first bus access stop signal (211) to the second bus master means (213) in response to an external first bus access request withdrawal signal (216). The function of withdrawing the first bus access request (204) and the second bus release notification (21) from the second bus master means (213).
0), the function to connect the first bus (201) and the second bus (202) to the switch means (203), and the second bus (208) by the first bus master means (208). When the access to the first bus (201) is completed, the switch means (203) is connected to the first bus (201).
And a function of disconnecting the second bus (202) from each other, and an access to the second bus (202) by the first bus master unit (208) after the output of the first bus access stop signal (211). Second inter-bus access control means (217) having a function of outputting the first bus access retry signal (212) to the second bus master means (213) when completed, and the first bus The second bus access request (209) is output from the inter-bus access control means (215), and the first bus access control means (217) outputs the first bus access request (209).
When the first bus access request (204) is prioritized when the second bus access request (204) is output, the second inter-bus access control means (217)
A function of outputting the first bus access request cancellation signal (216) to the second bus access request (20)
9), the inter-bus access contention arbitration means (218) having a function of outputting the second bus access request cancellation signal (214) to the first inter-bus access control means (215). The bus connection system according to claim 2, wherein the bus connection system is a bus connection system. 6. When other bus master means other than the first bus master is connected to the first bus, the first bus master means and the other bus master means connected to the first bus When the first intra-bus access contention arbitration means for arbitrating contention with the bus master means and the other bus master means other than the second bus master are connected to the second bus, the second And a second intra-bus access contention arbitration means for arbitrating a contention between the bus master means and the other bus master means connected to the second bus. Or the bus coupling method according to any one of 5 above. 7. The first or second bus, which is the target of the first or second bus access request, is connected to another second or first bus by the switch means, and then, The device connected to the first or second bus that is the target of the first or second bus access request is the first
7. The processing for a control signal that has disappeared on the second bus is performed based on another control signal that has not disappeared on the first or second bus. The bus coupling method according to item 1. 8. The switch control means, when connecting the two or more first and second buses to the switch means, disappears on the connected first and second buses. 7. The bus coupling method according to claim 4, wherein the control signal is reproduced.