JPS58220542A - Data communication interface circuit - Google Patents

Abstract

PURPOSE:To reduce an overhead of a software, and also to decrease a hardware quantity, by storing in common a work area of a logical operation and transmitting and receiving data in a data storing circuit, using the data storing circuit as a buffer area of the transmitting and receiving data by executing the control of a controlling circuit, and executing the data communication. CONSTITUTION:In case when a transmitting request from a host computer (hereinafter called a host) connected through buses (an address bus 19, a data bus 20, I/OW' and I/OR'), and a receiving data from a circuit do not exist, a processor 11 waits for them, executing an instruction which is not referred to an RAM (random access memory) in a data storing circuit 16. When the transmitting request exists, a transmitting data is written to the data storing circuit 16 from the host side by use of the address bus 19, the data bus 20 and the I/OW', and after it ends, its fact is informed to the processor 11 by some means (for instance, interruption, etc.) from the host side.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data communication interface circuit connected to a computer bus in data communication using a computer.

First of the conventionally known data communication interface circuits
As an example, a case will be described in which the device is composed of a communication interface integrated circuit that is directly connected to a computer path, and some additional circuits.

In the transmission operation, parallel data equal to the word length of the computer (8 bits or 16 bits, etc.) is sent to the communication interface integrated circuit, and after parallel to serial conversion, a synchronization code etc. is added and sent out at the transmission speed of the line. . On the other hand, in the receiving operation, an operation opposite to the transmitting operation is performed. In this data communication interface circuit, data on the line is accessed from the computer in units of computer word length, and each time it must be input/output to the computer using interrupts, etc., there is a large amount of overhead when executing software control. It had the following drawback.

Further, a second example of a conventionally known data communication interface circuit is shown in FIG. This interface circuit has a processor l therein, and executes a transmission control procedure based on a control program in a fixed storage circuit 2. Therefore, the bus (
address bus 91 data bus 10, 170Vf',
Data transmission and reception between the host computer and the line connected via 110R') is not based on the word length of the host computer as in the first example, but on the text (character string) level based on the transmission control procedure. It will be held in Therefore, the first
It is possible to reduce the software overhead as in the example shown in FIG. However, in half-duplex operation, no further text can be sent until a response to the text is received. Therefore, when transmitting, the host side sequentially writes transmission data into the buffer memory 6, and after completion, the processor 1 sequentially reads data from the buffer memory 6 and sends it to the line, and when receiving, the processor 1 writes the received data from the line into the buffer memory 6. In such an operation in which data is written to the memory 6 and the contents of the front buffer memory 6 are read from the host side after the received data is completed, access from the host side and access from the processor 1 do not occur at the same time.

Therefore, the buffer memory 6 can be constructed by simply switching the addresses and pledge pulses of the host and processor 1.

However, in the example shown in FIG.
In addition to the buffer memory 6, it had two data storage circuits.

An object of the present invention is to reduce the software overhead in the first example, and further to combine two data storage circuits into one in the second example.

An object of the present invention is to provide a data communication interface circuit that can reduce the amount of hardware required.

Focusing on the fact that the data communication interface circuit of the present invention is half-duplex, the control program for the transmission control procedure is accommodated in a fixed redundant memory circuit, and the working area for logical operation and the transmitted and received data are shared in common. Recorded in memory episode wl''1
Under the control of the control circuit, data communication is performed using the data storage circuit as a buffer area for transmitted and received data.

Next, the present invention will be explained in detail. FIG. 2 is an embodiment of a data communication interface circuit according to the present invention. In FIG. 2, buses (address bus 19, data bus 20
, 110W', 110R') when there is no transmission request from the host computer (hereinafter referred to as host) or data received from the line.
Assume that the command is waiting for instructions that do not refer to the RAM (random access memory) in the data storage circuit 16 while executing them. When there is a transmission request, transmission data is written from the host side to the data storage circuit 16 using the address bus 19, data bus 20, and l10W', and after the writing is completed, the host side sends the transmission data by some means (such as an interrupt). 11 will be notified to that effect.

After this, in the data storage circuit 16, the access switching signal 18 is inverted by the processor 11 so that the processor 11 can access the data storage circuit 16.
6 and sends it to the line. At the time of reception, the operation described above can be performed in reverse, but if the host notifies the processor 11 using an interrupt or the like when the host has finished reading all the received data, the processor 11 will respond to the original request for transmission or waiting for the received data. It is possible to return to the current state.

In the above operation, a work area is required only when the processor 11 accesses the data storage circuit 16, that is, when transmitting and receiving data with the line, and does not require a work area at other times. Therefore, the transmit/receive data buffer (area) and work area can be realized by a common RAM (data storage circuit 16).

As is clear from the above description, the data communication interface circuit according to the present invention reduces the software overhead of the host compared to the conventional circuit configuration, and also reduces the FLA.
By having M in common, it is possible to reduce the amount of hardware.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a conventional data communication interface circuit, and FIG. 2 is a block diagram showing another embodiment of the data communication interface circuit according to the present invention. 1... Processor (control circuit), 2...
Fixed memory circuit, 3... Working area memory circuit, 4
...Communication interface, 5...Access selection circuit, 6...Buffer memory, 7...
...Bidirectional buffer, 8...Access switching signal, 9...Address bus (host), 10.
... Data bus (host), 11 ... Processor (control circuit), 12 ... Fixed memory circuit. 14... Communication interface, 15...
・Access selection circuit, 16... Data storage circuit, 17... Bidirectional buffer% 18...
・Access switching signal, 19...address bus (
host), 20...data bus (host).

Claims (1)

[Claims] In half-duplex data communication in which transmission and reception are not performed simultaneously, a fixed storage circuit stores a control program for a transmission control procedure, a control circuit controls and executes a logical operation based on the control program, and a logical operation is performed. 1. A data communication interface circuit comprising an area and a data storage circuit that commonly stores transmitted and received data, and performs data communication using the data storage circuit as a buffer area for transmitted and received data.