JPS5836380B2 - Direct memory access method in multiprocessor systems - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a direct memory access method between a processor-compatible memory and an external input/output device in a multiprocessor system having a processor-compatible memory and a memory common to the processors. .

A conventional direct memory access method between a processor-compatible memory and an external input/output device in this type of multiprocessor system will be described below.

That is, FIG. 1 shows an example of a multiprocessor system consisting of a plurality of (n+1) processors.

In the figure, 3 is a plurality of processors having the same hardware configuration, 1 is a unique memory corresponding to each processor 3, 2 is a memory bus of the memory 1, 4 is a common bus to which each processor 3 is connected, 5 is a common memory shared by each processor 3, 6 is a data channel connected to the common bus 4,
7 is an input/output control unit, and 8 is an input/output device.

In a conventional multiprocessor system having the above configuration, the only memory to which the data channel 6 can directly access the memory is the common memory 5, and the conventional unique memory 1 can access data by direct memory access. Not used for transfer.

Therefore, when data is transferred between the input/output device 8 and the memory 1 via the data channel 6, data is input/output by the processor 3 via the common memory 5 according to the procedure shown in FIG. That's what I was doing.

That is, FIG. 2 shows an example of a sequence when data is transferred from the data channel 6 to the memory 1.

Now, after the data channel 6 sends the memory request signal 9 to the common memory 5, when it receives the memory request enable signal 10 from the common memory 5, the data channel 6 sends the data 11 to the common memory 5 by direct memory access. The data is transferred to the common memory 5.

After this data transfer is completed, the data channel 6 sends an interrupt request signal 12 to the preselected processor 3. In response, that processor 3 sends an interrupt enable/interrupt data request signal 13 to the data channel 6. If you send it to
Processor 3 receives interrupt data 1 from data channel 6
It is designed to read 4.

As a result, the processor 3 can know by analyzing the interrupt data 14 that m words of data from address a in the common memory 5 should be sequentially transferred and stored from address b onward in the memory 1.

After this, the processor 3 sends a memory request signal 9 to the common memory 5.
However, if a memory request enable signal 10 is received from the common memory 5, data is sequentially read from the common memory 5 word by word under program transfer control and transferred to the memory 1 for storage. It is something.

As described above, in the conventional multiprocessor system, when data is transferred between the memory 1 and the external input/output device 8 via the data channel 6, etc., the common memory 5 and the processor 3 are interposed. As a result, the reality is that it is undeniable that the processing power of the processor will decline rapidly.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a direct memory processor in a multiprocessor system in which data can be transferred between an external input/output device and a private memory without reducing the processing power of the processor.
Provides an access method.

In order to achieve the above object, the present invention is capable of controlling the transfer direction of a private memory bus and a common bus so that an external input/output device can transfer data between the private memory and the private memory by direct memory access. The device is connected by a bus connection section as a switch, and data can be transferred directly to and from the dedicated memory without going through the processor and the common memory.

The present invention will be specifically explained below with reference to FIGS. 3 to 5.

FIG. 3 shows a multiprocessor system according to the present invention with two processors.

In FIG. 3, parts that are the same as those shown in FIG. bus connection section 15 as a switch whose transfer direction can be controlled;
is provided for the processor 3.

FIG. 4 shows the specific configuration of the bus connection section 15.

In the figure, 16 is a tri-state buffer, 17 is a specific memory request enable signal, 18 is a transfer end signal, and 19 is a common bus 4.
20 is an enable signal for the tri-state buffer 16, and 27 is a connection control flip-flop.

In a multiprocessor system having such a structure, the data transfer sequence from the data channel 6 to the memory 1 will be explained below with reference to FIG.

That is, if the interrupt request signal 12 is sent to the processor 3 for which the data channel 6 is selected, the interrupt request enable signal 21 and the direct memory access information 22 will be sent to the processor 3 if interrupts are enabled. More data channel 6
It will be sent to

From the direct memory access information 22, the processor that has accepted the interrupt as well as the memory address at which access starts in the private memory can be known through the data channel 6.

Therefore, the data channel 6 sends the common bus access request signal 23 according to the direct memory access information 22, and then receives the common bus access enable signal 24 from the processor 3. This is where the memory request signal 25 is sent to.

On the other hand, when the memory request signal 26 is sent from the memory 1, the tri-state buffer of the bus connection section 15 is enabled by the bus switching signal 19 and the memory request enable signal 26, and the common bus 4 and the memory bus 2 are connected to each other. It is something that is connected.

That is, the data channel 6 can perform data transfer by direct memory access as if the memory 1 were connected to the common bus 4 while controlling bus switching.

As is clear from the above, the present invention enables data transfer between a memory and an external input/output device through direct memory access.

This enables direct memory access between external input/output devices and memory, which was not possible in conventional multiprocessor systems, resulting in a reduction in the processing time required for data transfer between each processor. Therefore, the processing capacity of the multiprocessor system can be improved.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing a conventional multiprocessor system, Fig. 2 is a data transfer control sequence diagram in the above system, and Fig. 3 is an example of the multiprocessor system according to the present invention. 4 is a detailed circuit diagram of the bus connection section shown in FIG. 3, and FIG. 5 is a data transfer control sequence diagram according to the present invention. 1...Memory, 2...Memory bus, 3
...Processor, 4...Common bus, 5
... Common memory, 6 ... Data channel 15 ... Bus connection.

Claims (1)

[Claims] 1 Direct memory between external input/output devices and private memories in a multiprocessor system in which a plurality of processors, each having its own memory, are connected to and accommodate processor common memory and external input/output devices via a common bus.
As an access method, when a data input/output transfer request occurs between an external input/output device and a specific memory, an interrupt is sent to the processor selected by the device, and the processor accepts the interrupt. In this case, the memory designation is notified to the external input/output device, and from then on, the device is provided to correspond to the processor and is provided between the common bus and the specific memory and is capable of controlling the transfer direction. Direct memory access in a multiprocessor system characterized by direct memory access to transfer input/output data to and from a specific memory specified by interrupt processing independently of the processor via a bus connection section as a switch. Memory access method.