JP2821176B2 - Information processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, and in particular, to an arithmetic processing device (Ex
ecution Processing Unit. The present invention relates to an information processing apparatus that performs data transfer between EPUs.

[Conventional technology]

Conventionally, in this type of information processing apparatus, the following processing has been performed at the time of data transfer between EPUs.

(1) EPU previously allocated on main storage
The transfer source EPU (data transfer request source EPU) writes transfer data to the EPU table corresponding to the transfer destination EPU (data transfer partner EPU) in each table (EPU table).

(2) The transfer source EPU issues a write instruction to a fixed address (an address to which the main storage device does not respond) determined to be used only during data transfer between the EPUs by an interrupt set instruction (when the transfer source EPU is the transfer destination EPU Is issued as an interrupt instruction indicating that data transfer is to be performed by specifying an EPU number or the like.

(3) Bus interface device (Bus Interface Un
it. Upon receiving this interrupt set instruction, the BIS returns a response signal instead of a response signal from the main storage device for a normal memory access, terminates the bus sequence, and at the same time, based on the above-described interrupt set instruction. Issues an interrupt signal to the transfer destination EPU.

(4) Upon receiving the interrupt signal, the transfer destination EPU reads the transfer data from its own EPU table in the main storage device.

(5) For the purpose of checking the interrupt signal, the transfer destination EPU issues a write instruction to a fixed address similar to the interrupt set instruction by an interrupt reset instruction (the transfer destination EPU identifies itself by the PEU number or the like and transfers the data. (Interrupt instruction indicating that the data has been received).

(6) Upon receiving this interrupt reset instruction, the BIU resets the interrupt signal output to the transfer destination EPU.

[Problems to be solved by the invention]

In the above-described conventional information processing apparatus, the above-described processes (1) to (6) are performed at the time of data transfer between EPUs, and thus have the following disadvantages.

(1) Six phases for data transfer between EPUs ((1) above)
(Each phase of (6)).

(2) Due to the fact that the interrupt set instruction and the interrupt reset instruction are realized by a write instruction to a fixed address, a plurality of local buses (usually main memory) are used for transmitting the interrupt set instruction and the interrupt reset instruction. Only one of the local buses of the even address block local bus and the odd address block local bus corresponding to the even / odd address of the device is used.

(3) Due to the drawback shown in (2), the information processing device becomes 2
If it is composed of more than one set of EPUs (two EPUs),
When one set of EPUs is performing data transfer, other EPUs cannot perform data transfer.

In view of the above, an object of the present invention is to provide an information processing apparatus which eliminates the need for data transfer between EPUs via a main storage device and enables data transfer between EPUs in the following four-phase process. Is to provide.

(1) The transfer source EPU issues an interrupt set instruction to the transfer destination EPU, and subsequently outputs transfer data.

(2) After receiving the interrupt set instruction, the BIU
, And subsequently receives and holds the transfer data.

(3) Upon receiving the interrupt signal, the transfer destination EPU issues an interrupt reset instruction and performs transfer data read processing.

(4) At the same time as the phase (3), the BIU receiving the interrupt reset instruction resets the interrupt signal output to the transfer destination EPU, and outputs the transfer data held in the phase (2).

[Means for solving the problem]

An information processing apparatus according to the present invention includes a main storage device divided into a plurality of blocks, a plurality of local buses provided for each block of the main storage device, a BIU for controlling an interface between a system bus and a local bus, and a plurality of BIUs. In an information processing device having an EPU, an interrupt set instruction for specifying a destination EPU is issued using a local bus defined based on the EPU number of the destination EPU and the like, and subsequently, the same local bus is used. A transfer unit in the transfer source EPU for transferring transfer data, and a BIU that issues an interrupt signal based on an interrupt set instruction issued by the transfer unit to the transfer destination EPU using an interrupt signal line independent of the local bus.
, Read means in the destination EPU for reading transfer data from a local bus defined based on the EPU number of the transfer destination EPU based on an interrupt signal from the interrupt means, and issuance by the transfer means. The EPU number of the transfer difference EPU holds the transfer data transferred from the transfer unit based on the received interrupt set instruction and holds the transfer data held based on the reception of the interrupt reset instruction issued by the reading unit. And a holding output means in the BIU for outputting to a local bus defined based on the above.

[Action]

In the information processing apparatus of the present invention, the transfer means in the transfer source EPU issues an interrupt set instruction for specifying the transfer destination EPU using a local bus defined based on the EPU number or the like of the transfer destination EPU, and subsequently, The transfer data is transferred using the same local bus, and the interrupt means in the BIU uses an interrupt signal line independent of the local bus.An interrupt signal based on the interrupt set instruction issued by the transfer means to the destination EPU And the reading means in the transfer destination EPU issues an interrupt reset instruction based on the interrupt signal from the interrupt means, and then reads the transfer data from the local bus specified based on the EPU number of the transfer destination EPU, etc. The holding output means in the BIU holds the transfer data transferred from the transfer means based on the reception of the interrupt set instruction issued by the transfer means and issues the data by the reading means. And the output to the local bus defined based transfer data that is stored in EPU number of the destination EPU based on the reception of an interrupt reset command was.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the information processing apparatus of the present invention. The information processing apparatus according to the present embodiment includes an even address block local bus 1 (main storage device (not shown)).
Above, a local bus connected to an even-numbered address block), an odd-addressed block local bus 2 (a local bus connected to an odd-addressed block on the main memory), and EPUs 3, 4, 6, and 7 (the number of EPUs constituting the information processing apparatus of the present embodiment is such that the EPU number is "0" to "3"
It is assumed that it is within 4. Here, the EPU number is “0”,
EPUs of "1", "2" and "3" are EPU3,4,6 respectively
And BIU5 (between the even-numbered block local bus 1 and the odd-numbered block local bus 2) and the system bus (not shown; a plurality of peripheral controllers (not shown) are connected). Governs the interface of
BIU), an interrupt set signal line 8 (an interrupt set signal line between BIU5 and EPU3), and an interrupt set signal line 9 (BIU5
An interrupt set signal line between the CPU and the EPU4), an interrupt set signal line 10 (an interrupt set signal line between the BIU5 and the EPU6),
Interrupt set signal lines 11 (interrupt set signal lines between BIU5 and EPU7) (interrupt set signal lines 8 to 11 are independent of even address block local bus 1 and odd address block local bus 2). It is a single wire that was used.)

EPUs 3, 4, 6 and 7 are EPUs 3, 4, 6 and 7
And the EPUs 3, 4, 6 and 7
And a reading means 13 that functions when is the transfer destination EPU.

The BIU 5 includes interrupt means 14 and holding output means 15.

Referring to FIG. 2, the BIU 5 is connected to the even address block local bus 1, the odd address block local bus 2, and the interrupt set signal lines 8 to 11, and the even address block local bus 1 and the odd address block local bus 2 For each of the command holding register 21,
Command decode circuit 22 and transfer data holding register 23
And interrupt signal generating flip-flops 24, 2 corresponding to EPUs 3, 4, 6, and 7 (interrupt set signal lines 8, 9, 10, and 11).
(Interrupt means 14 is realized by command holding register 21, command decoding circuit 22, and interrupt signal generation flip-flops 24-27, and command holding register 21, command decoding circuit 2
2 and the transfer data holding register 23 hold and output means 1
5 is realized).

Referring to FIG. 3, the bus interface unit (portion relating to the bus interface) in the EPU 3, 4, 6, or 7 is
It is connected to the even-numbered block local bus 1, the odd-numbered block local bus 2, and the interrupt set signal lines 8, 9, 10, or 11, and has an odd / even address block local bus switching control circuit 31, an output address register 32, The output data register 33, the input data register 34, and the interrupt control circuit 35 are included. (The transfer means 12 is controlled by the odd / even address block local bus switching control circuit 31, the output address register 32 and the output data register 33.
Is realized, and the reading means 13 is realized by the odd / even address block local bus switching control circuit 31, the output address register 32, the input data register 34, and the interrupt control circuit 35).

Next, the operation of the information processing of the present embodiment thus configured will be described. Here, an operation in a case where data transfer is performed from EPU3 (EPU having an EPU number of “0”) to EPU6 (EPU having an EPU number of “2”) will be described.

 EPU3, which is the transfer source EPU, performs the following processing.

First, the odd / even address block local bus switching control circuit 31 determines whether the EPU number of the EPU 6 as the transfer destination EPU is an even number (including 0) or an odd number by referring to the output address register 32. Using the corresponding local bus (if the EPU number of the destination EPU is even, it is the even-numbered block local bus 1; if the EPU number of the destination EPU is odd, it is the fractional address block local bus 2) Outputs the interrupt set instruction set in the output address register 32 (in this case, the EPU of the transfer destination EPU
Since the PU number is "2", the even-numbered block local bus 1 is used.)

Subsequently, the transfer data set in the output data register 33 is output to the same local bus (in this case, the even address block local bus 1) as the local bus from which the interrupt set instruction was output.

On the basis of the output of the interrupt set instruction and the transfer data from the EPU 3, the BIU 5 performs the following processing.

First, the command input to the command holding register 21 (BIU5 always receives the commands on the even-numbered block local bus 1 and the odd-numbered block local bus 2 in the command holding register 21) is used as the command decoding circuit.
Decrypt at 22.

The instruction input to the command holding register 21 in this decoding (in this case, the command holding register 21 on the even address block local bus 1 side. The same applies to each component in the BIU 5 in the following description) Since the EPU3 determines that the instruction is an interrupt set instruction, the command decode circuit 22 outputs an enable signal to the transfer data holding register 23, and the transfer data output from the EPU3 to the even address block local bus 1 following the interrupt set instruction. Is held in the transfer data register 23.

At the same time, an interrupt signal generation flip-flop (in this case, the interrupt signal generation flip-flop 26 corresponds) corresponding to the transfer destination EPU (EPU6) indicated in the interrupt set instruction decoded by the command decode circuit 22 is set. I do.

Next, the interrupt set signal line 10 is activated by the output of the interrupt signal generating flip-flop 26, and the EPU 6 receives an interrupt signal that does not exist (independent) on the even address block local bus 1 and the odd address block local bus 23. Issue.

Based on this interrupt signal, the EPU 6 that is the transfer destination EPU performs the following processing.

First, this interrupt signal is sent to the EP by the interrupt control circuit 35.
Judge as an interrupt signal indicating data transfer between U, and set an interrupt reset instruction in the output address register 32 (a part (not shown in FIG. 3) other than the bus interface part in the interrupt control circuit 35EPU6) Set an interrupt reset instruction in the output address register 32 via the CPU).

When this interrupt reset instruction is output to the even address block local bus 1 based on the determination of the odd / even address local bus switching control circuit 31 that the EPU number “2” of its own (EPU6) is even, BIU5 performs the following processing.

First, the command holding register 21 receives this interrupt reset command.

Command decode circuit for received interrupt reset instruction
At 22, the interrupt signal generating flip-flop 26 is reset based on the decoding, and at the same time, the transfer data held in the transfer data holding register 23 is output to the even address block local bus 1.

After setting the interrupt reset instruction in the output address register 32, the transfer destination EPU6 holds the transfer data output from the BIU5 to the even-numbered block local bus 1 in the input data register 34, as described above. And perform processing internally.

This completes the data transfer between EPU3 and EPU6.

In this embodiment, the local bus is an even-numbered block local bus 1 and an odd-numbered block local bus 2
However, it is needless to say that the information processing apparatus of the present invention having three or more local buses can be realized.

〔The invention's effect〕

As described above, the present invention provides a transfer unit in a transfer source EPU, an interrupt unit in a BIU, a read unit in a transfer destination EPU, and a holding output unit in a BIU, so that data transfer between EPUs can be performed. There is no need to go through the main storage device, and the data transfer process can be shortened from six phases to four phases.
Data transfer can be performed simultaneously among a set of EPUs or more, and the data transfer between EPUs can be speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a BIU in FIG. 1, and FIG. 3 is a block diagram of a bus interface unit in an EPU in FIG. FIG. 3 is a block diagram illustrating a configuration. In the figure, 1 ... Even address block local bus, 2 ... Odd address block local bus, 3,4,6,7 ... EPU, 5 ... BIU, 8 to 11 ... Interrupt set signal line, 12 ... Transfer means, 13 readout means, 14 interrupt means, 15 holding output means, 21 command holding register, 22 command decode circuit, 23 transfer data holding registers, 24 to 27 interrupt Signal generation flip-flop, 31 ... Odd / even address block local bus switching control circuit, 32 ... Output address register, 33 ... Output data register, 34 ... Input data register, 35 ... Interrupt control circuit.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-238651 (JP, A) JP-A-55-37635 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 15/16

Claims (1)

(57) [Claims] A main storage device divided into a plurality of blocks;
In the information processing device having multiple local buses, BIUs that control the interface between the system bus and the local bus provided for each block of the main storage device, and multiple EPUs, the rules are based on the EPU number of the transfer destination EPU, etc. The transfer means in the source EPU that issues an interrupt set instruction that specifies the transfer destination EPU using the local bus to be transferred, and then transfers the transfer data using the same local bus, is independent of the local bus Transfer destination using the interrupt signal line
An interrupt means in the BIU that issues an interrupt signal to the EPU based on the interrupt set instruction issued by the transfer means; and issues an interrupt reset instruction based on the interrupt signal from the interrupt means, and subsequently transfers the transfer data. Destination EPU
Reading means in a transfer destination EPU to be read from a local bus defined based on the EPU number and the like, and holding transfer data transferred from the transfer means based on reception of an interrupt set instruction issued by the transfer means. The transfer data held based on the reception of the interrupt reset instruction issued by the reading means is transferred to the transfer destination EP.
And a holding and outputting means in the BIU for outputting to a local bus defined based on an EPU number of the U or the like.