JPH07121483A - Shared memory access control circuit - Google Patents

Abstract

PURPOSE:To prevent read data from being damaged at the time of executing word access to a shared memory by efficiently executing the mediation control of usage right to the shared memory. CONSTITUTION:CPU1 and 2 are operated by clocks whose phases are mutually deviated. An address decoding circuit 7 decodes address data from CPU 1 and 2 and outputs a chip select signal corresponding to the respective CPU 1 and 2 to a control circuit 6. The control circuit 6 outputs an under usage signal and a stand-by signal which are exclusive for CPU 1 and 2 based on the chip select signal from the address decoding circuit 7. Buffers 4 and 5 respond to the under usage signal from the control circuit 6 and execute open control an access line between CPU 1 and 2 and the shared memory 3 to a CPU 1 side or the CPU 2 side. CPU 1 and 2 respond to the stand-by signal from the control circuit 6 so as to be a stand-by state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared memory access control circuit, and more particularly to an arbitration function for a right to use a shared memory shared by a plurality of CPUs.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, arbitration of a shared memory usage right by a plurality of CPUs is performed by a CPU 1 to which asynchronous or synchronized in-phase clocks are supplied, respectively.
The control circuit 16 arbitrates that the access from the shared memory 13 to the shared memory 13 is not simultaneous.

The control circuit 16 includes a shared memory 13
A status flag (not shown) indicating the access status is provided, and the access status in the shared memory 13 can be known by this status flag.

When the CPUs 11 and 12 access the shared memory 13, the CPUs 11 and 12 output an access request in advance to the control circuit 16. Upon receiving the access request from the CPUs 11 and 12, the control circuit 16 rewrites the contents of the status flags corresponding to the CPUs 11 and 12 during the access unless the shared memory 13 is accessed by another CPU.

Each of the CPUs 11 and 12 confirms the content of the status flag of the control circuit 16, and if the content of the status flag corresponding to its own circuit is being accessed, the shared memory 13
To access. That is, permission of access to the shared memory 13 is controlled based on the content of the state flag so that the CPUs 11 and 12 do not access the shared memory 13 at the same timing.

Each of the CPUs 11 and 12 has a shared memory 1
3 is permitted, buffers 14 and 1 respectively
Access to the shared memory 13 is performed via 5.

[0007]

In the above-described conventional shared memory use right arbitration method, since the procedure for obtaining the use permission for the shared memory is complicated, the access time for accessing the shared memory is inefficient. There is a problem of becoming.

In addition, the CPU has a byte memory (8 addresses at each address).
When performing word access to (a memory that stores bit data), this byte memory must be accessed twice.

Therefore, while the byte memory is accessed twice, another CPU can access the byte memory, which causes the read word data timing before and after to be incorrect and the read data to be damaged. There is also.

Therefore, an object of the present invention is to solve the above problems, to efficiently control the arbitration of the usage right to the shared memory, and to ensure that the data read when the shared memory is word-accessed. It is an object to provide a shared memory access control circuit that can prevent the damage.

[0011]

A shared memory access control circuit according to the present invention includes information processing including a plurality of central processing units each having a different operation clock phase and a shared memory shared by the plurality of central processing units. A shared memory access control circuit for the apparatus, which decodes an access address from the plurality of central processing units to the shared memory and outputs a chip select signal corresponding to each of the plurality of central processing units; Means for selecting a central processing unit that permits access to the shared memory based on the chip select signal from the decoding means and a specific signal indicating that the shared memory is being used; and the sharing by outputting the specific signal. It is provided with a central processing unit that is permitted to access the memory and means for connecting the shared memory.

Another shared memory access control circuit according to the present invention comprises, in addition to the above configuration, means for outputting a standby signal to a central processing unit in which access to the shared memory is awaited.

[0013]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG.
Clocks that are 0 degrees (t / 4) out of phase are supplied, and the CPUs 1 and 2 operate according to the supplied clocks.

Therefore, the operation timings of the CPUs 1 and 2 are deviated by the amount of the phase shift of the clock.
A CPU whose memory read / write cycle ends in two states is used for each of the CPUs 1 and 2.

When the CPUs 1 and 2 access the shared memory 3, the address decoding circuit 7 decodes the address data 112 and 122 from the CPUs 1 and 2,
Chip select signals 171 and 17 corresponding to 1 and 2 respectively
2 is output to the control circuit 6.

Based on the chip select signals 171 and 172 from the address decoding circuit 7, the control circuit 6 outputs C
In-use signals (inverted signal of BUSY signal) 161, 162 dedicated to PU1, 2 and standby signals (inverted signal of READY signal) 163, 164 are output.

Busy signals 161, 162 are CPUs 1, 2.
Is a signal for switching the right of use when the shared memory 3 is accessed. By inputting to the buffers 4 and 5, the CPUs 1 and 2 and the shared memory 3 via the buffers 4 and 5
The access line between and is controlled to be open to the CPU1 side or the CPU2 side. This controls connection and disconnection between the CPUs 1 and 2 and the shared memory 3.

The standby signals 163 and 164 are control signals for causing the CPU that comes later to access the shared memory 3 when either of the CPUs 1 and 2 is accessing the shared memory 3, and are input to the CPUs 1 and 2. By doing so, the respective standby control is performed.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention. Arbitration control of the usage right in the access to the shared memory 3 by the CPUs 1 and 2 according to the embodiment of the present invention will be described with reference to FIGS. 1 and 2.

As described above, since the operation timings of the CPUs 1 and 2 are deviated by the deviation of the clock phase, the CPUs 1 and 2 do not operate at the same timing.

When the CPU 1 first accesses the shared memory 3, the CPU 1 outputs the address data 112 to the address decoding circuit 7. When the address decoding circuit 7 receives the address data 112 from the CPU 1, it receives a chip select signal 171 corresponding to the CPU 1.
Is output to the control circuit 6.

Chip select signal 1 corresponding to CPU 1
71 is normally kept at "High" level, but CP
While U1 is outputting the address data 112, "Lo
Fixed to w "level.

In the control circuit 6, the chip select signal 171 corresponding to the CPU 1 and the busy signal 16 on the CPU 2 side at the rising edge of T1 of the clock 111 on the CPU 1 side.
If both 2 are "Low" level, the busy signal 161 on the CPU1 side is set to "High" level.

That is, in the control circuit 6, the CPU
At the rise of T1 of the clock 162 on the first side, the states of the chip select signal 171 corresponding to the CPU1 and the busy signal 162 on the CPU2 side are confirmed.

At this time, since the chip select signal 171 corresponding to the CPU 1 and the busy signal 162 on the CPU 2 side are both at "Low" level, the control circuit 6 does not currently access the shared memory 3. Then, it is determined that the CPU 1 can access the shared memory 3, and the busy signal 161 on the CPU 1 side is set to the “High” level.

As a result, when the busy signal 161 on the CPU 1 side changes to "High" level in the buffer 4,
The access line of the shared memory 3 is controlled to be released to the CPU 1 side. Therefore, the CPU 1 can access the shared memory 3.

Next, when the CPU 2 accesses the shared memory 3 while the CPU 1 is accessing the shared memory 3, the CPU 2 outputs the address data 122 to the address decoding circuit 7. When the address decoding circuit 7 receives the address data 122 from the CPU 2,
The chip select signal 172 corresponding to PU2 is output to the control circuit 6.

Chip select signal 1 corresponding to CPU 2
72 is normally kept at "High" level, but CP
While U2 is outputting the address data 122, "Lo
Fixed to w "level.

In the control circuit 6, the chip select signal 172 corresponding to the CPU2 is at "Low" level at the rising of T1 of the clock 121 on the CPU2 side, and the CPU1
Since the busy signal 161 on the side is at the “High” level, the busy signal 162 on the CPU 2 side is kept at the “Low” level.

That is, in the control circuit 6, the CPU
At the rise of T1 of the clock 121 on the second side, the states of the chip select signal 172 corresponding to the CPU2 and the busy signal 161 on the CPU1 side are confirmed.

At this time, since the chip select signal 172 corresponding to the CPU2 is at the "Low" level and the busy signal 161 on the CPU1 side is at the "High" level, the CPU1 is currently in the shared memory 3 in the control circuit 6. It is being accessed, and it is determined that access from the CPU 2 is impossible, and a busy signal 162 on the CPU 2 side is determined.
Is kept at "Low" level.

Further, in the control circuit 6, at the falling edge of T1 of the clock 121 on the CPU2 side, the chip select signal 172 corresponding to the CPU2 is at "Low" level, and C
Since the busy signal 161 on the PU1 side is at the "High" level, the standby signal 164 on the CPU2 side is set to the "High" level.

That is, in the control circuit 6, the CPU
At the falling edge of T1 of the clock 121 on the second side, the states of the chip select signal 172 corresponding to the CPU2 and the busy signal 161 on the CPU1 side are confirmed.

At this time, since the chip select signal 172 corresponding to the CPU 2 is at the "Low" level and the busy signal 161 on the CPU 1 side is at the "High" level, the CPU 1 is currently in the shared memory 3 in the control circuit 6. The CPU 2 determines that the CPU 2 is in the process of accessing and is inaccessible from the CPU 2, and sets the standby signal 164 on the CPU 2 side to the “High” level. Standby signal 16 on the CPU2 side
4 becomes "High" level, so that CPU2
Enters the waiting state.

When the CPU 1 completes the access operation to the shared memory 3 in two states, it stops outputting the address data 112 to the address decoding circuit 7. When the address data 112 is no longer input from the CPU 1, the address decode circuit 7 sets the chip select signal 171 corresponding to the CPU 1 to the “High” level, and notifies the control circuit 6 that the access operation to the shared memory 3 by the CPU 1 is completed. To do.

In the control circuit 6, if the chip select signal 171 corresponding to the CPU1 is at the "High" level at the rising of the clock 111 on the CPU1 side, the CPU
The busy signal 161 on the first side is set to the “Low” level.

Therefore, when the busy signal 161 on the CPU 1 side changes to "Low" level, the buffer 4 stops the control of opening the access line of the shared memory 3 to the CPU 1 side. As a result, the CPU 1 cannot access the shared memory 3.

In this case, in the control circuit 6, the CPU
Since the busy signal 161 on the CPU1 side and the chip select signal 172 corresponding to the CPU2 are both at the "Low" level at the rise of the clock 121 on the second side, the busy signal 162 on the CPU2 side is set to the "High" level.

That is, in the control circuit 6, the CPU
At the rising edge of the clock 121 on the second side, the states of the busy signal 161 on the CPU1 side and the chip select signal 172 corresponding to the CPU2 are confirmed.

At this time, the busy signal 161 on the CPU 1 side
Also, the chip select signals 172 corresponding to the CPU 2 are both at "Low" level. Therefore, the control circuit 6 judges that there is no access to the shared memory 3 at present and the CPU 2 can access the shared memory 3, and the busy signal 16 on the CPU 2 side is determined.
2 is set to the "High" level.

As a result, in the buffer 5, when the busy signal 162 on the CPU 2 side changes to "High" level,
The access line of the shared memory 3 is controlled to be released to the CPU 2 side. Therefore, the CPU 2 can access the shared memory 3.

Further, in the control circuit 6, at the falling edge of the clock 121 on the CPU2 side, the busy signal 161 on the CPU1 side and the chip select signal 17 corresponding to the CPU2.
Since both 2 are at "Low" level, the standby signal 164 on the CPU2 side is set to "Low" level.

That is, in the control circuit 6, the CPU
At the falling edge of the clock 121 on the second side, the states of the busy signal 161 on the CPU1 side and the chip select signal 172 corresponding to the CPU2 are confirmed.

At this time, the busy signal 161 of the CPU 1 side
Since both the chip select signals 172 corresponding to the CPU 2 and the CPU 2 are at the “Low” level, it is determined that the control circuit 6 is not currently accessing the shared memory 3 and the CPU 2 can access the shared memory 3. Then, the standby signal 164 on the CPU 2 side is set to the "Low" level.

The standby signal 164 on the CPU 2 side is "Low"
When the level becomes the level, the standby state of the CPU 2 is released. The CPU 2 whose standby state has been released accesses the shared memory 3 via the buffer 5.

When the CPU 2 completes the access operation to the shared memory 3 in two states, it stops outputting the address data 122 to the address decoding circuit 7. When the address data 122 is no longer input from the CPU 2, the address decoding circuit 7 sets the chip select signal 172 corresponding to the CPU 2 to the “High” level, and notifies the control circuit 6 that the access operation to the shared memory 3 of the CPU 2 is completed. To do.

In the control circuit 6, if the chip select signal 172 corresponding to the CPU2 is at the "High" level at the rising edge of the clock 121 on the CPU2 side, the CPU
The busy signal 162 on the second side is set to the “Low” level.

Therefore, when the busy signal 162 on the CPU 2 side changes to "Low" level, the buffer 5 stops the control of opening the access line of the shared memory 3 to the CPU 2 side. As a result, the CPU 2 cannot access the shared memory 3.

As described above, the arbitration control of the usage right in the access to the shared memory 3 between the CPUs 1 and 2 eliminates the need for the complicated procedure which has been conventionally performed until the usage right of the shared memory 3 is acquired. The access time to the shared memory 3 can be shortened.

Further, when the shared memory 3 is a byte memory, even if one of the CPUs 1 and 2 makes a word access to the shared memory 3, the other one is executed until the operation of one of the CPUs 1 and 2 ends. Does not access the shared memory 3.

Therefore, the read word data timing before and after the word access is not disturbed, so that it is possible to prevent the read data from being damaged when the word access to the shared memory 3 is performed.

The above-described operation is performed by the shared memory 3 having two CPs.
The operation is in the case of being shared by U1 and U2, but even if the shared memory 3 is shared by three or more CPUs, if a buffer and signal lines corresponding to those CPUs are added,
The same operation as described above can be performed.

As described above, the shared memory 3 shared between the CPUs 1 and 2 to which the clocks having different phases are supplied.
The access addresses 112 and 122 to the CPU are decoded by the address decoding circuit 7 and the chip select signals 171 and 172 corresponding to the CPUs 1 and 2 are output. The chip select signals 171 and 172 and the use indicating that the shared memory 3 is in use are used. CPUs 1 and 2 that allow access to the shared memory 3 are selected based on the medium signals 161 and 162, the busy signals 161 and 162 are output, and C is set by the buffers 4 and 5.
By connecting the PU1 and PU2 with the shared memory 3,
The arbitration control of the usage right for the shared memory 3 can be efficiently performed, and the data read when the shared memory 3 is word-accessed can be prevented from being damaged.

[0055]

As described above, according to the present invention, an access address to a shared memory shared between a plurality of central processing units each having a different operation clock phase is decoded to decode each of the plurality of central processing units. Output a chip select signal corresponding to, and based on this chip select signal and a specific signal indicating that the shared memory is in use, select a central processing unit that permits access to the shared memory, and output this specific signal. By connecting the selected central processing unit and the shared memory, the arbitration control of the usage right for the shared memory can be efficiently performed, and the data read when the shared memory is word-accessed is damaged. There is an effect that it can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1, 2 CPU 3 Shared memory 4, 5 Buffer 6 Control circuit 7 Address decode circuit

Claims (3)

[Claims] 1. A shared memory access control circuit for an information processing apparatus, comprising: a plurality of central processing units each having a different operation clock phase; and a shared memory shared by the plurality of central processing units, Decoding means for decoding an access address from the central processing unit to the shared memory and outputting a chip select signal corresponding to each of the plurality of central processing units, and the chip select signal from the decoding means and use of the shared memory Means for selecting a central processing unit that permits access to the shared memory based on a specific signal indicating the inside; and the sharing with the central processing unit that outputs the specific signal and is permitted to access the shared memory A shared memory access control circuit having means for connecting to a memory. 2. The shared memory access control circuit according to claim 1, further comprising means for outputting a standby signal to a central processing unit in which access to the shared memory is kept waiting. 3. A means for connecting the shared memory to a central processing unit permitted to access the shared memory,
A plurality of buffers provided corresponding to each of the plurality of central processing units and for connecting the central processing unit and the shared memory, and outputting the specific signal, permitting access to the shared memory. 3. A means for controlling the plurality of buffers so as to connect the central processing unit and the shared memory to each other.
A shared memory access control circuit as described.