JPH0612313A - Memory device - Google Patents

Abstract

PURPOSE:To enable high-speed memory access without any sampling loss of a confliction circuit in a device made access from plural CPUs at the same time by providing a mode switch and a selector which output a CPU clock requesting memory access operation and the memory conflicting circuit operated based on the output clock. CONSTITUTION:When memory access by a 1st CPU takes place successively, a 1st selector 2, the mode switch 1, and a 2nd selector 3 hold the selection of the CPU and since an edge detecting circuit 4 does not change the output, a 3rd selector 6 outputs the output of the 1st selector 2. Therefore, when CPU1 REQ becomes active, the CPU1REQ is sampled from a 2nd latch 7 without passing through a 1st latch 5, so no sampling loss is generated. Such removal of the loss results from that a synchronous circuit can be omitted by one stage since the CPU1REQ is synchronized with the sampling clocks of the 1st and 2nd latches 5 and 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a workstation,
The present invention relates to a memory device used for desktop publishing, personal computers and the like.

[0002]

2. Description of the Related Art In recent years, as application software has become more sophisticated, the processing speed of workstations, desktop publishing (DTP), personal computers, etc., and the capacity of memory have been increasing. As memories, semiconductor memories, which are becoming faster and cheaper, are being used more and more. Generally, a memory accessed from a plurality of CPUs requires a competing circuit that arbitrates a memory access request from each CPU, and is driven by a clock that is asynchronous with the CPUs.

[0003]

However, in the conventional method, since the competing circuit is driven by the clocks asynchronous with all CPUs, sampling loss occurs at the time of memory access of each CPU, resulting in a decrease in access speed. Was there.

The present invention is intended to solve the above-mentioned problems. Each C
An object of the present invention is to provide a memory device in which a PU can access at high speed without sampling loss of a competitive circuit.

[0005]

In order to achieve the above object, the present invention provides a switch circuit for outputting a CPU operation clock during a memory access request, and a switch circuit output clock for a current clock during a non-memory access. It has a configuration including an access arbitration circuit between the CPUs that performs switching and operates as a reference clock.

[0006]

The present invention has a plurality of CPUs with the above-mentioned configuration.
In the memory device accessed by each CPU, each CPU acts to enable high-speed memory access without the sampling loss of the competing circuit.

[0007]

1 is a block diagram showing the structure of a memory device according to an embodiment of the present invention. In this embodiment, two CPUs will be described.

In FIG. 1, reference numeral 1 denotes a signal for selecting the CPU 1 (high output) each time a rising edge of the memory access request (active high) of the CPU 1 is detected, and a rising edge of the memory access request (active high) of the CPU 2. This is a mode switch that outputs (low output) a signal for selecting the CPU 2 each time an edge is detected. 2 is C when the output of the mode switch 1 is high
PU1 access request signal (CPU1REQ), when low, CPU2 access request signal (CPU2RE
It is a first selector that outputs Q). 3 indicates the CPU clock of the CPU 1 (CPU 1 clock) when the output of the mode switch 1 is high, and the CP of the CPU 2 when it is low.
It is a second selector that outputs the U clock (CPU 2 clock). 4 is selected by the mode switch 1 (C
When a rising edge of a CPU access request that is different from that when PU1 is selected is detected, high output is performed only during the current memory access request period, and a clear signal (rising or falling period) is output when this output signal changes (rising or falling period). This is an edge detection circuit that outputs a low pulse). 5 is the first
2 is a first latch for sampling the signal of the selector 2 of FIG. 1 by the output clock of the second selector 3. A third selector 6 selects and outputs the output of the first latch 5 when the select signal output from the edge detection circuit 4 is high, and outputs the output signal of the first selector 2 when the select signal is low. 7 is the third
2 is a second latch for sampling the output of the selector 6 of FIG. 1 with the clock of the output of the second selector 3. A memory controller 8 generates a memory access control signal from the output of the second latch 7. 9 is a memory controller 8
Is a memory array in which data is read and written in response to a memory access control signal from. Further, the first selector 2, the second selector 3, the mode switch 1, and the edge detection circuit 4 accept the memory access request from another CPU during the current memory access after the current access is completed. .

The operation of the memory device of this embodiment having the above components will be described below.

FIG. 2 is a timing chart when the access request of the CPU 1 is received after the memory access of the CPU 2 is completed, and FIG. 3 is a timing chart when the access requests of the CPU 1 are successively received after the memory access of the CPU 1 is completed. is there.

First, the case shown in FIG. 2 will be described.
When CPU1REQ in FIG. 1 goes high (21 in FIG. 2),
The output of the mode switch 1 changes from low to high. Then, the first selector 2 outputs the CPU1REQ signal to the first latch 5, and the second selector 3 outputs the CPU1 clock to the first latch 5 and the second latch 7. After detecting the rising edge of the CPU1REQ, the edge detection circuit 4 activates (clears) the clear signal until the CPU1 clock becomes low. When the CPU1 clock is low (22 in FIG. 2), the select signal becomes high, and C
Holds high until PU1REQ goes inactive (low). The memory controller 8 receives the output of the second latch 7, outputs a memory access control signal to the memory array in the subsequent stage, and memory access is performed. As described above, when a memory access request of a CPU other than the currently selected CPU clock is generated, the access request is sampled by the first latch 5 and the second latch 7, and the loss is shown in FIG. First and second latches 5, 7
There is a delay in access time due to switching of sampling clocks. This is equivalent to sampling the access request signal with the asynchronous clock of the CPU.

However, as shown in FIG. 3, when the memory accesses of the CPU 1 occur continuously, the first selector 2, the mode switch 1 and the second selector 3 keep the selected state of the CPU 1. Since the edge detection circuit 4 does not change the output, the third selector 6 outputs the output of the first selector 2. Therefore, CPU1R
When EQ becomes active (31 in FIG. 3), CP
Since U1REQ is sampled from the second latch 7 without passing through the first latch 5, high-speed access is possible without the sampling loss shown by the loss in FIG. this is,
Sampling clocks for the first and second latches and the CPU 1
This is because one stage of the synchronizing circuit can be omitted because the REQs are synchronized (the first latch 5 in the example of FIG. 3).

As described above, according to this embodiment, the mode switch and the selector for outputting the CPU clock requesting the memory access operation and the memory competing circuit for operating on the basis of the output clock are provided. High-speed access can be achieved without circuit sampling loss.

In this embodiment, the case where the number of CPUs is two is described. However, when the number of CPUs increases, the number of inputs of each selector, mode switch and edge detection circuit may be expanded by the increased number. .

[0015]

As is apparent from the above embodiments, according to the present invention, the switch circuit for outputting the CPU operation clock during the memory access request and the switch circuit output clock are switched to the current clock during the non-memory access. ,
Since an access arbitration circuit between each CPU that operates as a reference clock is provided, it is possible to provide a memory device that can be accessed at high speed without a sampling loss of a competing circuit in a memory device that is simultaneously accessed by a plurality of CPUs.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory device according to an embodiment of the present invention.

FIG. 2 shows the CPU1 after the CPU2 completes the memory access.
Timing chart when the access request of the

FIG. 3 is a timing chart when the access requests of the CPU 1 are continuously made after the memory access of the CPU 1 is completed.

[Explanation of symbols]

 1 Mode Switch 2 First Selector 3 Second Selector 4 Edge Detection Circuit 5 First Latch 6 Third Selector 7 Second Latch 8 Memory Controller

Claims (1)

[Claims] 1. In a memory device simultaneously accessed by a plurality of CPUs, a switch circuit for outputting a CPU operation clock for a memory access request, and a clock output from the switch circuit are switched to a current clock during a non-memory access. , A memory device having an access arbitration circuit between CPUs that operates as a reference clock.