JP3133696B2 - DRAM control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a DRAM, and more particularly, to a single access mode or a high speed page.
The present invention relates to a DRAM control circuit of an arithmetic device that accesses a DRAM that can take a mode using a CPU or an arithmetic module.

[0002] Here, a single access mode,
In other words, single read / write mode and high-speed page mode
Including

[0003]

2. Description of the Related Art A conventional DRAM control circuit of this type mainly has a role of adjusting a shift in access timing between a CPU and a DRAM and a plurality of DRAMs required from an arithmetic module.
RAM single access mode or high-speed page mode
It has a role to switch the mode.

[0004] For example, in FIG.
The CPU 31 and the arithmetic module 32 read data for performing the arithmetic processing from the DRAM 36, and after completing each arithmetic processing, write the data to the DRAM 36 again. The CPU 31 and the operation module 32
In order to smoothly communicate with AM36, DRA
There is an M control circuit A33 and a DRAM control circuit B34.

[0005] The DRAM control circuit A33 includes address data output from the CPU 31 and a read signal or a write signal.
When receiving the RAS / CAS signal, it converts the address data into a row / column address in accordance with the AC characteristics of the DRAM 36 and simultaneously outputs the RAS / CAS signal. Meanwhile, DRAM
The control circuit B34 performs row / column address conversion and RAS / CAS signal output in accordance with a single read / write mode or high-speed page mode request requested by the operation module 32. The selector 35 functions to switch the bus use right from the CPU 31 to the arithmetic module 32 when a bus request is issued from the CPU 31 and the arithmetic module 32.

The arithmetic module 32 is a dedicated device for performing a specific process, such as an image processing device. Therefore, a DRAM control circuit 34 for the operation module 32 is provided in addition to the DRAM control circuit 33 for the CPU 31 in order to take an operation mode different from that of the CPU 31.

[0007]

The above-mentioned conventional DRA
In the M control circuit, there is a first problem that the DRAM read / write timing of the CPU and the operation module cannot be synchronized, so that the DRAM control circuit cannot be shared by the CPU and the operation module. In order to achieve read / write timing matching, it is necessary to output a common synchronization signal from both the CPU and the operation module to the DRAM control circuit. However, signals that can be used as synchronization signals include address data signals and read signals.
Although Rui is either the write signal, address data signal output from the CPU, the read signal or a write signal
The signal may be asynchronous with respect to the clock or the enable time may fluctuate. In this case, the synchronization between the CPU and the arithmetic module cannot be obtained.
The PU and the arithmetic module had to have separate DRAM control circuits.

[0008] Further, the conventional DRAM control circuit operates in the DRAM single access mode or high- speed mode of the operation module.
It is necessary to match the request if Kaware request because it is made to fit the fast page mode request, DRAM single access mode or the high computing module
When the fast page mode is changed, there is a second problem that the DRAM control circuit must be changed.

[0009]

A DRAM control circuit according to the present invention comprises at least a CPU or an arithmetic module.
The timing and time width at which the read signal or write signal is enabled are detected, and the result is used to determine the DRAM thinning.
It is characterized in that a read / write timing is determined from a single access mode or a high speed page mode .

More specifically, the DRAM control circuit of the present invention performs row / column address switching and RAS / CAS output at the timing when a read signal or a write signal is enabled, and further outputs a read signal or a RAS signal.
Is DRAM single depending on the enable time of the write signal.
Access mode or high-speed page mode ,
It controls the switching of the column address and the number of times the CAS signal is output. To this end, the present invention provides an address decoding circuit for decoding address data, a CE signal and a read signal.
A timing detection circuit for detecting a timing and a time width when both the signal and the write signal are enabled by a CLK signal, a row / column address switching circuit for switching and outputting address data between a row address and a column address, and RAS / CAS in synchronization with the address switching A RAS / CAS output circuit for outputting a signal has a data latch circuit for latching read data when the CPU performs a DRAM read.

[0011]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a DRAM showing an embodiment of the present invention.
FIG. 2 shows a block diagram of a control circuit. The present DRAM control circuit 1
Is connected to a CPU and an operation module (not shown) located on the left side of FIG.
A read signal or a synchronous signal between the RAM control circuits 1
Uses a write signal .

The timing detection circuit 3 has a read signal.
Alternatively, the period during which both the write signal and the CE signal decoded by the address decode circuit 2 are enabled is defined as CL.
Sampling is performed by the K signal, and the result is output as a sampling result. The row / column address switching circuit 4, the RAS / CAS output circuit 5, and the data latch circuit 6 execute predetermined operations only while the sampling result is enabled.

That is, the row / column address switching circuit 4 further samples the sampling result with CLK.
The row address is output during the disable period,
The column address is output only while the sampling result is enabled. The RAS / CAS output circuit 5 enables the RAS / CAS signal only while the sampling result is enabled. The data latch circuit 6 stops data latching in response to a bus ACK signal output by the CPU when a bus request by the arithmetic module is detected, thereby holding data only when the CPU reads DRAM data.

Next, the operation of the DRAM control circuit 1 of FIG. 1 will be described with reference to the time chart of FIG. The address decode circuit 2 decodes address data output from the CPU 31 or the operation module 32, and enables the CE signal when the address data is determined to be DRAM address data. The timing detection circuit 3 outputs the CE signal
The period during which both the read signal and the write signal are enabled is sampled by the CLK signal, and the result is output as a sampling result.

This sampling result has two meanings. One is row / column address switching and RAS
The output timing of the CAS signal can be known from the falling edge of the sampling result. The other is that the DRAM single access mode or the high-speed
Is to be able to know the page mode . For example, FIG. 2 shows the sampling result of the timing detection circuit 3 as CL.
K and sampled by the timing detection circuit 3
This is an example of a time chart of an operation in the case where the enable period of the pulling result is 2 CLK or more, the high-speed page mode is determined, and the column address switching and the output of the RAS / CAS signal are continuously performed.

However, a read signal or a write
For CPUs that output signals irregularly, this read
Not all problems can be solved by the method of detecting a signal or a write signal . The remaining task is CPU
May read indefinite data when reading DRAM. This problem is solved as follows by utilizing the characteristic that the CPU does not take the high-speed page mode.

That is, the read signal output from the CPU is
Alternatively, the enable width of the write signal is not limited to the time width of 3 CLK even in the single read mode. If there is more than 3 CLKs, the DRAM control circuit 1 may determine that it is in the high-speed page mode and output the CAS several times, but at this time, the column address changes since it is actually in the single read mode. No, the same data is read several times.
Although this is not a problem in itself, the timing at which the CPU reads data is the rising edge of the read signal on the data bus.
M cannot determine the data, and eventually the CPU may read indefinite data. So, CP
Only when the DRAM is read by U, the data latch circuit latches the data in response to the first rising edge of the CAS signal, thereby eliminating the possibility that the CPU reads indefinite data.

Meanwhile, Lee outputted from the arithmetic module
The enable width of the write signal or the write signal is constant, and the above-described problem in the CPU cannot occur.

In the above-described embodiment, the CPU
It is assumed that the read signal or write signal from the CPU is common to the signal for the DRAM and the signal for the input / output device.
No. A device such as that cut into the output device only the DRAM only has a timing detection circuit 3 Li
The sampling result can be generated only from the read signal or the write signal , and the read signal or the write signal does not need to be taken into consideration.

[0021]

The first effect of the present invention is that the difference between the read / write timing of the CPU and the operation module is removed.
Since the address switching and the RAS / CAS output timing are unified by sampling the load signal or the write signal , the operation device including the CPU and the operation module can reduce the number of DRAM control circuits conventionally required to one to one. As a result, the circuit size can be reduced, and this effect becomes more remarkable as the number of operation modules increases.

The second effect is that the dedicated signal is not used as the synchronization signal and that the read / write width varies.
In order to automatically recognize the single access mode or the high-speed page mode , addition and deletion of arithmetic modules and D
The DRAM control circuit is not affected by the change of the RAM read / write. As a result, complicated timing design and mode design related to DRAM read / write at the time of operation module design are released, and only read signal
It is only necessary to pay attention to the enable width of the signal or the write signal .

The third effect is that a read signal or
A data latch circuit is provided for a CPU that outputs a write signal irregularly, thereby eliminating instability when the CPU reads data from the DRAM.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing an example of the related art.

[Explanation of symbols]

 Reference Signs List 1 DRAM control circuit 2 Address decode circuit 3 Timing detection circuit 4 Row / column address switching circuit 5 RAS / CAS output circuit 6 Data latch circuit 31 CPU 32 Operation module 33 DRAM control circuit CPU 32 Operation module 33 DRAM control circuit A 34 DRAM control Circuit B 35 Selector 36 DRAM

Claims (4)

(57) [Claims] 1. At least a timing and a time width at which a read signal or a write signal from a CPU or an operation module is enabled are detected, and a DRA is determined from the result.
A DRAM control circuit for determining a read / write timing from an M single access mode or a high speed page mode . 2. The method according to claim 1, wherein a detection result of the address data from the CPU or the operation module and a read signal are detected.
2. The method according to claim 1, wherein the detection of the timing and the time width at which both the write signals are enabled are performed.
RAM control circuit. 3. The DR according to claim 1, wherein when the CPU which does not take the high-speed page mode reads the DRAM, the CPU holds read data from the DRAM at the first rising edge of the CAS enable.
AM control circuit. 4. The DRAM control circuit according to claim 3, wherein said holding is performed by a latch circuit.