JPS6168654A - Memory control method - Google Patents

Abstract

PURPOSE:To control the timing to access a memory device by providing a ROM activated by a control signal which accesses the memory device and by using output data of the ROM. CONSTITUTION:If, for example, required conditions are that RAI3-0 are '0' and SRVIN, RFRQ are '0', and when there is no request for access to a ROM31, an output of the ROM31 are not activated since RAS, CAS strobe signals remain '1'. Then, if an access request signal SRVIN is inputted as an address from CPU, RAI3-0 remain at '0000' but an RAS strobe signal is activated after 50ns and goes to '0'. At this moment, output signals RA3-0 which specify the next address of the ROM31 go to '0001' and become next address information. As a result, a CAS strobe signal is activated and goes to '0', and consequently RA3-0 output '0010'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a storage device, and particularly to a method for generating various control timing signals necessary for accessing a storage device.

With recent remarkable progress in semiconductor technology, storage devices are becoming larger in capacity and faster, and the control timing of the storage device is changed depending on the characteristics of the memory element used in the storage device. With the conventional timing control method using a delay line, it has become necessary to change the design of the timing control circuit as the characteristics of the memory element are improved. There is a growing need for a memory control method that can flexibly handle the increasing performance of memory devices.

In addition, if the memory element used in the storage device is a so-called dynamic RAM, a so-called refresh mechanism is used to charge the information storage mechanism of the memory element at a constant cycle before the electric charge stored in the information storage mechanism is completely discharged. However, this refresh method also comes in various forms, such as R
AS only refresh, CAS Before RA
S Refreshe, Hidden Refresh, etc. are known.

Therefore, for these various refresh methods,
Flexible refresh control method % Formula % Also, various types of storage devices are known, such as main storage, buffer storage, and address conversion buffer memory. A memory control method that can flexibly deal with control timing is desired.

Furthermore, the speed of the above-mentioned storage device has been increased as the speed of devices that access the storage device has become faster, but in addition to increasing the speed of the storage elements that make up the storage device, improvements in the control method have also been made. Ingenuity, for example page mode.

Various improvements have been made, such as nibble mode and static mode, and it is necessary to be able to flexibly handle these control modes.

On the other hand, read-only memory (ROM) can be used as needed.
Focusing on the fact that various data can be output at a certain timing by rewriting the contents, it is possible to output multiple control signals at the various timings as described above, and the control method is unique to the storage device. An application to memory control that changes depending on the type of memory can be considered.

[Prior Art] A central processing unit (hereinafter referred to as c) accesses a memory array using, for example, dynamic RAFI as a storage element.
In an information processing device equipped with a
FIG. 3 shows an example in which timing control for writing data from u to the memory array or reading data from the memory array is realized using a conventional method.
An example of the operation timing is shown in FIG.

In order to control the above dynamic RIV, ■RAS,
CAS timing control.

■Data output latch timing control from RAM.

■The upper address (RAS), lower address (CAS), and refresh address (RA
S) selection timing control.

is necessary.

First, CPU 1 sends a memory access request signal (SRV
I) is output, the flip-flop (PF) 70.
At 71, synchronization with the clock (CLK) is established;
The flip-flop (FF) 72 is activated and the 5RVIN signal is input to the timing control circuit (TCTL) 3.

In the above timing control circuit (TCTL) 3,
The 5RVIN signal generates strobe signals RAS and CAS as shown in the time chart of FIG. A signal LA is output.

Flip-Flo by RAS strobe signal.

UPPI (FF) 73 is activated at the falling edge of the clock (CIJ), and UPPI! Outputs the R signal and selects the upper address (RAS) of memory addresses AO to A15 A15 to A15.
88 and lower addresses (CAS) ^7 to ^0 are performed in the address switching unit 4, and the 8-bit address is transferred to the memory array (RAM) 2 from the above R.
It operates to input in the order of AS and CAS.

Further, the NAND circuit 81 is activated by the output latch timing (LA), and the flip-flop (FP) 72 is activated.
is reset, the 5RVIN signal is blocked, and the output of the memory array (RAM) 2 becomes a flip-flop due to this output latch timing (LA).

(FF), and a read output in response to a memory access request from the CPU 1 is taken out.

By the output signal of the NAND circuit 81, CPIJ 1
, a response signal for the memory access is sent back.

In this way, in the conventional system, the timing control circuit (TCTL) 3 responds to, for example, the memory access request rSRVIN signal from the CPU 1.
It generated various timing signals for accessing the memory array (RAM) 2.

In this example, since the memory array (RAM) 2 is composed of a dynamic RAM, the above-mentioned refresh operation is necessary. The flip-flop (FF) 74 is activated every time the refresh request signal RFRQ is generated and inputted to the timing control circuit (TCTL) 3.
In the same way as in the case of normal memory access, various timing signals (RFL) necessary for the refresh operation are
, RAS, LA) are generated, and a refresh operation is performed in the same way as a normal memory access.

The operation at this time is shown in a time chart as shown in Figure 4 (b).
become that way.

As is clear from FIG. 3, during the refresh operation, the RFL timing signal is activated.
The output of the NAND circuit 81 is °1", and CPt1
1, it functions to inhibit normal memory access.

[Problem that the invention seeks to solve]

In such conventional methods, the various timing signals mentioned above are processed by a timing control circuit (for example) using a delay line.
TCTL) 3, the memory array (R
Since the timing control circuit (TCTL) 3 is generated according to the characteristics of the timing control circuit (TCTL) 3, it is necessary to completely change the hardware of the timing control circuit (TCTL) 3 for memory arrays (RAM) with different access times. there were.

As mentioned above, it is necessary to configure a timing control circuit (TCTL) suitable for each control timing for the storage devices having various operation modes and five different functions.

In view of the above-mentioned conventional drawbacks, the present invention provides a read-only memory (
By focusing on the fact that the ROM (ROM) can retrieve various control signals at a timing that is an integral multiple of the access time of the memory, the above-mentioned control signals of the control unit of the storage device can be obtained by simply replacing the contents of the read-only memory (ROM). It is an object of the present invention to provide a method for easily generating control timing signals for various memory arrays without changing the peripheral hardware of the timing control circuit (TCTL) 3 at all.

[Means for solving problems]

This purpose is to provide a device that controls a storage device with a read-only memory (ROM) that is activated by a control signal that accesses the storage device;
This is achieved by the memory control method of the present invention, which performs various timing controls for accessing the storage device based on the output data of the OM).

[Effect]

That is, according to the present invention, read-only memory (ROM
) can retrieve various types of data at a fixed period (i.e., access time), and for example, when accessing the dynamic RAM 2 at a timing that is an integral multiple of the access time of the read-only memory (ROM). In order to access the dynamic RAM 2, ■RAS, CAS strobe timing signals ■I? Latch timing signal for extracting output data from AFI ■ Upper address of RAM address (RAS) and
Lower address (CAS) and refresh address (
In order to output various control timings such as the selection timing signal of RAS), data is written in advance in the read-only memory (ROM) corresponding to the address, and the access request signal (SRVIN) from CPL1 is output. , or the read-only memory (ROM) is accessed based on the refresh request signal (RFRQ) from the fresh counter 5.
By simply changing the contents of the OM), it is possible to generate access timings for various storage devices.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, where the same symbols as in FIG. 3 indicate the same objects, 3'' is a functional block necessary to implement the present invention, It corresponds to the timing control circuit (TCTL) 3 in the figure, and is composed of a read-only memory (ROM) 31 and a register 32 that latches the read data as shown.

In the read-only memory (ROM) 31, AO-
45 indicates an address terminal, 01 to 08 indicate output terminals, and in the register 32, Di-08 indicates an input terminal, and 01 to Q8 indicate output terminals.

The key point of the present invention is that the various control timing signals explained in FIG. It is possible to extract various timing signals at timings that are integral multiples of the access time.

The overall operation when accessing memory array (RAM) 2 is exactly the same as the conventional method, so here,
This timing control circuit (TCTL) which is the main focus of the present invention
The explanation will be limited to operation 3'.

Therefore, since the operation time chart is also the same as that in FIG. 4, the timing signal generation operation when the present invention is implemented will be explained with reference to the time chart.

FIG. 2 shows an example of the relationship between the input data (i.e. address) of the ROM 31 and the output data.
In this example, the access time and cycle time are
For example, if it is 50 ns, output data will be sequentially output to the output terminals (01-08) with a delay of 50 ns with respect to the address (AO~^5) that is input every 50 ns.

Among the various signal names shown in this diagram, those with the same names as those explained in Figure 3 indicate the same signals, but RAI
3 to 0 indicate the next address signals for sequentially accessing the ROM 31, and as shown in the figure, part of the output data of the ROM 31 read previously (R
A3-0). And RA13~0
(hexadecimal) is the value of RAr3~0 above expressed in hexadecimal, and RA3~0 (hexadecimal) is the value of RAr3~0 above.
This is a hexadecimal representation of a value between 3 and 0.

Further, in the figure, the value of the part represented by (-) indicates that it may be "0" or "1".

First, RAI3~0'' is 'o'-t' and 5RVIN
, RFRQ is 0'', indicating that there is no access request to the ROM 31.

Therefore, the output of the ROM 31 as well as the RAS and CAS strobe signals are not activated in the "L" state.

Here, for example, the access request signal 5RV is sent from the CPU 1.
When IN is manually entered as an address, RAI3~0'' remains 'oooo', and 50 ns later, the RAS strobe signal is activated and becomes '0°. At this time, ROM 31
Output signal “R^3~Os that specifies the next address of
001', which becomes the next address information. [See Figure 2, ROM output, RA3~0 (hexadecimal number) °1] As a result, the CAS strobe signal is activated and becomes °0'', and "RA3~θ" outputs "ooio". [Figure 2, ROM output, RA3~0 (
(see hexadecimal number) 2''] Thereafter, the ROM 31 is sequentially accessed in the same way, and the output data (01 to 08) is sent to the register 32, thereby completing the conventional method shown in FIG. 4(A). It can be seen that the same timing signal is generated. Also,
During refresh operation, the above “RA3~θ” is 0,
By stepping up to 5, 6, 7.8, Figure 4 (b)
It can be seen that the refresh timing shown by is obtained.

In this way, in the present invention, various timing signals different from those in this embodiment can be generated every 50 ns, for example, by simply rewriting the contents of the ROM 31 that constitutes the timing control circuit (TCTL) 3'. Therefore, it is possible to flexibly deal with changes in the control mode, usage pattern, etc. of the storage device.

In addition, if the memory elements of one memory array (RAM) become faster and cannot be supported by the above 50 ns timing,
It can be seen that this problem can be easily dealt with by using a high-speed element with a short access time as the element of the ROM 31.

In the above embodiment, a method was described in which a control timing signal for a memory array (RAM) constituted by a dynamic RAM is generated by a read-only memory (ROM). However, considering the essence of the present invention, the above-mentioned Various operating modes of storage devices, such as:

It goes without saying that the invention can also be applied to other forms of use.

〔Effect of the invention〕

As described above in detail, the memory control method of the present invention is such that the read-only memory IJ (ROM) is
Focusing on the fact that various data can be retrieved at I (i.e., access time), for example, when accessing the dynamic RAM 2 at a timing that is an integral multiple of the access time of the read-only memory (ROM), ■RAS, CAS strobe timing signal necessary to access the dynamic RAM2 ■RAM
Latch timing signal for fetching output data from RAM address (RAS), lower address (CAS), refresh address (RA
In order to output various control timings such as the selection timing signal of S), data is written in advance in the read-only memory (1 to 01'l) corresponding to the address, and the access request signal ( Since the read-only memory (ROM) is accessed based on the SRV(N) or the refresh request signal (RFRQ) from the refresh counter 5, the read-only memory (ROM)
By simply changing the contents of the ROM (ROM), it is possible to generate access timings for various storage devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing an example of the relationship between input and output of a read-only memory (ROM) when accessing a storage device by applying the present invention. FIG. 3 is a diagram illustrating a conventional storage device access method. FIG. 4 is a time chart showing an example of various timing signals when accessing a storage device. It is. In the drawing, 1 is a central processing unit (CPU), and 2 is a memory array (RA).
M). 3.3° is the timing control circuit (TCTL). 4 is an address selection section. 5 is a refresh counter. 6 is the output edge register. SRVI is an access request signal. RFRQ is a refresh request signal. RAS is the upper address (RAS) strobe signal. CAS is a lower address (CAS) strobe signal. LA is the output latch signal. RFL is a refresher address selection signal. are shown respectively.

Claims (1)

[Claims] A device for controlling a storage device includes a read-only memory (ROM) activated by a control signal for accessing the storage device, the read-only memory (ROM)
A memory control method characterized in that various timing controls for accessing the storage device are performed based on output data of the memory device.