JPH07146814A - Memory device - Google Patents

Abstract

PURPOSE:To provide a memory device capable of changing a timing to output a read completion signal corresponding to the access time of a storage means in actual working environment. CONSTITUTION:This device is equipped with a counter means 101 which outputs a timing change request signal to request the change of the timing to output the read completion signal representing the determination of read out data, and an arbitration means 102 which reads out by making access specific data when the timing change request signal is issued. Also, it is equipped with a comparison means 105 which compares read out specific data with the expected value of the data, and a read timing control means 104 which changes the timing to output the read completion signal based on lapse time from the start of access to the specific data to the coincidence of result data of comparison.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dynamic RAM.
The present invention relates to a memory device that uses a semiconductor memory such as (random access memory) as a storage unit.

[0002]

2. Description of the Related Art In recent years, the processing speed of a CPU (central processing unit) of a computer has been dramatically improved due to the progress of semiconductor technology. However, the speed of the memory device has not improved much compared to that, and the speed of the memory device has become a bottleneck in system performance.

An example of a conventional memory device will be described below with reference to the drawings. FIG. 5 is a block diagram of a conventional memory device. However, of the constituent elements of the memory device, those not directly related to the present invention are omitted. In FIG. 5, reference numeral 501 denotes access control means, 502
Is a storage means and 503 is a delay means.

When an access request signal is input from the outside, the access control means 501 outputs an access start signal according to the access request signal and the operating state of the memory device. An address is externally input to the storage unit 502, an access start signal is input from the access control unit 501, and when the access start signal changes from 0 to 1, access to the address data externally input is performed. In the case of read access, read data is output after a fixed time. The delay unit 503 delays the input access start signal by a fixed number of clocks and outputs it as a read completion signal to the outside. An external device such as a CPU, when the read completion signal becomes 1,
Take in the read data internally.

With respect to the memory device configured as described above, its read operation will be described below with reference to the timing chart of FIG.

First, assume that the access request signal becomes 1 in cycle 2. Then, in response to this, the access control means 501 sets the access start signal to 1 in cycle 3. As a result, the storage unit 502 starts the read operation of the data of the address input from the outside, and the data confirmed during the cycle 5 is output to the outside as the read data. Here, the access start signal is 1
The time from when the read data is confirmed to when the read data is confirmed is called access time.
It changes depending on the voltage and temperature. Then, the delay means 503 delays the access start signal by 5 clocks and sets the read completion signal to 1 in cycle 7. In this cycle 7, an external device such as a CPU fetches the read data, and the reading to the memory device is completed. In this operation example,
Although the read data is already fixed at the time of cycle 6, the read completion signal is not set to 1 in cycle 6, but this is because the access time is different from the use environment such as the voltage and temperature of the storage means and the individual difference. This is because the output timing of the read completion signal is set assuming that the access time will be the longest.

[0007]

However, in the above-mentioned configuration, the timing of outputting the read completion signal is determined assuming that the access time of the storage means 502 is the maximum, so that it is actually used. In most environments, access times are much less than their maximum. Nevertheless, there is a problem in that the timing at which the read completion signal is output is delayed and the timing at which the external device such as the CPU fetches the data is also delayed.

In consideration of such a problem of the conventional memory device, the present invention can change the timing of outputting the read completion signal according to the access time of the storage means in the environment actually used. It is an object to provide a memory device.

[0009]

According to the present invention, in addition to a general data storage area for storing general data, a storage means having a specific data storage area for storing specific data, and reading of general data is completed. That outputs the read completion signal indicating that the timing change request signal is output, and the counting means that outputs the timing change request signal and the specific data that is read when the timing change request signal is output. Data read instruction means,
Comparison means for comparing the read specific data with the preset expected value of the data, and the result of the comparison,
The memory device includes a timing changing unit that changes the timing of outputting the read completion signal based on the elapsed time from the start of access to the specific data until the data match.

[0010]

According to the present invention, the storage means has, in addition to the general data storage area for storing general data, a specific data storage area for storing specific data, and the counting means completes reading of the general data. Requesting a change in the timing of outputting a read completion signal indicating that the specific data read instruction means outputs the specific data when the timing change request signal is output. , The read specific data is compared with the expected value, and the timing changing means outputs a read completion signal based on the elapsed time from the access start of the specific data until the data match as a result of the comparison. Change the timing.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments.

FIG. 1 is a block diagram of a memory device according to the first embodiment of the present invention. However, of the constituent elements of the memory device, those not directly related to the present invention are omitted. In FIG. 1, 101 is a counting means, 102 is an arbitration means, 103 is a delay means, 104 is a read timing control means, 105 is a comparison means, and 106 is a storage means. The above-mentioned arbitration means 102 constitutes a specific data read instruction means, and delay means 103 and read timing control means 10 are provided.
Reference numeral 4 constitutes a timing changing means.

The counting means 101 has a built-in counter that counts down from an initial value N to 0 by a system clock, and sets a timing change request signal to 1 when the count value = 0. The arbitration means 102 inputs the access request signal and the timing change request signal,
Arbitration is performed between normal memory access and memory access for changing timing. Arbitration is performed according to the following rules.

(1) When the timing change request signal is 1, the memory access for changing the timing is preferentially executed regardless of the value of the access request signal. That is,
Both the dedicated data access signal and the access start signal are set to 1. When the access request signal is 1, the normal memory access is executed after the memory access for changing the timing is completed.

(2) When the timing change request signal is 0 and the access request signal is 1, normal memory access is executed. That is, the dedicated data access signal is set to 0,
The access start signal is set to 1.

(3) When both the timing change request signal and the access request signal are 0, the memory access is not executed and both the dedicated data access signal and the access start signal are set to 0.

The delay means 103 inputs the access start signal, the dedicated data access signal and the number of delay clocks. When the dedicated data access signal is 0, the delay means 103 receives the number of delay clocks after the access start signal becomes 1. After the elapse, the read completion signal is set to 1. At this time, if the dedicated data access signal is 1, the read completion signal remains 0 even if the access start signal becomes 1.

The read timing control means 104 inputs an access start signal, a dedicated data access signal, and a coincidence signal (described later), and when the dedicated data access signal is 1, the coincidence signal becomes valid after the access start signal becomes valid. Counts the number of clocks until it becomes effective, and outputs the number obtained by adding 1 to the delay means 103 as the number of delay clocks.

The comparison means 105 compares the read data output from the storage means 106 with a predetermined expected value, and when they match, sets a match signal to 1,
If they do not match, the match signal is set to 0.

The storage means 106 has a built-in read-only one-word-length dedicated storage area in which specific data is always read, in addition to a general-purpose storage area that is normally used. here,
Dedicated data access signal and access request signal are both 1
If the dedicated data access signal is 0 and the access request signal is 1, the general-purpose storage area is accessed according to the address input from the outside regardless of the address input from the outside. To output read data.

The operation of the memory device configured as described above will be described below with reference to the timing chart of FIG. At this time, it is assumed that the data A is stored in the address a, the data B is stored in the address b, and the data Z is stored in the dedicated storage area. In cycle 1, the number of delay clocks is 6.

First, in cycle 2, the access request signal is 1
Then, the arbitration means 102 executes normal memory access according to the above-mentioned rule (2).
That is, the access start signal is set to 1 in cycle 3.
Next, the storage means 106 starts reading to the address a input from the outside when the access start signal becomes 1 in cycle 3. After that, the read data changes to A in the middle of cycle 6. Since the number of delay clocks is 6, the delay means 103 sets the read completion signal to 1 6 clocks after the access start signal becomes 1, that is, in cycle 9. Then, at this time CP
An external device such as U fetches the read data and the read operation is completed.

Next, when both the access request signal and the timing change request signal become 1 in cycle 11, the arbitration means 102 first prioritizes and executes the memory access for the timing change according to the above-mentioned rule (1). , Perform normal memory access.
Here, cycles 12 to 17 are memory accesses for changing the timing, and cycles 18 to 23 are normal memory accesses.

First, in cycle 12, the access start signal and the dedicated data access signal become 1. by this,
The storage unit 106 starts reading the dedicated storage area regardless of the address b input from the outside, and then the read data changes to Z in the middle of the cycle 15. This causes the comparison means 105 to set the coincidence signal to 1 at the end of cycle 15. Then, the read timing control means 1
04 counts the number of cycles from the cycle 12 in which the access start signal becomes 1 to the cycle 16 in which the coincidence signal becomes 1 and adds 1 to it. As a result, the number of cycles becomes 5, and the number of delay clocks is changed from 6 to 5 in cycle 17.
Change to. Then, in this cycle 17, the memory access for changing the timing is completed. Then cycle 1
At 8, the access start signal becomes 1 and the dedicated data access signal becomes 0, the read to the waiting address b is started, and the read data changes to B in the middle of cycle 21. Then, at this time, the number of delay clocks is already 5
Therefore, the read completion signal becomes 1 in cycle 23 one clock earlier than the time of the first read to the address a, and the read operation to the address b is completed. In this way, the number of delay clocks corresponding to the actual access time is changed at regular intervals thereafter. As a result, highly efficient access becomes possible.

As described above, according to this embodiment, the counting means 1 for setting the timing change request signal to 1 at a constant cycle.
01, arbitration means 102 for performing arbitration between normal memory access and memory access for timing change, and when the dedicated data access signal is 1, the access start signal becomes valid and then the coincidence signal becomes valid. Read timing control means 104 which counts the number of clocks up to and outputs the number obtained by adding 1 to the delay means 103 to the delay means 103.
And the read data and a predetermined expected value are compared with each other.
5 and the storage means 106 having a built-in read-only 1-word-long dedicated storage area where specific data is always read, in addition to the general-purpose storage area normally used, the access time of the storage device, that is, access As the time from when the start signal becomes 1 to when the read data is output changes depending on the individual difference of the storage device and the usage environment, the timing of outputting the read completion signal changes. Also in this case, the read access can be always performed by utilizing the access performance of the storage device to the limit.

FIG. 3 is a block diagram of a memory device according to the second embodiment of the present invention. In FIG. 3, 101 is a counting means, 102 is an arbitration means, 103 is a delay means, 104 is a read timing control means, and 105.
Is a comparison means, and the above is the same as the configuration of FIG. 1 is different from FIG. 1 in that the write data holding unit 201 and the address mask unit 203 are provided, and the storage unit 106 in FIG. 1 is changed to a storage unit 202 having a structure without a dedicated storage area.

The write data holding means 201 inputs an address and write data input from the outside and R / W indicating read access or write access, and when the write to the address 0 is executed, the write data is written. Is internally held and is output to the comparison means 105 as expected value data.

The storage means 202 is a general storage means that contains only a general-purpose storage area that is normally used. When the dedicated data access signal is 1, the address masking unit 203 outputs 0 to the storage unit 202 as an access address regardless of the address input from the outside.

The operation of the memory device configured as described above will be described below with reference to the timing chart of FIG. At this time, it is assumed that the data A is stored in the address a of the storage means 202.

First, when the access request signal is 1, the address is 0, and the R / W is 1 in cycle 2, the arbitration means 102 executes a normal memory access according to the above-mentioned rule (2). In this case, writing to address 0 is executed. At this time, the write data is assumed to be B. Then, the write data holding means 201
Holds this write data B inside and outputs it to the comparing means 105 as expected value data.

Next, when both the access request signal and the timing change request signal become 1 in cycle 8, the arbitration means 102 first prioritizes and executes the memory access for the timing change according to the above-mentioned rule (1). , Perform normal memory access. Here, cycle 9 to cycle 14 are memory accesses for changing the timing, and cycle 15 to cycle 20.
Is a normal memory access.

First, in cycle 9, the access start signal and the dedicated data access signal become 1. As a result, the address mask unit 203 outputs the address 0 to the storage unit 202 as an access address regardless of the address a input from the outside. Therefore, data B at address 0 is output as read data from the middle of cycle 12. This causes the comparison means 105 to set the coincidence signal to 1 at the end of cycle 12. Then, the read timing control unit 104 counts the number of cycles from the cycle 9 in which the access start signal becomes 1 to the cycle 13 in which the coincidence signal becomes 1 and adds 1 to it. As a result, the number of cycles becomes 5, and in cycle 14, the number of delay clocks is changed from 6 to 5. Then, in this cycle 14, the memory access for changing the timing is completed.

Next, in cycle 15, when the access start signal becomes 1 and the dedicated data access signal becomes 0, the reading to the awaited address a is started, and cycle 18
The read data changes to A in the middle of. Then, since the number of delay clocks at this time is 5, the read completion signal becomes 1 in cycle 20 and the read operation to the address a is completed.

As described above, according to this embodiment, the counting means 1 for setting the timing change request signal to 1 at a constant cycle.
01, arbitration means 102 for performing arbitration between normal memory access and memory access for timing change, and when the dedicated data access signal is 1, the access start signal becomes valid and then the coincidence signal becomes valid. Read timing control means 104 which counts the number of clocks up to and outputs the number obtained by adding 1 to the delay means 103 to the delay means 103.
And the read data and a predetermined expected value are compared with each other.
5, the address and write data input from the outside, and R / W indicating read access or write access are input, and when write to address 0 is executed, the write data is held internally, and Is output to the comparing means 105 as expected value data, the write data holding means 201
When the dedicated data access signal is 1, the address masking unit 20 outputs 0 to the storage unit 202 as an access address regardless of the address input from the outside.
3 is provided, the same as in the first embodiment is obtained by using the general storage means 202 including only the general-purpose storage area normally used, instead of the special storage means 106 used in the first embodiment. In any environment, it is possible to always perform a read access using the access performance of the storage device to the limit.

In the first embodiment, the storage means 1
Although the number of 06 is set to one, the number is not limited to this, and may be configured to include a plurality of storage units. In this case, a timing change request signal and a dedicated data access signal are provided for each storage means.

In the second embodiment, the storage means 2
Although the number of 02 is one, it may be configured to include a plurality of storage means. In this case, a timing change request signal and a dedicated data access signal are provided for each storage unit, and the write data storage unit 201 stores the expected value data for each storage unit.

Further, in the second embodiment, the address to which the data for comparison is written is the address 0, but other addresses may be used.

[0038]

As is apparent from the above description, according to the present invention, in addition to a general data storage area for storing general data, a storage means having a specific data storage area for storing specific data, and general data. When the timing change request signal is output, the specific means is accessed when the timing change request signal is output. Specific data read instructing means to be read out, a comparing means for comparing the read specific data with an expected value of the data set in advance, and as a result of the comparison, until the data match,
Based on the elapsed time from the start of access to specific data,
Since the timing changing means for changing the timing of outputting the read completion signal is provided, it is possible to change the timing of outputting the read completion signal in accordance with the access time of the storage means in the actually used environment. It has advantages.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation in the first embodiment.

FIG. 3 is a configuration diagram of a memory device according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining an operation in the second embodiment.

FIG. 5 is a configuration diagram of a conventional memory device.

FIG. 6 is a timing chart for explaining the operation of the conventional memory device.

[Explanation of symbols]

 101 Counting Means 102 Arbitration Means 103 Delay Means 104 Read Timing Control Means 105 Comparing Means 106 Storage Means 201 Write Data Holding Means 202 Storage Means 203 Address Masking Means

Claims (2)

[Claims] 1. A storage unit having a specific data storage area for storing specific data, in addition to the general data storage area for storing general data, and reading of the general data should be completed. Counting means for outputting a timing change request signal requesting a change in the timing of issuing the read completion signal, and specific data read instructing means for accessing and reading the specific data when the timing change request signal is output. , Comparing means for comparing the read specific data with preset expected values of the data, and as a result of the comparison, the elapsed time from the start of access to the specific data until the data match. And a timing changing means for changing the timing of outputting the read completion signal based on the above. Place 2. The specific data storage area is indicated by a predetermined address preset in the storage means, and the expected value holds the data when the specific data is written in the predetermined address. The memory device according to claim 1, wherein