JP2795310B2 - Memory control device and memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a dynamic RA.
The present invention relates to a memory control device that controls an access operation such as read / write to M (hereinafter, abbreviated as DRAM).

[0002]

2. Description of the Related Art A DRAM has a simple structure of a memory cell, so that the area can be reduced. Even if the same level of manufacturing technology is used, a highly integrated RAM can be realized. Therefore, D
The RAM has a feature that the packing density can be improved due to the miniaturization of the memory system, and the low cost per bit leads to the provision of a cheap and large-capacity RAM. Due to these features, the DRAM is used as the most general-purpose memory in a main storage device or an extended storage device of a computer.

In a DRAM, stored information is represented by electric charge stored in a charge accumulating capacitance element. However, the accumulated electric charge is reduced due to leakage current of a charge input / output control element and recombination on the surface of a semiconductor substrate. Decays over time.
For this reason, it is necessary to refresh the DRAM for updating the storage information at regular intervals.

[0004]

By the way, access instructions such as read / write to the DRAM from a processor of a computer or the like are generated asynchronously with respect to refresh, so that a conflict between access and refresh may occur. There is.

On the other hand, in a conventional memory control device for controlling an access operation to a DRAM, a DRA
When the access instruction to M and the refresh instruction conflict with each other, according to each timing of the conflicting instructions,
There is an example in which arbitration control for delaying refresh or suspending an access instruction is performed. The arbitration control by the memory control device is described in, for example,
No. 40549.

In a conventional memory control device, if a refresh instruction signal is received while an access instruction signal is already being received, refresh is delayed. However, there is a limit to the time during which the refresh can be delayed, and immediately before this limit, in some cases, it is necessary to prioritize the refresh and suspend the access instruction. Also, when the access instruction signal is received during the execution of the refresh, the access instruction is suspended. If the access instruction is suspended, that is, if the access instruction is a read request, the response to the issuer of the access instruction is delayed, which adversely affects the performance of the system.

An object of the present invention is to provide a memory control device which prevents adverse effects on system performance due to contention between an access instruction and refresh.

[0008]

According to the present invention, an address is specified at the time of access by inputting a column address strobe signal following a row address strobe signal, while a row address is specified following a column address strobe signal. A memory control device which is applied to a dynamic RAM having a mode in which a refresh operation is performed by inputting a strobe signal and controls access and refresh of the dynamic RAM, wherein an access request source which issues an access instruction signal is connected to an input side. A refresh control circuit for issuing a refresh instruction signal at a predetermined issuance interval, the access request source side and the refresh control circuit being connected to an input side, and the dynamic RAM being connected to an output side. The dyna A memory access control circuit for controlling access to the memory RAM and refreshing, and when there is an access instruction signal from the access request source, the memory access control circuit controls a row address strobe to the dynamic RAM. A signal, a column address strobe signal, and a row address strobe signal are successively output. If there is a refresh instruction signal from the refresh control circuit simultaneously with the access instruction signal, the refresh instruction is invalidated. Wherein the refresh control circuit resets the issuance interval for a refresh instruction signal to an initial value when an access instruction signal is received from the access request source. Can be

According to the invention, the refresh control circuit includes a counter for counting the issuance interval for the refresh instruction signal from the initial value, a register for storing the initial value of the issuance interval, and a count value of the counter. A counter that outputs a count instruction signal to the counter if counting is not completed and outputs a refresh instruction signal if counting is completed and outputs a reset instruction signal to the counter. Wherein the counter is reset when there is an access instruction signal from the access request source.

According to the present invention, there is further provided a memory device comprising the dynamic RAM and the memory control device.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory control device according to an embodiment of the present invention will be described with reference to the drawings.

The present memory control device is a device that controls access to and refresh of a DRAM.

A DRAM to which the present invention is applied has memory cells arranged in a matrix, and a row address signal and a column address signal are input from the same input pin in a time-division manner to specify an address at the time of access. Make That is,
In this DRAM, a row address strobe (hereinafter, abbreviated as RAS) is input after a row address is applied, so that an address signal is taken in and latched as a row address. Subsequently, after applying a column address signal, a column address strobe (hereinafter, abbreviated as CAS) signal is input to take in the address signal and latch it as a column address.

Further, as described above, the present DRAM
A mode in which an address is specified at the time of access by inputting a CAS signal following an S signal, while performing a refresh operation by inputting a RAS signal following a CAS signal (hiddenrefresh mod).
e). In the present invention, the state in which the strobe signals continue is a state in which at least each falling continues with a difference of one clock or more. Therefore, after both fall, there may be a part which overlaps with each other at the same clock.

FIG. 1 is a block diagram showing a memory control device according to the present embodiment. Referring to FIG. 1, the memory control device is configured such that an access request source (not shown) such as a CPU of a computer that issues an access instruction signal is connected to an input side and issues a refresh instruction signal at a predetermined issuance interval. A refresh control circuit 10, an access request source side and a refresh control circuit 10 connected to an input side, a DRAM connected to an output side, and a memory access control circuit 20 for controlling access and refresh to the DRAM; have. still,
In the present embodiment, a system of 4 clocks / 1 bus cycle is assumed.

The memory access control circuit 20 receives an access instruction signal and an access type (read / write) signal from an access request source at its input side,
At least the RAS terminal, the CAS terminal, the read operation (hereinafter referred to as OE) terminal, and the write operation (hereinafter referred to as WE) terminal of the DRAM are connected to the output side. In particular, when there is an access instruction signal from an access request source, the memory access control circuit 20 successively outputs a RAS signal, a CAS signal, and a RAS signal to the DRAM. Further, if there is a refresh instruction signal from the refresh control circuit 10 at the same time as the access instruction signal, the refresh instruction signal is invalidated.

The refresh control circuit 10 resets the issue interval for the refresh instruction signal to an initial value when there is an access instruction signal from an access request source.

The refresh control circuit 10
Refresh counter 1 as a subtraction counter for subtracting and counting the issue interval related to the fresh instruction signal from the initial value
1 and initial value n of a predetermined issue interval (n is the number of clocks)
, And a comparator 13. The comparator 13 compares the count value of the refresh counter 11 with the count completion value (0 in this example), and if the count is not completed (count value ≠ 0), the refresh counter 1
A subtraction instruction signal is output to 1. On the other hand, if the comparison result indicates that the counting is completed (the count value = 0), a refresh instruction signal is output and a reset instruction signal is output to the refresh counter 11.

Further, in the refresh control circuit 10, when there is an access instruction signal from an access request source, the refresh counter 11 is reset to an initial value n.

Incidentally, in the present invention, it is needless to say that the means for defining the predetermined issuance interval of the refresh instruction signal may be constituted by using an addition counter instead of the subtraction counter as in this embodiment. . In this example, the reset instruction signal output from the comparator 13 to the refresh counter 11 has the same form as the refresh instruction signal.

In the present invention, the initial value n relating to the interval at which the refresh instruction signal is issued is basically set so that the information stored in the memory cell in the DRAM is not destroyed. Set in consideration of the attenuation limit. However, it should be set in consideration of the following facts.

In the present invention, hidden refr
The refresh by the esh mode is executed when an access instruction signal is issued. More specifically, when there is an access instruction signal, as described above, first, after the RAS signal and the CAS signal are successively output for addressing, the RAS signal is output after the CAS signal is further output. Refresh is performed. In other words, the RAS signal related to refresh is not output while the RAS signal for addressing is being output. That is, the refresh is not executed during the output of the RAS signal for address designation.

Here, immediately before the time at which refresh is to be issued, that is, immediately before the count value of the refresh counter 11 reaches the count completion value, if there is an access instruction signal, the RAS signal for address designation is output. During this time, the RAS signal relating to the refresh is not output, so that even if the counting is completed (even at the time when the refresh should be issued), a “refresh delay” in which the refresh is not executed may occur. As described above, the “refresh delay” is not preferable because it leads to the destruction of the stored information due to the attenuation of the charge stored in the memory cell. In particular, when address data related to addressing is long, the RAS signal for addressing is also
The output of the RAS signal relating to the refresh is also delayed, and the delay time of the “refresh delay” is long, which is not preferable.

Therefore, in the present invention, the initial value n relating to the issuance interval of the refresh instruction signal should be set in consideration of the longest time expected for the time difference from when the access instruction is issued to when the refresh is executed. It is. That is, the issue interval of the refresh instruction signal should be set shorter than the case where the time difference is not considered.

FIGS. 2 to 4 are timing charts showing the operation of the present apparatus when there is a read access instruction signal from the access request source. FIGS. 5 to 7 each show a write access instruction signal from the access request source. FIG. 4 is a timing chart showing the operation of the present device in the case.

Hereinafter, the operation of the present apparatus will be described with reference to FIG. 1 and FIGS.

FIG. 2 shows a case where the refresh instruction signal from the refresh control circuit 10 does not conflict with the read access instruction signal from the access request source. In FIG. 2, when the count value of the refresh counter 11 in the refresh control circuit 10 becomes 0, the comparator 13 determines this, and outputs a reset instruction signal and a refresh instruction signal. Refresh counter 11
Fetches an initial value n from the register 12. Upon receiving the refresh instruction signal, memory access control circuit 20 outputs a RAS signal following the CAS signal,
Perform refresh for.

When a read access instruction signal is received from the access request source, that is, when the refresh control circuit 10
When the access instruction signal is input to the memory access control circuit 20 and the access instruction signal and the read access type signal are input to the memory access control circuit 20, the present device operates as follows. The refresh counter 11 takes in the initial value n from the register 12. The memory access control circuit 20
The RAS signal and the CAS signal are successively output to the DRAM so as to respond to the address signal at a predetermined timing to perform address designation, output the OE signal, and subsequently output the RAS signal. Perform refresh. The DRAM is read and refreshed in accordance with the designated address.

FIG. 3 shows a case where a refresh instruction signal by the refresh control circuit 10 and an access instruction signal for reading from an access request source are simultaneously generated. In FIG. 3, when the count value of the refresh counter 11 in the refresh control circuit 10 becomes 0, the comparator 13 outputs a reset instruction signal and a refresh instruction signal. The refresh counter 11 takes in the initial value n from the register 12. On the other hand, at the clock when the count value of the refresh counter 11 becomes 0, a read access instruction signal is input from the access request source.
The memory access control circuit 20 invalidates the refresh instruction signal from the refresh control circuit 10. Since the memory access control circuit 20 also receives a read access type signal, the RAS signal and the CAS signal are continuously output to the DRAM so as to respond to the address signal at a predetermined timing to specify the address. At the same time, the OE signal is output. Memory access control circuit 2
0 further outputs a RAS signal following the CAS signal to execute refresh. The DRAM is read and refreshed in accordance with the designated address. Since the refresh control circuit 10 receives the access instruction signal, the refresh counter 11
Again, the initial value n is fetched from the register 12.

Thereafter, when the read access instruction signal from the access request source is input alone, the same operation as described in FIG. 2 is performed.

FIG. 4 shows a case where a read access instruction signal is generated from an access request source immediately before a refresh instruction signal is issued by the refresh control circuit 10. In FIG. 4, immediately before the count value of the refresh counter 11 in the refresh control circuit 10 becomes 0 (in FIG. 4, the count value is 4), a read access instruction signal is input from the access request source. That is, the access instruction signal was input to the refresh control circuit 10, and the access instruction signal and the read access type signal were input to the memory access control circuit 20. The refresh counter 11 takes in the initial value n from the register 12. The memory access control circuit 20 successively outputs the RAS signal and the CAS signal to the DRAM so as to respond to the address signal at a predetermined timing, performs the address designation, and outputs the OE signal. The memory access control circuit 20 further outputs a RAS signal following the CAS signal to execute refresh. The DRAM is read and refreshed in accordance with the designated address. In this case, if the count value of the refresh counter 11 becomes 0, the refresh is delayed compared to when the refresh instruction signal is executed by the refresh control circuit 10. However, as described above, since the initial value n is set in consideration of the longest time difference from when the access instruction signal is issued to when the refresh is executed, the accumulated charge in the memory cell of the DRAM is attenuated beyond the limit. The stored information will not be destroyed.

Thereafter, when the read access instruction signal from the access request source is input alone, the same operation as described with reference to FIG. 2 is performed.

FIG. 5 shows a case where the refresh instruction signal from the refresh control circuit 10 does not conflict with the write access instruction signal from the access request source. In FIG. 5, when the count value of the refresh counter 11 in the refresh control circuit 10 becomes 0, the memory access control device 20 refreshes the DRAM as in the case of FIG.

When a write access instruction signal is received from an access request source, that is, when the refresh control circuit 10
When an access instruction signal and an access instruction signal and a write access type signal enter the memory access control circuit 20, the present device operates as follows. The refresh counter 11 takes in the initial value n from the register 12. The memory access control circuit 20
The RAS signal and the CAS signal are successively output to the DRAM so as to respond to the address signal at a predetermined timing to perform address designation, output the WE signal, and subsequently output the RAS signal. Perform refresh. The DRAM is written and refreshed according to the designated address.

FIG. 6 shows a case where a refresh instruction signal from the refresh control circuit 10 and a write access instruction signal from an access request source are simultaneously generated. 6, when the count value of the refresh counter 11 in the refresh control circuit 10 becomes 0 and a read access instruction signal is input from the access request source at the same time, the memory access control circuit 20 performs the refresh control as in the case of FIG. The refresh instruction signal from the circuit 10 is invalidated. Since the memory access control circuit 20 also contains a write access type signal, the DRA
The RAS signal and the CAS signal are successively output to the address signal M so as to respond to the address signal at a predetermined timing, and the address is designated, and the WE signal is output.
The memory access control circuit 20 further outputs a RAS signal following the CAS signal to execute refresh.
The DRAM is written and refreshed according to the designated address. Since the refresh control circuit 10 receives the access instruction signal, the refresh counter 11 again stores the initial value n in the register 1.
I'm importing from 2.

FIG. 7 shows a case where a write access instruction signal is generated from an access request source immediately before a refresh instruction signal is issued by the refresh control circuit 10. In FIG. 7, immediately before the count value of the refresh counter 11 in the refresh control circuit 10 becomes 0 (in the figure, the count value is 4), a write access instruction signal is input from the access request source. That is, the access instruction signal was input to the refresh control circuit 10, and the access instruction signal and the write access type signal were input to the memory access control circuit 20. The refresh counter 11 takes in the initial value n from the register 12. The memory access control circuit 20 performs address designation to the DRAM in the same manner as in the case of FIG. 4, and outputs a WE signal. The memory access control circuit 20 further outputs a RAS signal following the CAS signal to execute refresh. The DRAM is written and refreshed according to the designated address. In this case,
Similar to the case of FIG. 4, although the refresh is delayed as compared with the case where the refresh instruction signal is executed by the refresh control circuit 10, the initial value n is set to be shorter, so that the accumulated charge in the memory cell of the DRAM is limited. And the stored information is not destroyed.

[0037]

According to the memory control device of the present invention, an address is specified at the time of access by inputting a column address strobe signal subsequent to a row address strobe signal, while a row address strobe signal follows a column address strobe signal. Is applied to a dynamic RAM having a mode of performing a refresh operation by inputting an access request signal, and a memory control device for controlling access and refresh of the dynamic RAM, wherein an access request source for issuing an access instruction signal is connected to the input side. And a refresh control circuit that issues a refresh instruction signal at a predetermined issue interval, and an access request source side and a refresh control circuit are connected to the input side.
A dynamic RAM is connected to the output side, and has a memory access control circuit for controlling access to the dynamic RAM and refreshing. When the memory access control circuit receives an access instruction signal from an access request source, The RAM sequentially outputs a row address strobe signal, a column address strobe signal, and a row address strobe signal to the RAM. If there is a refresh instruction signal from the refresh control circuit at the same time as the access instruction signal, it is output. The refresh instruction is invalidated, and the refresh control circuit resets the issue interval related to the refresh instruction signal to an initial value when there is an access instruction signal from the access request source. Competition Thereby preventing adverse effect on the performance of the originating system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a memory control device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of the memory control device shown in FIG. 1;

FIG. 3 is a timing chart for explaining an operation of the memory control device shown in FIG. 1;

FIG. 4 is a timing chart for explaining an operation of the memory control device shown in FIG. 1;

FIG. 5 is a timing chart for explaining an operation of the memory control device shown in FIG. 1;

FIG. 6 is a timing chart for explaining an operation of the memory control device shown in FIG. 1;

FIG. 7 is a timing chart for explaining the operation of the memory control device shown in FIG. 1;

[Explanation of symbols]

 Reference Signs List 10 refresh control circuit 11 refresh counter 12 register 13 comparator 20 memory access control circuit

Claims (3)

(57) [Claims] An address is specified at the time of access by inputting a column address strobe signal following a row address strobe signal, and a refresh operation is performed by inputting a row address strobe signal following a column address strobe signal. A memory control device which is applied to a dynamic RAM having a mode to execute and controls access and refresh of the dynamic RAM, wherein an access request source for issuing an access instruction signal is connected to an input side and a predetermined issue interval A refresh control circuit for issuing a refresh instruction signal at
While the access request source side and the refresh control circuit are connected to the input side, the dynamic RA
M is connected to the output side, and has a memory access control circuit for controlling access to the dynamic RAM and refreshing. The memory access control circuit, when receiving an access instruction signal from the access request source, Sequentially outputting a row address strobe signal, a column address strobe signal, and a row address strobe signal to the dynamic RAM, and further including a refresh instruction signal from the refresh control circuit simultaneously with the access instruction signal. The refresh instruction is invalidated, and when there is an access instruction signal from the access request source, the refresh control circuit resets the issue interval for the refresh instruction signal to an initial value. Memory system characterized by Apparatus. 2. A refresh control circuit comprising: a counter for counting the issuance interval for a refresh instruction signal from the initial value; a register for storing the initial value of the issuance interval; A comparator that outputs a counting instruction signal to the counter if the counting is not completed and outputs a refresh instruction signal if the counting is completed and outputs a reset instruction signal to the counter. 2. The memory control device according to claim 1, wherein the counter is reset when there is an access instruction signal from a request source. 3. A memory device comprising the dynamic RAM and the memory control device according to claim 1.