JPH0450625B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory bus control method for electronic computers, and is particularly suitable for systems that have a restriction on the number of bus signal lines and that use dynamic random access memory. This paper relates to a memory bus control method.

[Conventional technology]

Electronic computers generally have the configuration shown in FIG. 2, except for some special purpose computers. That is, main processing unit 1
A main memory 102 is connected via a memory bus 111 to the main memory 01. On the other hand, an input/output control mechanism 103 is connected via an input/output bus 112, and an input/output device 104 operates under the control of the main processing unit 101 and the input/output control mechanism 103. Depending on the system configuration of the computer, the memory bus 111 and the input/output bus 112 may be used together.

In such a computer system, the main memory 102 and the input/output control mechanism 103 are modularized in order to make the main memory capacity variable depending on the system use or to change the input/output device configuration depending on the system use. , module to memory bus 1
11 or an input/output bus 112. For example, in a system that requires a small storage capacity but at a low price, only one main memory module is installed, whereas in a system that requires a large storage capacity, the maximum number of main storage modules that can be installed is installed. Memory is implemented.

In order to miniaturize such a system, it is necessary to reduce the size of the module. To achieve this, the circuit configuration within each module must be minimized. On the other hand, the signal line of the bus that connects the modules occupies one side of the module when the modules are configured in a two-dimensional configuration (for example, each module corresponds to one printed wiring board). Therefore, when the module is miniaturized, the number of bus signal lines is subject to restrictions. Similar restrictions apply when configuring a bus using empty pins in a system where the number of signal lines and module dimensions are already fixed, such as an IEEE796-compliant input/output bus.

When such constraints exist, the number of signal lines required for performance may not be sufficient, and the conventional method to deal with this problem is to use the address signal Some have multiple lines and data signal lines. This conventional method is described in Chapter 2, pages 10 to 25 of the product catalog "Microprocessor and Peripheral Handbook (1983)" published by Intel Corporation in the United States.
Although detailed in Handbook (1983) Pages 2-10 to 2-25), an outline of the address/data multiplexing of the processor 8085 will be explained below.

The processor 8085 is the same company's microprocessor 8080.
Although the number of signal lines has increased as the functions have been enhanced, since it uses the same package as the 8080 (40-pin dual in-line package), it is possible to multiplex address and data signal lines. I went there. FIG. 3 schematically shows the data transfer signals and peripheral circuits of the 8085.
The 8085 microprocessor 201 has eight address buses 211, eight address/data multiplex buses 212, an address latch enable signal 213,
The memory and peripheral circuits are accessed through signal lines for a read access timing signal 214, a write access timing signal 215, and an access ready signal 216. In devices such as static memory, it is necessary to hold the corresponding address while accessing it, but on the other hand, 8 bits of the 16 bits of the address are output from the address/data multiplexed bus 212, and are not held during data transfer. Since this address cannot be output, it is necessary to provide an address latch circuit 202 externally to hold the address.

4 and 5 show the access timing of the 8085 microprocessor 201 including the address latch circuit 202.
FIG. 5 shows the case of writing. In these figures, when an address is output from the address/data multiplexed bus 212 at the beginning of an access cycle, the address latch enable signal 213 turns on almost simultaneously with this address output, and this signal 213 indicates that the address is being output. returns to the off state. As a result, the address from the bus 212 is held in the address latch circuit 202, and the held address 217 and the address 211 held in the microprocessor 201 itself constitute an address bus 221. After the address latch enable signal 213 turns off, the address output from the address/data multiplexed bus 212 ends after a predetermined holding time, and this bus 212 becomes the data bus 222, and the access timing signals 214, (read , Fig. 4) 215 (writing,
Data transfer is performed according to the timing shown in FIG.

When address/data multiplexing is performed in this manner, the number of signal lines can be reduced by adding an address latch enable signal and providing an external latch circuit. The 8085 is an 8-bit microprocessor, but the 8086 is also an 8-bit microprocessor.
By performing 16-bit address/data multiplexing, 16
Contains a bit microprocessor.

As mentioned above, by address/data multiplexing,
It is possible to increase the number of data signal lines without increasing the number of signal lines. However, if similar address/data multiplexing were to be performed on the memory bus of a system configured as shown in FIG. 2, each memory module would have to be provided with an address latch.

On the other hand, as a storage element for the main memory 102, an inexpensive and large-capacity dynamic random access memory (DRAM) is generally used.
When accessing DRAM, it is necessary to divide the address into a row address and a column address, and to apply a row address strobe signal and a column address strobe signal. Regarding DRAM access timing, please refer to the product catalog published by Hitachi, Ltd.
IC Memory Data Book” (Catalog No. 746U)
I am familiar with Therefore, if the 8085 signal is used as it is for the memory bus of a computer system as shown in Figure 2, and if DRAM is used as the main memory storage element, the row address strobe can be controlled from the read access timing signal or write access timing signal. It is necessary to provide a circuit for generating signals and column address strobe signals for each main memory module.

Additionally, DRAM has the property that once written content evaporates over time. Therefore, it is necessary to rewrite the contents periodically. This rewriting is called a refresh, and a typical refresh method is a refresh using a row address strobe signal. FIG. 6 shows the refresh timing using the row address strobe signal (RAS). That is, when a row address is added to the address input of the DRAM and the row address strobe signal is turned on, the contents of the memory cells in the row specified by the row address are rewritten. In order to perform refresh in this way, it is necessary to use a refresh counter to sequentially specify row addresses by the number of rows in the DRAM, a refresh timer to perform refresh periodically, and a row address strobe signal generation. However, since the 8085 does not take DRAM refresh into consideration, a circuit is required on each main memory module side to perform the above-mentioned refresh.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional technology, DRAM
No consideration has been given to the case where the DRAM is used as a memory bus in a computer equipped with a modular main memory, and each main memory module must be provided with a DRAM access timing signal generation circuit and a refresh control circuit. First, there was a problem that the amount of hardware increased. Furthermore, in the prior art, the address is determined,
Since the access timing signal is turned on after the address is latched, there is also a problem that the start of access is delayed.

An object of the present invention is to reduce the hardware of the main memory module in a system using an address/data multiplexed bus and DRAM, and to reduce the hardware of the entire computer system.
An object of the present invention is to provide a memory bus control method that allows high-speed access to DRAM.

[Means for solving problems]

The above purpose is to control a first timing signal which is an address latch enable signal and a row address strobe signal, a second timing signal which is a data transfer timing signal and a column address strobe signal, and a data transfer direction of an access cycle. A circuit that outputs a signal indicating whether it is a read or a write, a DRAM refresh address, and a refresh start timing signal.
This is achieved by providing it in the memory bus control section of the main processing unit.

[Effect]

When accessing the main memory, the first timing signal is turned on while the address is being output from the main processing unit onto the address/data multiplexed bus, thereby causing the address register provided in the main memory module to be turned on. While the address on the bus is latched, the row address stroke signal is turned on with the row address added to the address input of the DRAM. Next, the second timing signal is turned on, the address/data multiplexed bus is switched to the data bus, and the column address strobe signal is turned on with the column address added to the address input of the DRAM. This action
Data input/output pins of the DRAM are activated and data can be transferred, and data can be transferred without providing a timing circuit for DRAM access in each main memory module. In addition, since data access can be performed immediately with the second timing signal,
Delays in starting access can be reduced.

Also, when refreshing the DRAM, the address/
When a refresh address is output to the data multiplexing bus and the first signal is turned on,
Since the row address strobe signal is turned on with the refresh address added to the DRAM address input, a refresh cycle can be executed using the row address strobe signal, and the refresh control circuit can be It is not necessary to provide each main memory module.

〔Example〕

The present invention will be explained below with reference to Examples. FIG. 1 shows an embodiment of the method of the present invention, in which a main processing unit 101 is realized by a basic processing unit 11 that processes data according to instructions and other bus control units. The bus control section includes tristate buffers 197, 198, and 199 that connect internal buses 141 and 142 and memory bus 111, a refresh address counter 195, and a tristate buffer that outputs the contents of refresh address counter 195 to memory bus 111. buffer 196, and these tristate buffers and counter 7
The memory bus 111 includes a control circuit 131 that performs control of the memory bus 111 and timing control on the memory bus 111.

Memory bus 111 is address/data multiplex bus 1 and address latch enable signal.
Memory address strobe signal 2, which is a DRAM row address strobe signal; memory data strobe signal 3, which is a data transfer timing signal and a DRAM column address strobe signal; is on when access to main memory is a write access; memory write signal 4 which is in the OFF state, and memory acknowledge signal 5 which is an access response signal from the main memory.
Consisting of

The main memory 102 uses a dynamic operation type random access memory 151 as a storage element, and peripheral circuits are classified into three types: address system, data system, and control system. The address system includes a row address buffer 174, a column address register 153 that latches a column address using memory address strobe signal 2, and a row address register 153 that latches a column address when memory address strobe signal 2 is off, and a slight delay after the memory address strobe signal 2 is turned on. and the column address,
A multiplexer 152 that outputs to the DRAM 151, an address setting switch 156 assigned to the main memory module, and a memory bus 111, respectively.
A comparator 155 for comparing the above address with the contents of the switch 156, and a comparator 1
There is a register 154 that holds 55 match outputs. As a data type, light data buffer 1
73. Read data tri-state buffer 1
There are 71.

FIG. 7 shows an example of the internal configuration of the control circuit 131, which includes a shift register 41 for generating read/write timing, a shift register 42 for generating refresh timing, a refresh timer 51,
It consists of a refresh request register 52 and several gates.

In the embodiments described above, the main processing device 101
The operation when performing read access to the main memory 102 will be explained. FIG. 8 is a timing chart of the operation at this time. First, when the read/write discrimination signal 144 of the basic processing device 11 shown in FIG. 1 indicates read, the access request signal 143 is turned on. In response to this, the control timing circuit 131 in FIG. 7 turns off the memory write signal 4.
The address buffer control signal 187 is turned on. This causes address tri-state buffer 197 to output the contents of internal address bus 141 to address/data multiplexed bus 1. When the address is determined on the address/data multiplexed bus 1 (t ₁ in FIG. 8), the bit corresponding to the row address of the DRAM 151 out of all addresses is input to the multiplexer 152 through the address buffer 174. At this time, memory address strobe signal 2
is in the off state (note that 2 is shown as an inverted value in FIG. 8; the same applies to the others), so the row address from the buffer 174 is input from the multiplexer 152. In this state, when the output QA of the shift register 41 in FIG. 7 is turned on and the memory address strobe signal 2 is turned on (t ₂ in FIG. 8),
DRAM151 row address strobe signal RAS
is turned on, and the column address register 15
3 and the register 154 that holds information as to whether the address exists in the main memory module is in a hold state, and the delay gates 158 and 1
59, the output of the address multiplexer 152 changes from the row address to the column address from the register 153 ( _t3 in FIG. 8). Next, the output QB of the shift register 41 in FIG. 7 is turned on and the memory data strobe signal 3 is turned on, and at the same time, the address buffer control signal 187 is turned off and the data bus buffer control signal 189 is turned on. (Figure 8 t ₄ ). Then, the address buffer 197 becomes a high impedance state, the data bus buffer 199 becomes a low impedance state, and the contents of the address/data multiplexed bus 1 can be output onto the internal data bus 142. On the other hand, when the memory data strobe signal 3 turns on, the output of the AND gate 161 in the main memory 102 turns on when the access address exists in the main memory module, and the column address strobe CAS of the DRAM 151 turns on ( Figure 8 _t5 ). Further, when the output of the gate 161 is turned on, the output of the AND gate 163 is also turned on, and the data buffer 171 and the access response signal buffer 172 become in a low impedance state. Also and gate 1
The output of 61 is input to the shift register 157,
It is delayed by the time necessary to confirm the data output of the DRAM 151. When the data output of the DRAM 151 is determined (t ₆ in FIG. 8), the data is output to the address/data multiplexed bus 1 via the data bus buffer 171, which is then transferred via the data bus buffer 199 of the main processing unit 101. Internal data bus 14
2, and the read data is finalized. On the other hand, when the shift register 157 in the main memory 102 has elapsed a predetermined time, its output is turned on, and this is output as the memory acknowledge signal 5 via the buffer gate 172 ( _t7 in FIG. 8). Then, the timing circuit 131 turns on the access response signal 145 to the basic processing unit 11, whereby the basic processing unit 11 takes in the data on the internal data bus 142, and turns the access request signal 143 off. When the signal 143 is turned off, both the memory address strobe signal 2 and the memory data strobe signal 3 are turned off (t ₈ in FIG. 8),
Data bus buffer 199 enters a high impedance state. In addition, the DRAM 151 in the main memory 102
The row address strobe and column address strobe are both turned off ( _t9 in FIG. 8), the memory acknowledge signal 5 is turned off, and the tristate buffers 171 and 172 are placed in a high impedance state. With this, data reading from the main memory 102 is completed.

FIG. 9 is an operation time chart during write access from the main processing unit 101 to the main memory 102. In this case, the access request signal 143 is turned on while the read/write discrimination signal 144 of the basic processing unit 11 indicates write. In response to this, the control timing circuit 131 turns on the memory write signal 4 and turns on the address buffer control signal 1.
87 is turned on, and the address buffer 197 outputs the address to the address/data multiplexed bus 1 (t ₁ in FIG. 9). Thereafter, the process is the same as read access until the memory data strobe signal 3 turns on (t ₄ in FIG. 9). When writing to the DRAM 151, data input must be confirmed when the write enable signal WE turns on, and data input is confirmed when the memory data strobe signal 3 turns on (t ₄ ). Therefore, the output of the AND gate 161 is delayed by the shift register 157. When the output QA of the shift register 157 turns on, the output of the AND gate 162, that is, the write enable signal WE turns on (t ₁₀ in FIG. 9),
Data is written to the DRAM 151, and thereafter all accesses for write data are completed in the same procedure as for read access.

FIG. 10 is an operation time chart during refresh. At this time, the refresh timer 51 (FIG. 7) inside the timing circuit 131 times out, and when refresh is required, the register 52 is set in the timing circuit 131 and the refresh address buffer control signal 18 is set.
6 is outputted to the output QA of the shift register 42 in an on state, and the contents of the refresh address counter 195 are outputted onto the address/data multiplexed bus 1 via the buffer 196 (t ₁ in FIG. 10).
Subsequently, the memory address strobe signal 2 is output in the on state from the output QB of the shift register 42 (t ₂ in FIG. 10), and when the row address strobe signal RAS of the DRAM 151 is turned on, the contents of the refresh address counter are shown
Memory cells inside the DRAM 151 are rewritten. When the time required for rewriting has elapsed, the output QC of the shift register 42 is turned on to reset the register 52, and as a result, the output of the shift register 42 itself is turned off. As a result, the memory address strobe signal 2 and the refresh address buffer control signal 186 are turned off (t ₁₁ in FIG. 10), and at the same time, the counter update signal 18
5 is output and refresh address counter 1
The contents of 95 are updated.

〔Effect of the invention〕

As is clear from the above embodiments, according to the present invention, the timing generation circuit for dynamic operation type random access memory access and the refresh control circuit can be integrated into the main processing unit.
This has the effect of reducing the total amount of hardware in a processing device system that implements a plurality of main memory modules. Furthermore, according to the present invention, since the row address strobe is applied at the address latch timing on the address/data multiplexed bus, the bit width of the address latch can be halved, and the access start can be made earlier, thereby simplifying the hardware. This has the effect of speeding up access.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a diagram showing the configuration of a general processing device system, Figure 3 is a diagram showing the bus configuration of a conventional 8085 microprocessor, and Figures 4 and 5 are diagrams showing the bus configuration of the microprocessor shown in Figure 3. 6 is an operation timing chart of a dynamic operation type random access memory; FIG. 7 is a diagram showing an embodiment of the timing circuit; FIGS. 8 to 10 are the same as those in FIG. 1. 3 is a timing chart of a read operation, a write operation, and a refresh operation in an embodiment. 1...Address/data multiplexed bus, 2...Memory address strobe signal, 3...Memory data strobe signal, 4...Memory read signal, 5...Memory acknowledge signal, 101
... Main processing unit, 102 ... Main memory module,
131...Memory bus control timing circuit, 1
1...Basic processing unit, 151...Dynamic operation type random access memory, 51...Refresh timer, 195...Refresh counter.

Claims (1)

[Claims] 1. Memory bus control when a main processing unit accesses a main memory module connected to the device via a memory bus, which is an address/data multiplexed bus, and whose memory element is a dynamic RAM. In the method, the main processing unit is provided with a memory control means, and when the main processing unit outputs an access request and an access address, the memory control means outputs a first timing signal to control the memory in the main processing unit. Outputs the above access address on the internal address bus to the above memory bus,
On the other hand, when the main memory module receives the first timing signal, it applies the row address in the access address output onto the memory bus to the address input of the dynamic RAM in its own module via a multiplexer, and The strobe signal is turned on, and the column address in the access address is set in the column address register, and then the memory control means outputs a second timing signal to change the internal data bus in the main memory to the internal address. When the main memory module receives the second timing signal, it turns on the column address strobe signal as well as the row address strobe signal of the dynamic RAM in its own module, and also turns on the column address strobe signal. A memory bus control method characterized in that a column address set in a register is applied to an address input of a dynamic RAM via the multiplexer, thereby performing data transfer between a main processing unit and a main memory module. 2. The memory control means is provided with a refresh timer and a refresh counter, and
When the refresh timing signal is output from the refresh timer while the main memory module is not being accessed, the memory control means outputs the contents of the refresh counter to the memory bus as a refresh address; and outputs the first timing signal to the main memory module, the main memory module applies the address on the memory bus to the address input of the dynamic RAM in its own module, and further outputs the row address strobe signal by the first timing signal. By turning on the dynamic
2. The memory bus control method according to claim 1, wherein RAM is refreshed.