JPS57196334A - Memory interface - Google Patents

Memory interface

Info

Publication number
JPS57196334A
JPS57196334A JP7955881A JP7955881A JPS57196334A JP S57196334 A JPS57196334 A JP S57196334A JP 7955881 A JP7955881 A JP 7955881A JP 7955881 A JP7955881 A JP 7955881A JP S57196334 A JPS57196334 A JP S57196334A
Authority
JP
Japan
Prior art keywords
data
ram21
delivered
address
buffers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7955881A
Other languages
Japanese (ja)
Inventor
Takatoshi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7955881A priority Critical patent/JPS57196334A/en
Publication of JPS57196334A publication Critical patent/JPS57196334A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules

Abstract

PURPOSE:To decrease the number of interface lines, by inserting a tristate buffer into a memory and then multiplexing all address data with the proper timing. CONSTITUTION:The interface lines AD0-AD7 of the address data bus are connected in common to the address teminals A0-A7 of the dynamic RAM21- 28 respectively. At the same time, the read enable signal RE' delivered from a processor is supplied to a NAND gate 31 as well as to the control terminal G of each of the tristate buffers 41-48 via an inverter 23. The buffers 41-48 multiple completely all of the address data, read data or write data with the proper timing and therefore perform a control to avoid the superposition of the input and output data. In other words, the data delivered from the data output terminal D0 of the RAM21-28 is delivered to the data input terminal of the RAM21- 28 and the terminals A0-A7 respectively in case the signal RE' is on.
JP7955881A 1981-05-26 1981-05-26 Memory interface Pending JPS57196334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7955881A JPS57196334A (en) 1981-05-26 1981-05-26 Memory interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7955881A JPS57196334A (en) 1981-05-26 1981-05-26 Memory interface

Publications (1)

Publication Number Publication Date
JPS57196334A true JPS57196334A (en) 1982-12-02

Family

ID=13693332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7955881A Pending JPS57196334A (en) 1981-05-26 1981-05-26 Memory interface

Country Status (1)

Country Link
JP (1) JPS57196334A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144854A (en) * 1983-10-07 1985-07-31 エセツクス・グル−プ・インコ−ポレイテツド Input/output system
JPS6326753A (en) * 1986-07-21 1988-02-04 Hitachi Ltd Memory bus control method
JPS63137465A (en) * 1986-11-28 1988-06-09 Fujitsu Ltd Semiconductor integrated circuit
JPS6479850A (en) * 1987-09-21 1989-03-24 Fujitsu Ltd Effective using method for bus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50103947A (en) * 1974-01-14 1975-08-16
JPS50125646A (en) * 1974-03-20 1975-10-02

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50103947A (en) * 1974-01-14 1975-08-16
JPS50125646A (en) * 1974-03-20 1975-10-02

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144854A (en) * 1983-10-07 1985-07-31 エセツクス・グル−プ・インコ−ポレイテツド Input/output system
JPH0473180B2 (en) * 1983-10-07 1992-11-20 Essex Group
JPS6326753A (en) * 1986-07-21 1988-02-04 Hitachi Ltd Memory bus control method
JPH0450625B2 (en) * 1986-07-21 1992-08-14 Hitachi Ltd
JPS63137465A (en) * 1986-11-28 1988-06-09 Fujitsu Ltd Semiconductor integrated circuit
JPS6479850A (en) * 1987-09-21 1989-03-24 Fujitsu Ltd Effective using method for bus

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