JPS575143A - Communicating method of multimicroprocessor system - Google Patents

Communicating method of multimicroprocessor system

Info

Publication number
JPS575143A
JPS575143A JP7925280A JP7925280A JPS575143A JP S575143 A JPS575143 A JP S575143A JP 7925280 A JP7925280 A JP 7925280A JP 7925280 A JP7925280 A JP 7925280A JP S575143 A JPS575143 A JP S575143A
Authority
JP
Japan
Prior art keywords
transmitting
microprocessor
memories
memory
receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7925280A
Other languages
Japanese (ja)
Other versions
JPS593776B2 (en
Inventor
Shigeru Kokaji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP7925280A priority Critical patent/JPS593776B2/en
Publication of JPS575143A publication Critical patent/JPS575143A/en
Publication of JPS593776B2 publication Critical patent/JPS593776B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning

Abstract

PURPOSE:To perform arithmetic processing at a high speed and with high reliability, by enabling each microprocessor to obtain information on another microprocessor from its own receiving memory. CONSTITUTION:In a system consisting of microprocessor units MPU each provided with a transmitting memory and a receiving memory on a bus and a communication controller connected to respective transmitting and receiving memories, the contents of the transmitting memory of each microprocessor are all cleared and then while information is written in only specific addresses of the transmitting memory from its own microprocessor, writing in other addresses by another microprocessor is inhibited; and the communication controller reading and ANDs the contents of the same addresses of the transmitting memories of all MPUs to write the result in the same address of the receiving memories of all MPUs, and executes them successively to writing the contents, written in the transmitting memories of the respective MPUs, in respective receiving memories. Therefore, the MPUs are operated simultaneously.
JP7925280A 1980-06-12 1980-06-12 Communication method in multi-microprocessor system Expired JPS593776B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7925280A JPS593776B2 (en) 1980-06-12 1980-06-12 Communication method in multi-microprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7925280A JPS593776B2 (en) 1980-06-12 1980-06-12 Communication method in multi-microprocessor system

Publications (2)

Publication Number Publication Date
JPS575143A true JPS575143A (en) 1982-01-11
JPS593776B2 JPS593776B2 (en) 1984-01-26

Family

ID=13684654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7925280A Expired JPS593776B2 (en) 1980-06-12 1980-06-12 Communication method in multi-microprocessor system

Country Status (1)

Country Link
JP (1) JPS593776B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63314668A (en) * 1987-06-17 1988-12-22 Mosutetsuku:Kk Transfer system for memory mapped data
JPH09212471A (en) * 1996-01-30 1997-08-15 Nec Corp Device and method for parallel processing program execution

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63314668A (en) * 1987-06-17 1988-12-22 Mosutetsuku:Kk Transfer system for memory mapped data
JPH09212471A (en) * 1996-01-30 1997-08-15 Nec Corp Device and method for parallel processing program execution

Also Published As

Publication number Publication date
JPS593776B2 (en) 1984-01-26

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